JPS5832512B2 - Manufacturing method of junction field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a junction field effect transistor (abbreviated as J-FET) having good high frequency characteristics.

The feature of this J-FET is that it is a voltage-controlled element, and compared to bipolar elements, the temperature characteristics of the drain current are negative, so it does not cause thermal runaway and there is less worry about secondary damage. .

Other advantages of the J-FET include (a) since it uses majority carriers, there is no carrier accumulation effect and the switching speed is fast;

(b) It can be used near the saturation velocity of the carrier, so
High frequency operation can be expected.

The above is well known.

Therefore, taking the comb-shaped J-FET as an example, we aim to increase its frequency and output while ensuring its basic characteristics such as high voltage amplification factor μ and mutual conductance gm, as well as its excellent drain current saturation characteristics. The requirements for this will be explained using the longitudinal sectional view shown in FIG.

In the figure, 1 is a reshaped silicon substrate, 2 is an n-type epitaxial growth layer (hereinafter abbreviated as shrimp layer) formed on the n+ type silicon substrate 1, and 3 is a J- layer consisting of the n-type shrimp layer 2.
The drain layer of the FET, 4 is a field oxide film formed on the n-type epitaxial layer 2, 5 is a silicon nitride film (Si3N, film)
or silicon oxide film (SIO2 film), 6 is gate diffusion region, I is source diffusion region, 8 is aluminum (AJ)
An electrode made of a membrane is shown.

Necessary matter - The cutoff layer wave number fT of the comb-shaped J-FET is approximately given by the following equation, as in the case of bipolar elements.

TA is when the carrier runs in the channel area. while, TB is when charging capacitance between source and gate while, TO is capacitive charging between gate and drain time, shows.

This running time TA is determined by the shrimp layer 2 forming the drain layer 3.
J-F with high resistance and under the condition of high bias voltage.
When the ET is operated, the thickness of the shrimp layer 2 is almost completely depleted, so that the time taken for carriers to pass through the shrimp layer 2 at a saturation speed is approximately equal to the time.

Therefore, one way to reduce this transit time TA is to use a low resistance shrimp layer 2 and suppress the expansion of the depletion layer under the required gate bias voltage condition. When using the resistive layer 2, the pinch-off voltage vP increases, so in order to obtain good diode type characteristics, the distance W between the gates must be adjusted.

- It is necessary to reduce 〇.

This indicates that in order to increase the frequency and output of the J-FBT, it is necessary to establish a technology for forming a highly fine pattern as a manufacturing process, similar to bipolar transistors.

Requirements In order to shorten the charging times TB and TO, it is necessary to form the gate diffusion layer 6 and the source diffusion layer 7 as shallowly as possible and with high concentration diffusion to reduce their junction capacitance and their series resistance.

Requirement No. 3: To obtain high voltage amplification μ, mutual conductance gm, and excellent drain current saturation characteristics, J-
It is necessary to increase the source area per unit gate area of the FET, so-called high density and high integration.

The direction of the manufacturing technology for the three items necessary to increase the high frequency and high output of the J-FET mentioned above is the same as the direction of the manufacturing technology for the conventional high frequency and high output bipolar transistor.
-FETs also have different problems than bipolar transistors.

In other words, in the case of J-FETs, there is no difficulty in controlling the base width using the double diffusion method, which was an important factor in controlling the characteristics of bipolar transistors. Although the breakdown voltage was not so necessary, in the case of JFET, there is approximately BVGDO: μBVs between the source-gate breakdown voltage BVSGO and the gate-drain breakdown voltage BVGDO.
However, there is a difficult problem in that it requires the above-mentioned fine pattern, high density, and high breakdown voltage between source and gate.

By the way, the technology for forming high-fine patterns necessary for the conventional manufacturing process of high-frequency, high-output bipolar transistors involves the use of an oxide film or Si3 used as a diffusion mask.
The so-called Washed Emitter process uses the interface between the N4 film and the silicon semiconductor layer as it is as a mask interface during metallization processing.
There is a so-called composite mask method in which base and emitter contact holes are simultaneously highly finely patterned before emitter impurity diffusion.

A manufacturing process for manufacturing a high frequency, high output J-FET using these bipolar transistor manufacturing techniques will be described with reference to longitudinal sectional views shown in FIGS. 2a to 2d.

As shown in FIG. 2a, first, an n-type epitaxial layer 2 is grown on an n+-type silicon substrate 1, and a field oxide film 4 is formed on the n-type epitaxial layer 2 as a bottom film.

Bonding pads for the source and gate electrodes are provided on the field oxide film 4, so in order to reduce the capacitance caused by the bonding pads and the field oxide film 4, the thickness of the oxide film 4 must be Moderately thick.

On the other hand, since this field oxide film 4 is used to create a mask used when diffusing impurities necessary for forming source and gate diffusion regions, this field oxide film 4
If the film thickness is large, the amount of side etching due to selective etching during mask creation increases, making it difficult to create a mask with a highly fine pattern.

Therefore, taking these two contradictory conditions into consideration, the film thickness is set to a required value.

Next, as shown in FIG. 2, by using a composite mask method, a diffusion window is created in the field oxide film 4 to diffuse each impurity required to form the gate and source diffusion regions, and this impurity diffusion window A silicon nitride film (Si3N4 film) 10 required for making a mask for gate impurity diffusion is formed on the n-type epitaxial layer 2 and the field oxide film 4, and this Si3N4 film 10 is formed on the S t 3 N4 film 10.
A CVD oxide film 9 is formed by a chemical vapor deposition (CVD) method used for patterning.

Furthermore, as shown in FIG. 2C, in order to remove the Si3N4 film 10 and the CVD oxide film 9 within the gate impurity diffusion window by etching, the CVD oxide film is etched using a mask with a pattern larger than the gate impurity diffusion window. 9 and S
The i3N4 film 10 is removed and impurities are diffused from the gate impurity diffusion window to form a p+ type agate diffusion region 6.

At this time, the effective inter-gate interval wG-G is a side diffusion that is approximately equal to the diffusion depth of the gate diffusion region 6 from both sides of the inter-gate interval wG-G during composite mask patterning that simultaneously forms gate and source impurity diffusion windows. (
Reduction △w due to Side Diffusion
It will be minus G-G.

Therefore, in order to reduce the effective inter-gate spacing wG-G,
It is possible to increase the diffusion depth of the gate diffusion region 6 so that the reduction amount ΔwG−G due to side diffusion increases, but in this case, as the diffusion depth increases, the junction capacitance of the gate diffusion region 6 increases. As the voltage increases, it becomes necessary to increase the thickness of the shrimp layer 2 in order to maintain the gate-drain breakdown voltage, both of which are contrary to the direction of increasing the frequency of J-FETs.

Subsequently, as shown in FIG. 2d, similarly to the formation of the gate diffusion region 6, the Si3N4 film 10 within the source impurity diffusion window is
Then, the CVD oxide film 9 is removed, and a group III impurity such as phosphorus is diffused from this diffusion window to form an n+ type source diffusion region I.

If the junction depth of this source diffusion region 7 is deepened to increase the side diffusion component, the series resistance between the source and gate can be reduced and the mutual conductance gm can be increased. As increases, the source diffusion region 7
Since the withstand voltage between the high concentration gate diffusion region 6 and the high concentration gate diffusion region 6 rapidly decreases, there is a problem in that it is difficult to optimize the process conditions in such a manufacturing process. A J-FET that requires high concentration and shallow diffusion in the source diffusion region 7 as well as the diffusion region 6.
There is a serious problem in that it is contradictory to the direction of higher frequencies.

This invention was made in view of the above-mentioned problems, and is
- The purpose is to adopt a manufacturing process that uses selective oxidation during the manufacturing process of FET, and to increase the frequency of its characteristics.

Hereinafter, an embodiment of the method for manufacturing a comb-shaped J-FET according to the present invention will be described with reference to FIG. 3a=h.

The vertical cross-sectional views shown in FIGS. 3a and 3b are Si3N4 film 1 for making a mask used in the selective oxidation and gate impurity diffusion steps.
The first step of forming a film of 0 is shown.

In this step, first, as shown in FIG. 3a, an n-type epitaxial layer 2 is grown on an n+ type silicon substrate 1, and this shrimp layer 2
A field oxide film 4 is formed thereon.

The thickness of the field oxide film 4 is determined in consideration of reduction in capacitance and side etching amount, as described in FIG. 2a.

Next, openings are provided at required locations in the field oxide film 4 to expose the strip layer 2 required for forming an active gate region, which will be described later.

Subsequently, as shown in FIG. 3, an SI3N4 film 10 with a CVD oxide film 9 as an underlying film is formed on the exposed shrimp layer 2 and field oxide film 4 by the CVD method.

FIGS. 3C and 3D show that using the Si3N4 film 10,
Gate and source masks required to form the gate contact region and source contact region 11.12
The second step of creating a composite mask consisting of
Figure C is a plan view of the composite mask, and Figure 3d is a longitudinal sectional view taken along the line DD shown in Figure 3C.

When creating this composite mask, a new CVD oxide film (not shown) is formed on the 513N4 film 10, and this CVD oxide film (not shown) is formed on the 513N4 film 10.
It can be formed by either a phosphoric acid etching method using a mask formed of a D oxide film or a plasma etching method.

The vertical cross-sectional view shown in FIG. 3e shows the first step of gate diffusion in which a p+ type boron diffusion layer 13 is formed in the shrimp layer 2 by boron diffusion or boron ion implantation with low acceleration energy using the above composite mask. The third step is shown.

In this process, when the boron diffusion layer 13 is formed by a diffusion method, this first step of gate diffusion is performed only by a boron deposition process at a low temperature so that the boron diffusion layer 13 has a high concentration and a shallow junction depth. That's fine.

The boron concentration distribution form during this boron deposition process is that in the high concentration region near the surface of the shrimp layer 2, the concentration is close to the boron solid solubility of about 1 x 1020/- and approximates the complementary error distribution. In the low concentration region within 2, the distribution approximates a step distribution due to the influence of the concentration dependence of the boron diffusion coefficient.

The vertical cross-sectional view shown in FIG. 3f shows gate and source mask 1.
Selective oxidation (SOP) using a composite mask consisting of 1.12
) process to form the solicon oxide film 14 is shown.

Here, the state of the boron diffusion layer 13 in this SOP process will be explained.

The boron concentration distribution in the boron diffusion layer 13 after this SOP treatment etc. is based on the boron distribution coefficient c3 between silicon and silicon oxide film.
Since i/Cs1o2 is usually smaller than 1, boron in the shrimp layer 2 is out-diffused into the silicon oxide film 14 as shown in Fig. 4a.
The shape is as shown in the boron concentration distribution map.

In the figure, tsio2 indicates the thickness of the silicon oxide film 14, x-o indicates the interface between the shrimp layer 2 and the silicon oxide film 14, and XiG indicates the junction depth of the gate diffusion layer 13.

Approximately, from the surface y-o of the shrimp layer 2 before SOP treatment shown in the boron concentration distribution diagram in Figure 4, boron having a step distribution at the time of boron deposition has a diffusion coefficient at the oxidation treatment temperature and oxidation treatment. SOP
Junction depth X of gate diffusion layer 13 after processing.

is given by the following equation.

Here, Q is the total boron concentration with a step distribution at the time of deposition, CB is the boron concentration in the shrimp layer 2, and m is the silicon layer thickness tsi of the shrimp layer 2 that reacts when forming the silicon oxide film 14 and this oxidation. Ratio to the film thickness tsio2 of the film 14,
si/jsi.

2 and usually has a value of about 0.4.

In addition, B is based on the variation law of the silicon oxide film (
Parabolic Law), it is a constant term determined by oxidation conditions such as oxidation temperature.

By optimizing this oxidation condition, as can be seen from equation [1], the junction depth XjG of the gate diffusion layer 13 in the shrimp layer 2 can be kept almost constant with respect to the diffusion time, that is, the oxidation treatment time. However, the silicon oxide film 14 can be formed.

Although the effective inter-gate spacing wG is reduced by the lateral growth during the formation of the silicon oxide film 14, the lateral junction depth of the gate diffusion layer 13 can be made almost constant as described above. , by controlling the SOP processing time, the effective inter-gate interval WG-G can be controlled with high precision.

In addition, the boron concentration in the gate diffusion layer 13 after the SOP process decreases due to the out-diffusion effect of boron into the silicon oxide film 14, so the boron concentration at this time is determined by the source-gate breakdown voltage and gate Although it is necessary to control it to a required value in consideration of the diffusion layer series resistance, this control can also be performed by controlling the SOP processing conditions in the same way as controlling the effective inter-gate distance WG-G.

The vertical cross-sectional view shown in FIG.
5 shows the fifth step of forming 5.

In this step, first, the gate mask 11 consisting of the 5iaN film 10 and the underlying CVD oxide film 9 is removed by etching to expose the gate contact region 16.

As this etching removal method, it is also possible to use a plasma etching method using a photoresist mask.Also, a new thin CVD oxide film is formed on the entire surface, and the gate mask 11 is exposed using this CVD oxide film. A mask made of the above CVD oxide film is created by patterning it by photolithography as shown in FIG. Membrane 1
Since the silicon oxide film 14 is thinner than the silicon oxide film 14, it is also possible to use a method of lightly etching and removing the silicon oxide film 14 using it as a mask.

As described in FIG.
e) It goes without saying that masks can be used.

Next, in order to lower the contact resistance and gate series resistance of the gate contact region 15, a high concentration boron diffusion process is performed on the exposed contact region as a second stage of gate diffusion to form the gate contact region 15. .

Since this second stage of gate diffusion is a boron deposition process at a low temperature, this process reduces the effective inter-gate distance W formed by optimization control during the SOP process.
O-O is hardly affected.

Further, a boron ion implantation method can also be used for this second stage of gate diffusion.

The vertical cross-sectional view shown in the third figure shows a sixth step in which a source contact region 16 is formed by performing a high concentration diffusion process of n-type impurities such as phosphorus.

In this step, similarly to the step of forming the gate contact region 15, the source mask 12 is etched away to form an exposed source contact region.

When the mask used for this etching removal is made using the oxide film produced in the step of forming the gate contact region 15, the method for removing the gate mask 11 described above is exactly the same.

Next, the exposed source contact region is filled with n such as phosphorus.
A source contact region 16 is formed by performing a high concentration diffusion process of type impurities.

The high concentration diffusion treatment performed at this time is based on the gm and μ of the J-FET.
This is an important manufacturing process that determines characteristics such as , and source-to-gate breakdown voltage.

This source-gate breakdown voltage is, as mentioned earlier, SOP
It is almost determined by the impurity concentration of the gate diffusion layer 13 under the silicon oxide film 14 formed during processing.

Although it is unavoidable to some extent that the breakdown voltage between the source and gate is reduced due to the contact between the source diffusion region and the gate diffusion region due to the finer patterns and higher integration accompanying the higher frequency of J-F BT, the method according to the present invention In this case, the gate contact region 15 is treated with a high concentration diffusion treatment to reduce the gate contact resistance and the gate series resistance, and the contact portion between the source contact region 16 and the gate diffusion layer 13 is formed using SOF.
Since the boron concentration in the silicon oxide film 14 can be reduced to a low concentration by the gettering effect during the treatment, there is an advantage that the breakdown voltage between the source and the gate can be set to a relatively high value.

Aluminum film electrodes 17 are provided at the source contact portion, gate contact portion, and other required locations of the J-FET device created through such a process, and the J-FET device is
Complete the ET element creation.

As detailed above, in the present invention, the selective oxidation method is used to form the gate diffusion region in the J-FET manufacturing process, so the depth of the diffusion layer can be kept almost constant regardless of the diffusion time, and the desired depth can be maintained. Not only can a highly concentrated and shallow diffusion region be obtained, but also the effective inter-gate interval can be adjusted without considering the depth of these diffusion layers, making it easy to reduce the effective inter-gate interval.

[Brief explanation of the drawing]

Figure 1 is a vertical cross-sectional view showing an example of a conventional comb-shaped J-FET, and Figures 2 a to d are respectively conventional high-frequency, high-output J-FETs.
Longitudinal cross-sectional views showing the manufacturing process for making the ET, FIGS.
- A vertical cross-sectional view showing an example of the FET manufacturing method, FIG. 3 C is a plan view corresponding to the vertical cross-sectional view shown in FIG. 3 d, and FIGS. 4 a and b are boron concentration distribution diagrams during SOP treatment. It is. In the figure, 1 is an n+ type silicon substrate, 2 is an n-type epitaxial growth layer, 3 is a J-FET drain layer, 4 is a field oxide film, 5 is a silicon nitride film or silicon oxide film, 6 is a gate diffusion region 7 is a source Diffusion regions, 8 and 17 are electrodes, 9 is a CVD oxide film, 10 is a silicon nitride film, 11 is a gate mask, 12 is a source mask, 13 is a gate diffusion layer, 14 is a silicon oxide film, 15 is a gate contact region, Reference numeral 16 indicates a source contact region. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. First and second gate contact portions separated from each other on a surface portion of an epitaxially grown silicon layer of a first conductivity type formed on a main surface of a highly conductive silicon substrate of a first conductivity type. A silicon nitride film is selectively formed on a portion where a region is to be formed and on a portion where a source contact region is to be formed with a predetermined interval between the first and second gate contact regions. A first step of forming
Using the silicon nitride film as a mask, impurities of a second conductivity type are introduced into the surface portion of the epitaxially grown silicon layer between the first and second gate contact regions and the source contact region to diffuse gate diffusion. A second step of forming a shallow high concentration impurity region of the second conductivity type to form a layer, selectively oxidizing the high concentration impurity region on the surface of the epitaxially grown silicon layer using the silicon nitride film as a mask. a third step of forming a silicon oxide film thereon and using the high concentration impurity region pushed under the silicon oxide film as a gate diffusion layer; The silicon nitride film on the portion where the gate contact region is formed is removed and impurities of the second conductivity type are introduced into these portions to form the first and second impurities of the second conductivity type connected to the gate diffusion layer. a fourth step of selectively forming a gate contact region, and removing the silicon nitride film on a portion of the surface portion of the epitaxially grown silicon layer where the source contact region is to be formed, and forming a first conductivity type in this region. A method for manufacturing a junction field effect transistor, comprising a fifth step of selectively forming a source contact region of a first conductivity type by introducing an impurity. 2. The method of manufacturing a junction field effect transistor according to claim 1, wherein the high concentration impurity region in the second step is formed by an ion implantation method.