JPS5828753B2 - Method of manufacturing vertical field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a vertical field effect transistor with good output and gain characteristics.

Generally, field effect transistors intended for high output have a vertical structure.

It has been found that when attempting to construct the channel region of this structure using a GaAs-based mesa-like region, there are the following drawbacks.

That is, a mesa-shaped region is formed on a semiconductor substrate by a GaAs layer, and buried layers of, for example, GaAs are formed on both sides of the mesa-shaped region.
When epitaxially growing a layer or the like again, if the mesa-shaped region is formed of GaAs, the reproducibility of the growth of the buried layer will be extremely poor.

The present invention provides a manufacturing method that improves the reproducibility of buried layer growth.

In order to achieve this object, in the present invention, the mesa-shaped region is mainly composed of a GaAlAs layer.

The present invention will be described in detail below using examples.

FIG. 1 shows an embodiment of the present invention, in which a is an overhead view and b is a sectional view taken along line A-1.

The channel 8 of n-type GaO, gAl□, 1As is formed in the vertical direction (thickness direction) as shown in the figure, and the channel 8 of n-type GaO, gAl
As region 4 is a gate.

When a reverse bias is applied between the source electrode 6, the drain electrode 7, and the gate electrode 50, a depletion layer is expanded in the channel 8 as shown by the broken line in FIG. 1, and conductivity modulation is performed.

The region 3 provided between the gate and the p-type GaAs layer 40 is made of lightly doped n-type GaAs, and has the purpose of reducing the junction capacitance between the gate and the drain and improving frequency characteristics.

For this purpose, it is desirable to make the carrier density of this buffer layer as low as possible, but it should be lower than the carrier density of at least a part of the region constituting the channel.

The field effect transistor shown in FIG. 1 is manufactured as follows.

First, an n-type GaAs substrate (n~1016CrrL-
3) N-type Ga□ by liquid phase epitaxial growth method on 1
, gAlOoI As 2 is grown.

Ga1-XAIXAs (0<x<:1) is used because the reproducibility of the second stage growth (growth after mesa etching) is poor if AI is not included.

This growth requires the growth of multiple layers, and the boundaries of the multiple layers must intersect with the mesa-etched sides, but Ga
With As, the reproducibility of this growth becomes poor.

Also, keeping the ratio of A1 small can reduce the mobility
This is to keep it close to aAs.

The thickness of this epitaxial layer is 2μ.

This epitaxial layer is then mesa-etched to a depth that reaches the substrate, leaving only the channel region 8.

The channel is formed in a strip shape, and the width of this strip region is 0.
The thickness was suppressed to 8 μm.

In order to improve the reproducibility of this width, H
The composition of the etching solution was controlled within 1% using 2SO4:H2O22H2O-4:1:1, and the time and temperature were also precisely controlled.

Etching is performed to a depth greater than the thickness of the epitaxial layer 2, but here the etching was performed by 2.5 μm from the surface.

After etching, the univar is carefully cleaned and a gate region is formed.

For this purpose, a continuous liquid phase epitaxial growth method is used, and n
-Grow GaAs layer 3 and p-GaAs layer 4.

Generally, growth does not proceed on Ga1-XAIXAs, so growth proceeds only in the area where mesa etching was previously performed, resulting in the structure shown in FIG. 1.

By controlling the growth time, the surface of the growth layer and GaO,
7A10. The surface of HAs 2 was rubbed to obtain a flat surface as shown in the figure.

A source electrode 6 and a gate electrode 5 are formed by a lift-off method, and a drain electrode 7 is formed to complete the device.

The width of the source electrode was 0.5 μm and the width of the gate electrode was 5 μm.

When the field effect transistor fabricated through the steps described above was operated, good results were obtained with a power gain of 6 dB and an output of 1 W at 8 GHz.

FIG. 2 shows another embodiment of the invention.

The device of this example is made in the same manner as in the Sagi example, but in the second stage growth method, n-GaAs3, p-type GaAs3
Three layers of As4 and nGaAs11 are grown.

This is to reduce the thickness of the p-type GaAs layer 4 and shorten the effective gate length.

According to this method, the gate length can be reduced to 1 micron or less, and the frequency characteristics can be improved.

A reverse bias is supplied to the gate region 4 through a p-type GaAs region 10 formed by diffusion.

The subsequent electrode attachment is the same as in the previous embodiment.

The carrier density of the n-type GaAs 11 is also reduced as in the buffer region, which helps to keep the capacitance between the source and gate low.

FIG. 3 shows another embodiment of the present invention, in which a region with low carrier concentration is provided within the channel.

Here, in the first growth, n
Form Gao, 9Al(,, 1As 12, n-GaAs
13. Grow n-type GaO, gAlo, IAs 14.

When a reverse bias is applied between the source and gate, the depletion layer becomes n
- It mainly spreads in the GaAs region 13, but since this region is very narrow, efficient conductivity modulation is possible.

Further, by providing this region, the carrier concentration of the source and drain and the carrier concentration of the conductivity modulation region in the channel can be selected independently.

This allows the expansion of the channel depletion layer to be adjusted without increasing the source/drain resistance.

It is also advantageous because the effective length of the channel can be determined independently of the gate width.

Therefore, a vertical field effect transistor with excellent high frequency characteristics was obtained.

FIG. 4 shows another embodiment of the present invention, in which n-type Ga□, gAlO6IAs 2, n-type G
AAs15, n-type GaoBA10, and 2As16 were continuously grown.

After the second growth, n-type Gao, 8AI□-2As l
5 is etched to expose the n-type GaAs 15 and reduce the contact resistance of the source electrode.

As described above, the vertical field effect transistor of the present invention is an amplifying element that is excellent not only in high frequency characteristics but also in output characteristics, and its practical effects are extremely large.

Note that in the above example, n-type GaAs was grown in the first growth.
Although we have described the case where GaAlAs is grown directly on the substrate, it is better to grow the channel layer after growing the n-type GaAs for better thickness reproducibility.

In this case, mesa etching may be performed to a depth that reaches the grown n-type GaAs.

Furthermore, in the second growth, an example in which GaAs was mainly grown was described, but GaAlAs may be used instead.

In particular, since it is desirable that the buffer region has a low carrier density, better results can be obtained by growing GaAlAs.

In the above embodiment, the boundary between the buffer region and the gate region is
The figure shows the boundary between the n-type GaAs of the first growth and the n-type substrate, but this happens because the growth on the GaAs proceeds including the mesa-etched side surface, This is because the growth of the GaAlAs sidewalls begins once this has settled down, and if the growth of the gate region is started before this point, the result will be as shown in the figure of the embodiment.

Therefore, these boundaries do not necessarily have to coincide.

Furthermore, although the embodiment has mainly been described using GaAlAs as the growth mask, it is also possible to use an oxide film as the growth mask, and if this is applied to the embodiment shown in FIG.
The final etching step becomes unnecessary.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, in which a is an overhead view;
b is a sectional view taken along line AA'. FIGS. 2 to 4 are cross-sectional views showing another embodiment of the present invention, in which a is a cross-sectional view of the device at the time when growth has been completed, and b is a cross-sectional view of the device, respectively. 1: GaAs substrate, 2: n-Ga□, gAlo, IAs
Layer 3: buffer layer, 4: p-GaAs layer, 5, 6, and 7 are gate, source, and drain electrodes, respectively, and 8: channel.

Claims (1)

[Claims] 1 GaAlA on a GaAs substrate with a predetermined conductivity type
At least one layer of the s-layer is formed to have the same conductivity type as the substrate, such that the uppermost layer is made of GaAlAs, and a mesa-shaped region of a predetermined width is etched into the formed semiconductor layer, and the mesa-shaped semiconductor region is etched. At least two layers, a first semiconductor layer having a carrier density lower than that of the mesa-shaped semiconductor region and a second semiconductor layer constituting the gate region, are formed on both sides by epitaxial growth of GaAs or GaAlAs. 1. A method for manufacturing a vertical field effect transistor, comprising the steps of: