JPS6332273B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a field effect transistor.

[Prior art]

As a field effect transistor, we will use a gallium arsenide MES field effect transistor (hereinafter referred to as gallium arsenide MES field effect transistor).
This will be explained using GaAsFET (abbreviated as GaAsFET) as an example.

This type of GaAsFET is generally capable of operating in the sub-millimeter wave band when a gate electrode of about 1 micron in length is formed on a GaAs semiconductor, and is attracting attention as an ultra-high frequency transistor or an ultra-high speed integrated circuit. ing. This transistor consists of an n-type GaAs semiconductor layer epitaxially grown on a semi-insulating GaAs substrate, and a gate electrode forming a shot barrier on this n-type semiconductor layer, and ohmic electrodes as a source and a drain on both sides of the gate electrode. It has a structure with

In order to shorten the switching time of this transistor, it is necessary to shorten the gate length, increase the electron concentration in the channel region, and increase the transconductance gmo of the transistor. However, shortening the gate length in the former case is said to be difficult due to the limitations of microfabrication technology, and it is difficult to obtain a gate length of 0.3 microns or less. As the concentration increases, the drop voltage of the gate shot barrier decreases, so there is an upper limit to this electron concentration, and n-type GaAs semiconductors with an electron concentration of 10 ¹⁶ to ^{10 17} cm ^-3 are generally used. ing.

Furthermore, if source and drain ohmic electrodes are formed directly on the n-type GaAs semiconductor layer, the characteristics of the transistor will deteriorate due to the source series resistance Rs caused by the contact resistance of the electrodes and the resistance of the semiconductor layer between the source and gate. . In other words, the transconductance gm of a transistor is gm=
It is expressed as gmo/(1+Rs gmo), and a large source series resistance Rs reduces the transconductance gm of the transistor and increases the maximum switching time.In particular, the resistance between the source and gate is When the layer is thin, the resistance tends to be high due to the effect of a depletion layer (hereinafter abbreviated as surface depletion layer) due to the surface states of the semiconductor layer, which is the main cause of the source series resistance Rs.

FIG. 1 and FIGS. 2a to 2c show a conventional GaAsFET employing a structure for reducing the source series resistance Rs.

Figure 1 shows a GaAsFET with a recessed structure.This GaAsFET is made by first forming a sufficiently thick n-type GaAs semiconductor layer on a semi-insulating substrate 1 by epitaxial growth or ion implantation, and then etching it into a suitable thickness. A channel layer 2 whose thickness is controlled so as to obtain a threshold voltage, and a source region 4 and a drain region 5 on both sides thereof are obtained. Next, on the channel layer 2, a gate electrode 3 made of a metal layer forming a shot barrier junction with GaAs is formed, and a source region 4 and a drain region 5 are formed.
A source electrode 6 and a drain electrode 7, which form ohmic contact with GaAs, are respectively provided on top.

In the structure shown in FIG. 1, the source region 4 and drain region 5 are close to the gate electrode 3 and are sufficiently thick, so that the influence of the surface depletion layer is small and the source series resistance Rs can be reduced. be.
However, in this structure, after forming the n-type GaAs semiconductor layer, trenching or recessing is performed to control the thickness of the channel layer 2. Therefore, in order to reduce the source series resistance Rs, the n-type When the GaAs semiconductor layer is made thicker, it is necessary to increase the amount of digging, so-called recess, which makes controlling the thickness of the channel layer 2 extremely difficult. Since the thickness is thin, it is difficult to control the threshold voltage of the transistor using a recess, making it unsuitable for high integration.

In addition, Figure 2 a to c show high electron concentration.
The manufacturing process of a GaAsFET having a structure including a source and drain region made of an n ⁺ GaAs semiconductor layer is shown. First, a channel layer 2 is formed by ion implantation on a semi-insulating GaAs substrate 1, and this channel layer A gate electrode 3 is formed on 2 (FIG. 2a),
Next, using this gate electrode 3 as a mask, a source region 8 made of an n ⁺ semiconductor layer is formed by ion implantation.
and forming a drain region 9 (FIG. 2b),
Further, on each of these regions 8 and 9, a source electrode 6,
A drain electrode 7 is formed thereon (FIG. 2c).

In the structure according to steps a to c of FIG. 2,
Since the source region 8 and drain region 9 made of the n ⁺ semiconductor layer are close to the gate electrode 3 and the electron concentration is sufficiently high, the influence of the surface depletion layer is small, and the source series resistance Rs is also reduced. It is possible. However, in this structure, n ⁺
Since the source region 8 and drain region 9 made of semiconductor layers are located close to the gate electrode 3, the gate-source and gate-drain distances lgs and lgd (=0.1 to 0.3 μm), and if the distance lgs is long, the source series resistance Rs will increase due to the effect of the surface depletion layer, and if the distance lgd is short, the drain breakdown voltage will decrease and the capacitance between the gate and source will increase. The drawback was that the maximum switching time increased.

[Summary of the invention]

In view of these drawbacks of the conventional method, the present invention involves forming source and drain regions, etching and digging between these regions, and then implanting ions into the trenched areas to form a channel region. By doing so, it is possible to provide a field effect transistor that operates at high speed and high frequency, has small variations in device characteristics, and is suitable for high integration.

[Embodiments of the invention]

Hereinafter, one embodiment of the method of the present invention will be described in detail with reference to FIGS. 3a to 3d and FIG. 4.

In this embodiment method, first, as shown in FIG. 3a, ions are implanted into a predetermined portion of the semi-insulating GaAs substrate 11, for example, as shown in FIG.
By implanting 2×10 ¹³ cm ^-2 of Si ions with an acceleration energy of 170 KeV, a source region 18 and a drain region 19 made of an n ⁺ semiconductor layer are formed.
And by heat-treating this at, for example, 800℃,
From this n ⁺ semiconductor layer, regions 14 and 15 of the n semiconductor layer, which have substantially the same electron concentration as the channel layer, are formed by thermal diffusion. The impurity distribution in the depth direction in the source and drain regions 18 and 19 at this time is as shown in FIG.

Next, as shown in FIG. 3b, source and drain regions 18 and 19 made of the n ⁺ semiconductor layer are formed.
The sandwiched region is etched by chemical etching or dry etching to a depth less than the depth of the regions 14 and 15 made of the n-semiconductor layer, as shown in FIG. 3c. The channel layer 12 is formed by ion implantation, for example, by implanting 1×10 ¹² cm ^-2 of Si ions at an acceleration energy of 50 KeV, as shown in FIG. As a result, as shown in FIG. 4, the maximum concentration depth of the impurity distribution in the channel layer 12 can be made to match the maximum concentration depth of the source and drain regions 18 and 19. After that, the gate electrode 13, the source electrode 16, and the drain electrode 17
is formed as shown in FIG. 3d.

Therefore, in the method of this embodiment, since the channel is not dug after being formed, it is possible to reduce variations in the threshold voltage of transistors and manufacture highly integrated circuits with high yield. Since the channel region is formed by digging later, the source resistance Rs due to the surface depletion layer can be reduced, and since there is no need to place the source and drain regions made of n ⁺ semiconductor layers very close together, the drain withstand voltage can be sufficiently increased. The capacitance between the gate and source can be reduced. Also n ⁺
Source and drain region 1 made of a semiconductor layer
Since the n semiconductor layer regions 14 and 15 are formed between the n ⁺ semiconductor layers 8 and 19 and the channel layer 12, the diffusion shown in FIG. The heat treatment conditions are significantly relaxed compared to a structure in which the channel layer 2 is placed close to the channel layer 2, and highly integrated circuits with small variations in device characteristics can be manufactured with high yield.

In the above embodiments, the semiconductor material is
Although the case using GaAs has been described, it is of course applicable to field effect transistors using silicon or other semiconductor materials.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, after the source and drain regions are formed, a semiconductor having almost the same impurity concentration as the channel layer is formed by thermal diffusion from the high concentration semiconductor layer constituting the source and drain regions. After each region is formed, these regions are dug across each semiconductor region, and ions are implanted into the dug portion to form a channel region.
A field-effect transistor that can reduce source resistance and capacitance between the gate and source without losing uniformity of device characteristics within the wafer surface, operates at high speed and high frequency, and is suitable for high integration with small variations in device characteristics. There are benefits to be gained.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing a conventional recess structure GaAsFET, and Figures 2 a to c are conventional examples.
3A to 3D are sectional views sequentially illustrating the manufacturing process of an n ⁺ layered GaAsFET, and FIG. FIG. 3 is an explanatory diagram showing impurity distribution in the depth direction. DESCRIPTION OF SYMBOLS 11... Semi-insulating GaAs substrate, 12... Channel region, 13... Gate electrode, 14... N semiconductor layer region, 16 and 17... Source and drain electrode, 18 and 19... Source and drain region.

Claims (1)

[Claims] 1. A step of implanting impurity ions onto one main surface of a semi-insulating semiconductor substrate to selectively form source and drain regions made of a highly concentrated semiconductor layer, and heat-treating the substrate to form each of the highly concentrated semiconductor layers. A process of forming semiconductor regions each having an impurity concentration almost the same as that of the channel layer by thermal diffusion from the layer, and trenching between these regions astride each semiconductor region to a depth equal to or less than the depth of the semiconductor region. and a step of forming a channel region by implanting ions into the dug portion so that the depth at which the impurity distribution reaches a maximum concentration matches the depth at which the maximum concentration of the impurity distribution occurs in the source and drain regions. A method for manufacturing a field effect transistor, comprising the steps of: forming a gate electrode on the channel region, and forming source and drain electrodes on each of the source and drain regions, respectively.