JPS62296566A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To lower source resistance and drain resistance, keeping the steepness of the profile of a channel section, and to obtain sufficient breakdown strength of gate by providing the processes of high-concentration ion implantation, surface etching and low-concentration ion implantation. CONSTITUTION:A low resistance layer 3 with a steep profile is formed through first ion implantation, minimizing acceleration voltage, a gate-forming section is etched selectively, the thickness of the low resistance layer in the gate-forming section is thinned, acceleration voltage is minimized, and ions are implanted, thus shaping an active layer 4 only by a etched section only in the interior of the low resistance layer in the gate-forming section. Source-drain electrodes 5, 6 are attached after annealing, the N<+>layer of the gate-forming region is recess-etched, and a gate electrode 7 is annexed. Accordingly, source resistance and drain resistance are lowered because the profile of an impurity is steep because of the active layer formed at low acceleration voltage and there is the low resistance layer 3 up to a section just close to the electrode, and breakdown strength of the gate is high because the gate electrode is not brought into contact with the low resistance layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a low noise field effect transistor that can be used in a high frequency band.

Conventional technology Field-effect transistors are devices in which carriers travel by drift caused by an electric field, so they are thought to be advantageous in high-frequency bands, and have been actively developed in recent years. The channel layer is made using a phase epitaxial substrate or ion implantation method, but ion implantation method has advantages such as good in-plane distribution, steep profile, and low cost, and there are already many practical examples. .

The conventional field effect transistor as described above will be explained below with reference to the drawings.

FIG. 3 schematically shows a conventional method for manufacturing a field effect transistor.

In FIG. 3, 8 is a semi-insulating substrate, 9 is a resist, 1o
113 is the part where ions were implanted at a low concentration, page 113 is a part where ions were implanted at a high concentration, 12 is the source electrode, 13 is the drain electrode, and 14 is the gate electrode. Since it is necessary to lower the drain resistance and also have sufficient gate breakdown voltage, the device isolation region is usually first protected with a resist and an active layer is selectively formed by ion implantation (Figure 3a).Then, the source/drain resistance is lowered. For this purpose, ion implantation is performed at a high concentration only in the source/drain formation region (Fig. 3b), and after annealing, a source and drain electrode is attached (Fig. 3C). Recess etching is performed, a gate electrode is attached, and the field effect transistor is completed (Figure 3d).

Problems to be Solved by the Invention However, in the above configuration, the source resistance and drain resistance become high because the impurity concentration is not high near the gate. In addition, when increasing the amount of ion implantation to lower the source resistance and drain resistance, the steepness of the impurity profile cannot be obtained, and the voltage amplification factor is 1 m near the pinch-off voltage.
This has the disadvantage that the gate breakdown voltage also decreases.

In view of the above drawbacks, the present invention provides a field effect transistor that can lower the source resistance and drain resistance while maintaining the steepness of the profile of the channel portion, and provide a sufficient gate breakdown voltage, and a method for manufacturing the same. .

Means for Solving the Problems In order to solve the above-mentioned problems, the field effect transistor of the present invention has a structure in which a high concentration layer exists right up to the low concentration layer to which the gate electrode is attached, and a manufacturing method thereof. The process consists of three steps: (1) high-concentration ion implantation, zero surface etching, and (2) low-concentration ion implantation.

Operation With this configuration, the present field effect transistor has low resistance right up to the gate, so the source resistance and drain resistance are reduced, and low noise can be achieved in the high frequency band.

Embodiment 5 On the following pages, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 schematically shows the manufacturing process of a field effect transistor in a first embodiment of the present invention.

In FIG. 1, 1 is a semi-insulating substrate, 2 is a resist 3
4 is a portion where ions are implanted at a high concentration, and 4 is a portion where ions are implanted at a low concentration.However, the portion where double implantation of low concentration and low concentration is performed is a high concentration region, so they are indicated as such. 5 is a source electrode, 6 is a drain electrode, and 7 is a gate electrode.

Figure 2 shows the main parts.

Lowering the surface resistance while maintaining the steepness of the impurity profile is advantageous for high frequency field effect transistors. In order to achieve this, in the present invention, the acceleration voltage is minimized and the first ion implantation is performed to create a low resistance layer with a steep profile (Figure 1a).Then, the gate forming area is selectively etched. Then, the thickness of the low-resistance layer in that area is further thinned (Figure b). When the accelerating voltage is again minimized and the ion 6 page implantation is performed, the above-mentioned etching is carried out only in the depths of the low-resistance layer in the gate formation area. (C) of the same figure. After annealing, source and drain electrodes are attached (d in the same figure), NGFJ in the gate formation region is recessed and etched, and a gate electrode is attached (e in the same figure) to complete this transistor. Transistors made in this way: ■The active layer is formed at a low acceleration voltage, so the impurity profile is steep; ■The low resistance layer exists right up to the gate electrode, so the source and drain resistances are low. low, ■
Since the gate electrode is not in contact with the low resistance layer, the gate breakdown voltage is high, and the T2GHz noise figure is also 1.7.
It was below dB.

Effects of the Invention As described above, the present invention can realize a field effect transistor capable of low-noise operation by providing the steps of high-concentration ion implantation, surface etching, and low-concentration ion implantation, and its practical effects are as follows. There is something big.

[Brief explanation of drawings]

7 Hoeno FIG. 1 is a manufacturing process diagram of a field effect transistor according to an embodiment of the present invention, FIG. 2 is a sectional view of a main part of the same field effect transistor, and FIG. 3 is a manufacturing process diagram of a conventional field effect transistor. 1... Semi-insulating GaAs substrate, 3...
...High concentration ion implantation region, 4...Low concentration ion implantation region.

Claims (3)

[Claims] (1) A field effect characterized in that a low resistance layer is formed on the surface of the active layer with a gate electrode in between, and a source electrode and a drain electrode are formed on the surface of each low resistance layer, respectively. transistor. (2) The field effect transistor according to claim 1, wherein the low resistance layer is thicker at a distance from the gate electrode than near the gate electrode. (3) a step of performing a first ion implantation on the surface of the substrate; a step of forming a recess on the surface of the ion-implanted portion;
a step of performing second ion implantation into the substrate through the recess; a step of selectively removing the layer immediately below the recess into which the first ion implantation was performed; A method for manufacturing a field effect transistor, comprising the step of forming a gate electrode in a second ion implantation region.