JPS6223175A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the lowering of yield on manufacture of a MESFET due to the defective controllability of the thickness of a channel layer by providing a process, in which the ions of an N-type impurity for forming a channel for the MESFET are implanted, and a process in which the ion-implanted impurity is diffused through heat treatment. CONSTITUTION:The ions of sulfur (S<+>) are implanted into a semi-insulating GaAs substrate 1, a recessed section is shaped through etching, and the ions of arsenic are implanted to form N<+> type GaAs layers 7 and an N-type GaAs layer 8. The N<+> type GaAs layers 7 function as source-drain regions in a MESFET and the N-type GaAs layer 8 serves as a channel layer. Source-drain electrodes 9 are formed, the whole is sintered, and a gate electrode 10 is shaped, thus manufacturing the MESFET. The N<+> type GaAs layers as the source-drain regions are formed thickly by diffusing S, thus lowering source resistance, then improving the characteristics of the FET.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a Schottky barrier gate field effect transistor using a compound semiconductor. Semiconductor Schottky barrier gate field effect transistor (ME)
As one of the methods of manufacturing SFET), semi-insulating G
a A s substrate with one layer of buffer GaAs, n-type Ga
There is a method using a substrate on which As and n+ type Ga Ats are sequentially epitaxially grown. ME of recess structure using conventional epitaxial substrate according to Fig. 3
The SFET manufacturing method will be explained. In Figure 3(a), 3
1 is a semi-insulating GaAs substrate, 32 is a non-doped GaAs buffer layer, 33 is an n-type GaAs layer which becomes a channel of a field effect transistor, and 34 is a material for reducing contact resistance and source resistance. It is an n+ type GaAs layer to reduce the size, and is a semi-insulating GaAs layer.
This is a cross-sectional view showing that layers 32 to 34 are epitaxially grown on a substrate 31.

Using this substrate, the n+ type GaAs layer in the gate formation region 36 is first selectively removed, as shown in FIG. 3(b). (referred to as recessed structure) After that A u
Source/drain electrodes 36 made of G e /"N i /A u are formed, and finally, for example, T i /
After the gate electrode 37 made of P t /A u is formed, element isolation is performed by mesa etching, and the ME
SFET is manufactured. Although the conventional manufacturing method has been briefly described above, one problem with this method is the controllability of the thickness t of the channel layer shown in FIG. 3(b). This is one of the most important parameters that determines the threshold voltage and drain current of MESFET,
The n+ type Ga of the gate formation region 36 is removed by etching.
Not only is it difficult to uniformly remove the As layer 34 over the entire surface of the substrate, but it also requires great controllability in thinning the n-type Ga As layer 33 to a desired thickness t in the depth direction. Therefore, a good yield cannot be expected.

Problems to be Solved by the Invention The present invention attempts to solve the problem of the low production yield of MESFETs due to the poor controllability of the thickness t of the channel layer in the conventional example described above.

Means for Solving the Problems In order to realize a structure equivalent to that of the conventional example with a high yield, the present invention has developed an n+ type GaAg layer and an n
This method forms a GaAs type GaAs layer directly on a semi-insulating GaAs substrate, and involves a step of ion-implanting a high concentration of n-type impurity into the MESFET formation region, and a step of ion-implanting the GaAs substrate in the gate electrode formation region. The basic steps are a step of etching the surface layer to a predetermined depth, a step of ion-implanting n-type impurities for forming a MESFET channel, and a step of performing heat treatment to diffuse the ion-implanted impurities.

According to the present invention, the thickness of the MESFET channel layer can be controlled by ion implantation conditions, and control by etching is essentially not included, so the manufacturing yield of MESFETs can be dramatically improved compared to the conventional method. becomes possible. In addition, the thickness of the n+ type GaAs layer in the source region increases due to the diffusion of impurities in the region into which ions have been implanted at a high concentration.
It is expected to improve the characteristics of

Example A first embodiment of the present invention will be described with reference to FIG.

In FIG. 1 (-), reference numeral 1 indicates a semi-insulating GaAs substrate, and the cross section of the substrate is shown. Also, only the MESFET formation region is shown in the figure. First, MES
The ion beam 2 for zero ion implantation, which introduces high-concentration impurities into the entire FET formation region by ion implantation, is as follows:
Ion implantation is performed using sulfur ions (S+) at an acceleration energy of 120 to 170 KeV and an implantation amount of 1 x 10147 to 1 x 10 A.

3 indicates a region where S+ ions are implanted. Next, as shown in FIG. 1(b), Ga of the gate electrode formation region 4 is
The surface layer of the As substrate is etched to a depth of 3,000 to 500 mm to form recesses, and then MESFE is etched.
Ions are implanted into the entire surface of the T formation region to form a channel of the FET. The ion beam 6 contains silicon ions (si
+), the acceleration energy was 40 to 90 Kev, and the injection amount was 4 to 6 x 101 Si. In the figure, 6 is Si
Indicates + implanted area. After that, it was heated to 850°C in an arsenic (88) atmosphere.

When annealing is performed for 20 minutes, the ion-implanted S and Si become electrically activated, and the n+ type GaAs layer 7 and n
A G a As layer 8 is formed. The n+ type GaAs layer 7 is the source/drain region of the MESFET, and the n type GaAs layer 7 is the source/drain region of the MESFET.
The As layer 8 becomes a channel layer. Since S ions are used to form the source/drain regions, S ions are used during annealing.
The thickness of the n+ type GaAs layer is 1 μm due to the diffusion of
(Fig. 1 (C)).

After this, AuGe/N i /A
After forming source/drain electrodes 9 made of u and sintering, a gate electrode 10 made of Ti/Pt/Au is formed to produce a MESFET. Through the above steps, a MESFET with a structure equivalent to that of the conventional example is formed, but the n+ type GaAs in the source and drain regions is
Since the layer is formed thicker than before due to the diffusion of S, the source resistance is reduced and the characteristics of the FET are improved.

S used for forming source/drain regions in this example
Due to diffusion effects and solid solubility, the carrier (electron) concentration near the substrate surface is lower than when using St. Therefore, in order to further improve the characteristics of the FET, it is necessary to Better results can be obtained by double ion implantation of S and St instead of only S.

A second embodiment of the present invention will be explained with reference to FIG.

This embodiment particularly reduces the gate length, the distance between the source and drain regions, and the gate electrode resistance (Rq
), and aims to further improve the high frequency characteristics of the MESFET.

FIG. 2 (,) is the same as FIG. 1, and shows a step in which ions of high concentration S or S and Si are ion-implanted into the MESFET formation region. Next, as shown in the second figure, a first insulating film (for example, a film thickness of 300 mm) is applied over the entire surface of the substrate.
The S102 film 11 and the GaAs layer in the gate electrode forming region 4 are sequentially etched away to a predetermined depth by normal photoetching to form a recess.

Thereafter, St ion implantation is performed to form a channel of the FET (FIG. 2(C)). Subsequently, a second insulating film 12 (for example, a Si3N4 film) is deposited on the entire surface of the substrate at a thickness of about 30 μm (Fig. 2(d)), and the second insulating film 12 is etched perpendicularly to the substrate surface by reactive ion etching of CF4. When etching is performed in the direction, the second layer is etched only on the side wall of the recess.
The insulating film can be left behind (FIG. 2(e)).

Thereafter, source/drain electrodes 9 and gate electrodes 10 are formed to produce an FET. If such a process is used, when the width of the recess shown in FIG. 2(b) is 1 μm, the width L′ in FIG. 2(e) will be approximately 0.5 μm, and the gate length of the FET can be shortened. . Furthermore, when forming the gate electrode, since the area around the recess is insulated from the n+ type GaAs layer 7 by the first insulating film 11 and the second insulating film 12, the gate electrode 1Q is formed around the entire recess. It can be formed covering the gate electrode, and the resistance of the gate electrode can be lowered. Actually, the gate electrode 10 is
From the state shown in Figure 2 (,), T i /P t is applied to the entire surface of the substrate.
/A After depositing u, a cut-out pattern for the gate electrode is formed using photoresist, and after plating with Au, Ti/P
It was produced by selectively removing t/Au. As a result, the metal film thickness of the gate electrode could be increased to 2 μm, and the gate resistance could be reduced.

Effects of the Invention According to the present invention, the thickness of the channel layer of a recessed FET can be controlled by ion implantation conditions, and does not essentially include control by etching.
The manufacturing yield of SFET can be greatly improved, and the effect is significant.

In addition, the thickness of the n+ type GaAs layer in the source/drain region can be increased by utilizing sulfur diffusion through annealing, reducing the source resistance and increasing the thickness of the FET.
The high frequency characteristics of can be improved. Further, according to the second aspect of the present invention, the gate length, the source-drain interval, and the gate resistance are reduced, and the present invention greatly contributes to improving the characteristics and yield of FETs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a process diagram for explaining the first embodiment of the present invention in terms of an element cross section, FIG. FIG. 3 is a process diagram showing a cross section of an element for explaining a conventional example. 1...Semi-insulating GaAs substrate, 2...
...8 ion beam, 3...B ion implantation region, 4...gate electrode formation region, 6...
...31 ion beam, 6...S biion implantation region, 7...n+ type GaAs layer,
8...N-type GaAs layer, 9...
Source/drain electrode, 1o...gate electrode,
11...first insulating film, 12...second
insulation film. '-10111k? 111111 L F-' Soil Figure 2 Figure 2

Claims (6)

[Claims] (1) A step of implanting high-concentration impurity ions into a field effect transistor formation region on the surface of a semiconductor substrate, and etching and removing a surface layer of the semiconductor substrate in a gate electrode formation region of the field effect transistor to a predetermined depth. a step of implanting impurity ions at a low concentration into the entire surface of the field effect transistor formation region; and a step of performing heat treatment to diffuse the impurity in the region where the high concentration impurity ion implantation has been performed. Method of manufacturing the device. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made of a III-V compound semiconductor, and the impurity ion implantation at a high concentration is performed using sulfur ions. (3) The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a III-V compound semiconductor, and the high concentration impurity ion implantation is performed by double ion implantation of sulfur ions and silicon ions. manufacturing method. (4) A step of implanting high concentration impurity ions into a field effect transistor formation region on the surface of the semiconductor substrate, a step of forming a first insulating film over the entire surface of the semiconductor substrate, and a step of forming a gate electrode formation region of the field effect transistor. Said first
etching away the insulating film and the surface layer of the semiconductor substrate to a predetermined depth to form a recess; implanting low concentration impurity ions into the entire surface of the field effect transistor formation region; a step of performing heat treatment after forming the second insulating film to diffuse impurities in the region where the high-concentration impurity ion implantation has been performed; and a step of leaving the second insulating film only on the sidewalls of the recess. A method for manufacturing a semiconductor device, characterized in that: (5) The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor substrate is made of a III-V compound semiconductor, and the impurity ion implantation at a high concentration is performed using sulfur ions. (6) The semiconductor device according to claim 4, wherein the semiconductor substrate is made of a III-V compound semiconductor, and the high concentration impurity ion implantation is performed by double ion implantation of sulfur ions and silicon ions. manufacturing method.