JPH1064924A - Semiconductor device and production method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having embedded gate structure and production thereof with which coverage at the edge of a gate electrode is satisfactory and further it is not necessary to add any repair process for removing wafer damage at the time of sputtering. SOLUTION: An embedded gate electrode 17 is formed by forming a semiconductor layer while using a selective epitaxial crystal growth method for the recessed part (ditch part 1a) of a gate electrode forming region, of which the bottom face is composed of an n-AlGaAs etching stopper layer 2 formed by using an epitaxial growth method and the side face is composed of an i-GaAs layer 1 formed by using the epitaxial growth method. Thus, the gate electrode 17 composed of a p-type semiconductor is formed with no gap inside the ditch part 1a along the vertical plane of the i-GaAs layer 1 and the horizontal plane of the n-AlGaAs etching stopper layer 2 worked by dry etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a buried gate electrode in which controllability of a gate length is improved and a buried gate structure is inexpensive. It relates to what is formed in

[0002]

2. Description of the Related Art FIG.
FIG. 1 shows a cross-sectional side view of a conventional semiconductor device having a buried gate structure disclosed in Japanese Patent Publication No. 39-39. In FIG.
5 is a semi-insulating GaAs substrate, 4 is a buffer layer formed on the semi-insulating GaAs substrate 5, 3 is an n-GaAs active layer formed in a predetermined region of the buffer layer 4, and 7 is n of the buffer layer 4. An n ⁺ ohmic contact region formed in a region where the -GaAs active layer 3 is not formed;
N-AlGaAs formed on the GaAs active layer 3
The etching stopper layer 1 is an i-GaAs formed in a predetermined region of the n-AlGaAs etching stopper layer 2.
The s layer 10 is a gate electrode made of WSi formed so that its lower part is in contact with the n-AlGaAs etching stopper layer 2, 8 is a SiO 2 insulating film formed on the i-GaAs layer 1, and 13 is On the gate electrode 10, an Au upper gate electrode base film 11 serving as a plating power supply layer
Upper gate electrode 15 made of Au formed through
Is a drain electrode made of an AuGe-based metal formed on the n ⁺ ohmic contact region 7, and 16 is a source electrode made of an AuGe-based metal also formed on the n ⁺ ohmic contact region 7.

FIG. 14 is a sectional side view showing a manufacturing process of a semiconductor device having the above-described structure.
The manufacturing method will be described with reference to FIG.

First, on a semi-insulating GaAs substrate 5, a buffer layer 4 and an n-Ga
An As layer (active layer) 3, an n-AlGaAs etching stopper layer 2, and an i-GaAs layer 1 are sequentially formed (FIG. 1).
4 (a)), a photoresist 6 is formed on a predetermined portion of the i-GaAs layer 1 and patterned, and the obtained pattern is used as a mask to ion-prescribe a predetermined portion of n using an ion implantation / annealing method. -GaAs layer (active layer) 3, n-A
lGaAs etching stopper layer 2, i-GaAs layer 1
To n ⁺ ohmic contact region 7 (FIG. 14)
(b)).

Next, after the photoresist 6 is removed,
An SiO2 insulating film 8 is deposited on the entire surface of the semiconductor substrate (FIG. 14).
(c)) Subsequently, patterning is performed using the photoresist 9 as a mask, and SiO 2 existing in a region to be a gate formation portion is formed.
2 Open the insulating film 8 (FIG. 14D).

[0006] Next, as shown in FIG.
Only the portion of the i-GaAs layer 1 exposed at the opening of the iO2 insulating film 8 is selectively removed by dry etching to form a dug portion. At this time, the n-A formed below
The n-Ga etching stopper layer 2 allows n-Ga
The As layer (active layer) 3 is prevented from being etched.

Thereafter, as shown in FIG. 14 (f), a gate electrode (WSi) 10 and an Au upper gate electrode base film 11 serving as a plating power supply layer are deposited on the entire surface of the wafer by a sputtering method. Patterning is performed to obtain a gate shape of a mold.

Subsequently, using the photoresist 12 as a mask,
The upper gate electrode 13 is formed by Au plating (FIG. 14).
(g)) Then, after the photoresist 12 is removed, unnecessary portions of the gate metal (WSi) and the Au upper gate electrode base film 11 are removed by ion milling and dry etching, as shown in FIG. To form a gate electrode.

Thereafter, the S / D of the source / drain electrode formation portion is
The iO2 insulating film 8 is opened using the photoresist 14 as a mask to expose the lower n ⁺ ohmic contact region 7 (FIG. 14 (i)). Using the photoresist 14 as a mask, an AuGe-based A drain electrode 15 and a source electrode 16 made of metal are formed.
(j)), a semiconductor device as shown in FIG. 13 can be obtained.

The semiconductor device constructed as described above has a Schottky gate in which a metal and a semiconductor are in contact with each other, and reversely biases the Schottky barrier to change the width of the space charge region to reduce the flow of carriers. This constitutes a so-called Schottky (barrier) gate field effect transistor to be controlled.

In general, in a field-effect transistor having a recess structure, when a gate electrode is simply formed by sputtering or the like using a mask used for etching at the time of forming a recess, a region between a gate electrode end and a source-drain electrode is formed. Since the surface of the existing semiconductor substrate is exposed, a surface level exists in this region, and the surface depletion layer generated by this surface level does not follow the pulse signal applied to the gate. It is known that a pulse response delay or the like may be caused.

However, a recess is formed as described above, a gate metal or the like is deposited on the entire surface of the wafer by sputtering or the like, and an unnecessary portion of the metal layer is later removed to form a gate electrode. In a built-in gate type field effect transistor, the semiconductor substrate existing in the region between the gate electrode end and the source / drain electrode is relatively in close contact with the gate metal. There is an advantage that the mobility of carriers can be improved by suppressing the depletion layer from affecting the channel modulation immediately below the gate.

[0013]

The conventional semiconductor device and the method of manufacturing the same are constructed as described above. The semiconductor layer in the region between the gate electrode end and the source / drain electrode is relatively in close contact with the gate metal. Therefore, in this region, the surface depletion layer can be prevented from affecting the channel modulation immediately below the gate, and the carrier mobility can be improved. Therefore, a gap is formed between the gate metal and the semiconductor substrate at the edge of the buried gate electrode due to the limit of the coverage by the sputtering, thereby improving the controllability of the gate length and the reliability. There is a problem that it is difficult to improve, and it is difficult to perform fine processing such as shortening the gate length.

Further, when sputtering is performed on the semiconductor substrate immediately below the gate, the substrate may be damaged and DC characteristics may be degraded. Therefore, high-temperature annealing or the like at 400 ° C. or more is performed after sputtering to improve DC characteristics. Need
There has been a problem that the manufacturing process is complicated and the manufacturing cost is high.

In a semiconductor substrate formed by the epitaxial crystal growth method, the carrier concentration of the semiconductor layer in contact with the side surface of the buried gate electrode can be easily made low or undoped, and a high gate reverse breakdown voltage can be obtained. Can be easily obtained,
Since the epitaxial crystal growth method is an expensive manufacturing method and the cost is higher than using an inexpensive implantation / annealing method, it is necessary to manufacture a semiconductor device having a buried gate structure having a high gate reverse breakdown voltage at a low cost. There was a problem that it was difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is necessary to provide a good coverage at the edge portion of the gate electrode and to add a repair process for removing substrate damage at the time of sputtering. It is an object of the present invention to provide a semiconductor device having a buried gate structure and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device capable of inexpensively manufacturing a field effect transistor having a buried gate structure having a high gate reverse breakdown voltage by using an implantation / annealing method, and a method of manufacturing the same.

[0018]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a source / drain region comprising a first conductivity type epitaxial crystal growth layer formed on a semi-insulating compound semiconductor substrate; A region, an intrinsic semiconductor layer formed on the first conductivity type epitaxial crystal growth layer, the epitaxial semiconductor growth layer having an opening in the channel region, and a first semiconductor layer selectively grown in the opening of the intrinsic semiconductor layer. And a gate electrode made of a two-conductivity type epitaxial crystal growth layer.

According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the gate electrode formed of the second conductivity type epitaxial crystal growth layer has a smaller bandgap as the upper part thereof is formed. It has what it has.

According to a third aspect of the present invention, there is provided a semiconductor device, comprising: a source / drain region formed of a first conductivity type epitaxial crystal growth layer formed on a semi-insulating compound semiconductor substrate; A second conductivity type region formed on the channel region of the first conductivity type epitaxial crystal growth layer and serving as a gate electrode at a central portion thereof; and a second conductivity type region between the second conductivity type region and the source / drain region. And an epitaxial crystal growth layer having an intrinsic semiconductor region in the region.

According to a fourth aspect of the present invention, in the semiconductor device, a semi-insulating compound semiconductor substrate having a concave portion in a portion where a channel region is formed, and an impurity is implanted into the concave portion of the semi-insulating compound substrate. Formed by obliquely implanting impurities using a mask formed to surround the channel region and the channel region, and connected to the channel region inside the semi-insulating compound substrate below the mask. A source / drain region to be formed, an intrinsic semiconductor region formed by remaining a semi-insulating compound semiconductor substrate region below the mask when the impurity is obliquely implanted, and a gate electrode formed in the recess. It is.

A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein a gate metal layer is provided on the gate electrode.

According to a sixth aspect of the present invention, in a method of manufacturing a semiconductor device, a first semiconductor device is provided on a semi-insulating compound semiconductor substrate.
A step of epitaxially growing a conductive semiconductor layer;
A step of epitaxially growing an intrinsic semiconductor layer on the first conductive type epitaxial layer; and opening a region of the intrinsic semiconductor layer corresponding to a portion where a gate electrode is to be formed. A step of exposing the layer and a step of forming a gate electrode by epitaxially growing a semiconductor layer of the second conductivity type on the exposed semiconductor layer of the first conductivity type.

According to a seventh aspect of the present invention, in a method of manufacturing a semiconductor device, a first semiconductor device is provided on a semi-insulating compound semiconductor substrate.
A step of epitaxially growing a conductive semiconductor layer;
A step of epitaxially growing a semiconductor layer of the second conductivity type on the epitaxial layer of the first conductivity type; and etching of the semiconductor layer of the second conductivity type using a mask to remove unnecessary portions thereof, thereby obtaining the second semiconductor layer. Forming a gate electrode made of a two-conductivity type semiconductor layer, and epitaxially growing an intrinsic semiconductor layer over the entire surface of the substrate using the mask.
Forming an intrinsic semiconductor region connected to the gate electrode.

According to a method of manufacturing a semiconductor device according to an eighth aspect of the present invention, an insulating film is formed on a semi-insulating compound semiconductor substrate, and an opening is formed in a predetermined portion of the insulating film using a mask. Forming a recess in the semi-insulating compound semiconductor substrate by etching using the mask and the insulating film in which the opening is formed as a mask, removing the mask, removing the recess, and forming the recess. Forming a channel region in the recess by etching the insulating film using a mask covering the insulating film in the vicinity of the recess and leaving the insulating film in the vicinity of the recess; and implanting impurities using the remaining insulating film as a mask. Forming a sidewall made of a conductor on the side surface of the insulating film remaining in the vicinity of the concave portion and the side surface of the concave portion, and masking the remaining insulating film and the sidewall on the side surface of the concave portion. As the impurity is tilted implantation, but with the remaining insulating film, and a step of at below the side wall forming the source and drain regions to be connected to the channel region.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the sixth to eighth aspects, a gate metal layer is formed on the gate electrode. It has a process.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 shows a first embodiment of the present invention.
FIG. 11 is a diagram showing a planar pattern of a semiconductor device characterized by forming a buried gate structure by using a selective epitaxial growth method. FIG. 2 is a cross-sectional side view taken along the line AA ′ in FIG. In the figure, 5 is a semi-insulating GaAs substrate, 4 is this semi-insulating GaAs substrate 5
A buffer layer 3 formed on the buffer layer 4 is formed in a predetermined region of the buffer layer 4 and has a thickness of 200 to 2000 Å and an impurity concentration of 10 ^{17 to} 5 × 10 ¹⁸ / cm ^3. , 7 are n− of the buffer layer 4.
The n ⁺ ohmic contact region 2 formed in the region where the GaAs active layer 3 is not formed is the n-GaAs
An n-AlGaAs etching stopper layer formed on the active layer 3 and having a thickness of 50 to 1000 Å and an impurity concentration of 10 ¹⁶ to 10 ¹⁸ / cm 3.
An i-GaAs layer formed in a predetermined region of the AlGaAs etching stopper layer 2, an SiO2 insulating film 8 formed on the i-GaAs layer 1, and a 15 formed on the n ⁺ ohmic contact region 7 A drain electrode 16 made of AuGe-based metal, a source electrode 16 made of AuGe-based metal also formed on the n ⁺ ohmic contact region 7, and a drain electrode 17 made of, for example, p ⁺ -InGaAs
/ P ⁺ -GaAs / p-AlGaAs (p ⁺ layer concentration: 1
It is a gate electrode made of a p-type semiconductor formed at (× 10 ^{18 to} 5 × 10 ¹⁸ / cm ³ ).

As described above, the field effect transistor having the pn junction in the gate region is a JFET (Junction Field).
d Transistor), which controls the drain current by reverse-biasing the pn junction and controlling the width of the space charge region immediately below the gate.

Next, a method of manufacturing the semiconductor device will be described with reference to a sectional side view showing the manufacturing method of FIG. First,
Using a method similar to the conventional method, a photoresist 9 is formed on the semiconductor substrate formed by the epitaxial crystal growth method through the steps shown in FIGS. 14 (a) to 14 (d), as shown in FIG. Then, only the i-GaAs layer 1 exposed in the portion opened by the photoresist 9 is selectively removed by dry etching using a chlorine-based gas to form a dug portion 1a.

Thereafter, the photoresist 9 is removed, and FIG.
As shown in FIG. 2B, the MOCV is formed in the dug portion 1a formed using the SiO2 insulating film 8 having an opening as a mask.
Using D (Metal Organic Chemical Vapor Deposition) or CBE (Chemical beam Epitaxy), p-AlGaAs, p ⁺ -GaAs, p ⁺ -InG
aAs is sequentially formed using selective epitaxial growth to form a gate electrode 17 made of a p-type semiconductor. As described above, the gate electrode 17 is moved from below to the p-AlGa
By depositing As, p ⁺ -GaAs and p ⁺ -InGaAs in the order of decreasing band gap, the ohmic contact can be achieved without performing an annealing process between the uppermost p ⁺ -InGaAs and a wiring metal to be formed later. Can be obtained.

Thereafter, using the same method as in the prior art, an opening is made in the SiO 2 insulating film 8 in the source / drain electrode formation portion using the photoresist 14 as a mask (FIG. 3C). Au / Evaporation / Lift-off method
Drain electrode 15 and source electrode 16 made of Ge-based metal
Is formed (FIG. 3D), and a semiconductor device as shown in FIG. 2 can be obtained.

As described above, according to the first embodiment, the bottom surface portion of n formed by the epitaxial growth method is used.
A concave portion of the gate electrode formation region (a dug portion 1a) composed of an AlGaAs layer 2 and a side surface portion composed of an i-GaAs layer 1 formed by an epitaxial growth method.
Then, the buried type gate electrode 17 is obtained by forming a semiconductor layer by using the selective epitaxial crystal growth method.
Along the vertical plane of the GaAs layer 1 and the horizontal plane of the n-AlGaAs layer 2, a gate electrode 17 made of a p-type semiconductor is formed without any gap in the dug portion 1a.
The controllability and reliability of the gate length are improved, and fine processing such as shortening of the gate length can be performed without deteriorating device characteristics.

Further, since the gate electrode is not formed by using the sputtering method as in the prior art, there is no damage associated with the formation of the gate by sputtering. Therefore, a process such as an annealing process for repairing the damage is performed later. No need to do it.

Further, since the p-type semiconductor is used for the buried gate electrode 17, the maximum value of the saturation drain current can be improved as compared with a conventional metal / semiconductor Schottky junction type semiconductor device having the same pinch-off voltage. it can.

Further, when the gate electrode 17 is formed, p-AlGaAs, p ⁺ -GaAs
s, by carrying out the order to the deposition of p ⁺ -InGaAs and the band gap becomes smaller, the top p ⁺ -InGaA
Ohmic contact can be easily obtained without annealing between s and the wiring metal to be formed thereon.

Embodiment 2 FIG. 4 is characterized in that a buried gate structure is formed by using the selective epitaxial growth method according to the second embodiment, and the semiconductor device shown in the first embodiment is further developed to achieve higher performance. FIG. 3 is a diagram showing a planar pattern of a semiconductor device according to the present invention. FIG. 5 is a cross-sectional side view taken along the line BB ′ of FIG. In the figure, reference numeral 17 denotes p ⁺ -InGaAs / p ⁺ -
GaAs / p-AlGaAs (p ⁺ layer concentration:> 1 × 10
¹⁸ / cm ³ ), a gate electrode made of a p-type semiconductor, 11 is an Au upper gate electrode base film, 13 is an upper gate electrode made of Au, 18 is an SiO2 insulating film 8 and one of the gate electrodes 17. A SiO2 insulating film formed so as to cover the portion.

Next, a method of manufacturing the semiconductor device will be described with reference to a cross-sectional side view showing the manufacturing method of FIG. First,
As in the first embodiment, through the steps up to FIG.
A buried gate electrode 17 made of a mold semiconductor is formed. Next, as shown in FIG. 6A, an SiO2 insulating film 18 is deposited on the entire surface of the wafer, and a photoresist 19 is used as a mask.
An opening is formed in the SiO2 insulating film 18 above the gate electrode 17 (FIG. 6B).

Next, after removing the photoresist 19, as shown in FIG. 6C, an Au upper gate electrode base film 11 serving as a plating power supply layer is deposited on the entire surface of the wafer by sputtering.

Thereafter, the photoresist 12 is patterned so that a T-shaped gate shape is obtained, and then the upper gate electrode 13 is formed by Au plating using the photoresist 12 as a mask. (FIG. 6 (d)).

Next, after removing the photoresist 12, the Au upper gate electrode base film 11 serving as a plating power supply layer is formed.
Unnecessary portions are removed by ion milling using the gate electrode 13 as a mask and processed as shown in FIG. 6E to form gate electrodes (17, 11, 13).

After that, using the same method as in the prior art, the SiO2 insulating film 8 and the SiO2 insulating film 18 existing in the source / drain electrode forming portion are opened using a mask, and then the deposited region is evaporated / lifted off. AuGe by law
By forming the drain electrode 15 and the source electrode 16 made of a system metal (FIG. 6F), a semiconductor device as shown in FIG. 5 can be obtained.

As described above, according to the second embodiment, a semiconductor layer is formed by using a selective epitaxial crystal growth method in a recess in a region where a gate electrode is to be formed by using an epitaxial growth method. Since the gate electrode 17 is formed, the gate electrode 17 made of a p-type semiconductor is formed without a gap in the recessed recess, so that
A structure advantageous in controllability of gate length and reliability can be obtained, and miniaturization processing such as shortening of gate length can be performed without deteriorating device characteristics.

Furthermore, since the low-resistance upper gate electrode 13 is provided on the buried gate electrode 17 made of a p-type semiconductor, it is possible to obtain a junction field-effect transistor having excellent performance in high-frequency operation. Can be.

Embodiment 3 FIG. Next, Embodiment 3 of the present invention
Will be described with reference to FIGS. FIG. 7 is a cross-sectional side view of a semiconductor device according to the third embodiment, wherein a buried gate structure is formed using a selective epitaxial growth method and a method different from that of the first embodiment. In FIG. 7, 20 is, for example,
p ⁺ -InGaAs / p-GaAs (p ⁺ layer concentration: 1 ×
A gate electrode 23 made of a p-type semiconductor formed at 10 ^{18 to} 5 × 10 ¹⁸ / cm ³ ) is provided on both sides of the gate electrode 20.
I-Ga formed using selective epitaxial growth
This is an As layer.

Next, a method of manufacturing the semiconductor device will be described with reference to a sectional side view showing the manufacturing method of FIG. First,
As shown in FIG. 8A, a buffer layer 4 and an n-G layer are formed on a semi-insulating GaAs substrate 5 by an epitaxial crystal growth method.
aAs layer (active layer) 3, n-AlGaAs etching stopper layer 2, and p ⁺ -InGaAs serving as a gate electrode
p-type semiconductor gate electrode 2 formed of s / p-GaAs
0 are sequentially formed, and a SiO2 insulating film 21 is further deposited on the entire surface.

Next, as shown in FIG. 8B, the region where the gate electrode is to be formed is masked with a photoresist 22, and the SiO2 insulating film 21 in the region other than the gate electrode portion is dried using a fluorine-based gas. The photoresist 22 and the remaining SiO2 insulating film 2 are removed by etching.
By using 1 as a mask, only the p-type semiconductor layer gate electrode 20 in a region other than the gate electrode portion is selectively removed by dry etching using a chlorine-based gas (FIG. 8C).

After that, only the photoresist 22 is removed, and as shown in FIG. 8D, the n-AlG layer is formed using the SiO2 insulating film 21 deposited on the gate electrode 20 as a mask.
a-GaAs layer 23 on aAs etching stopper layer 2
Is formed by selective epitaxial growth using MOCVD or CBE. Thereafter, the SiO2 insulating film 21 used as the mask is removed, and as shown in FIG. 8 (e), the p-type semiconductor gate electrode 20 becomes an i-GaAs layer. A shape to be embedded in 23 is obtained.

Next, as shown in FIG. 8F, a photoresist 6 is formed on the p-type semiconductor gate electrode 20, i-GaAs.
Patterning is provided so as to cover the layer 23, and ion implantation and annealing are performed using the photoresist 6 as a mask,
Predetermined portion of n-GaAs layer (active layer) 3, n-AlGa
As etching stopper layer 2, i-GaAs layer 23,
The n ⁺ ohmic contact region 7 is formed.

Finally, as shown in FIG. 8 (g), evaporation / lift-off is performed using the photoresist 6 as a mask to form a drain electrode 15 and a source electrode 16 made of AuGe-based metal. Remove 6
A semiconductor device as shown in FIG. 7 can be obtained.

When the p-type semiconductor gate electrode 20 is formed, p-GaAs, p ⁺ -In
By depositing the semiconductor layers in order of decreasing band gap with GaAs, it is possible to obtain ohmic contact between the uppermost p ⁺ -InGaAs and the wiring metal disposed thereon without performing an annealing process. it can.

According to the semiconductor device formed as described above, the p-type semiconductor gate electrode 2 is formed by using the selective regrowth method.
Since the i-GaAs layer 23 is grown on the surface of the n-AlGaAs layer etching stopper 2 on which 0 is formed, i-GaAs is formed along the vertical plane of the gate electrode 20 made of p-type semiconductor processed by dry etching. Layer 2
3 is formed satisfactorily without any gaps adjacent to the gate electrode 20, a structure advantageous in controllability and reliability of the gate length can be obtained, as in the first embodiment. Also excellent in miniaturization processing. Further, it is possible to form a junction field effect transistor having a buried gate structure having a favorable gate / semiconductor interface without damage during sputtering as in the prior art.

Further, since the p-type semiconductor is used for the gate electrode, there is an effect that the maximum value of the saturated drain current can be improved as compared with the conventional metal / semiconductor Schottky junction semiconductor device having the same pinch-off voltage.

Further, the active layer 3 to the p-type semiconductor gate electrode 20 can be continuously formed on the semi-insulating GaAs substrate, and the semiconductor / gate interface is dry-etched as in the first embodiment. , And no exposure to the air, so that a better semiconductor / gate interface can be obtained, which is very effective in improving reliability.

Embodiment 4 Next, Embodiment 4 of the present invention
Will be described with reference to FIGS. FIG. 9 is characterized in that a buried gate structure is formed by using the selective epitaxial growth method according to the fourth embodiment, and the semiconductor device shown in the third embodiment is further developed to achieve higher performance. 1 is a cross-sectional side view of a semiconductor device to be manufactured. In FIG. 9, reference numeral 24 denotes a gate electrode 20, i-GaAs in which a part of the gate electrode 20 is opened.
The s layer 23 is an SiO 2 insulating film formed on the n ⁺ ohmic contact region 7.

Next, a method of manufacturing the semiconductor device will be described with reference to a sectional side view showing the manufacturing method of FIG. First, in the same manner as described in the third embodiment, through the steps shown in FIGS. 8A to 8F, the i-GaAs layer 23 formed by using the selective epitaxial growth method is formed. A semiconductor device having an embedded gate electrode 20 made of a p-type semiconductor and having an n ⁺ ohmic contact region 7 adjacent to the i-GaAs layer 23 is formed (FIG. 10A).

Next, an SiO2 insulating film 24 is deposited on the entire surface of the wafer, and the insulating film 24 in the gate electrode 20 forming region is opened using a photoresist 25 having an opening in the gate electrode forming region as a mask (FIG. 10B). ). Next, after removing the photoresist 25, as shown in FIG. 10C, an Au upper gate electrode base film 11 serving as a plating power supply layer is deposited on the entire surface of the wafer by a sputtering method.

Thereafter, the photoresist 12 is patterned so as to obtain a T-shaped gate shape with the photoresist 12, and then Au plating is performed using the photoresist 12 as a mask. An upper gate electrode 13 connected to the ground film 11 is formed (FIG. 10D).

Then, after the photoresist 12 is removed, ion milling is performed using the gate electrode 13 as a mask, and an Au upper gate electrode base film 1 serving as a plating power supply layer is formed.
Unnecessary portions of l are removed and processed as shown in FIG. 10 (e) to form gate electrodes (20, 11, 13).

Thereafter, using the same method as in the prior art, using a mask, the S / D
After opening the iO2 insulating film 24, a drain electrode 15 and a source electrode 16 made of AuGe-based metal are formed by vapor deposition / lift-off method respectively (FIG. 10 (f)) to obtain a semiconductor device as shown in FIG. Can be.

As described above, according to the fourth embodiment, the surface of the n-AlGaAs etching stopper layer 2 on which the p-type semiconductor gate electrode 20 is formed is formed by using the selective regrowth method.
Since the GaAs layer 23 is grown, the i-GaAs layer 23 is formed satisfactorily without any gap adjacent to the gate electrode 20 along the vertical plane of the gate electrode 20 made of p-type semiconductor processed by dry etching. Accordingly, a structure advantageous in controllability and reliability of the gate length can be obtained, and it is also excellent in miniaturization processing such as shortening the gate length. Further, it is possible to form a junction field effect transistor having a buried gate structure having a favorable gate / semiconductor interface without damage during sputtering as in the prior art.

Further, since the p-type semiconductor is used for the gate electrode, there is an effect that the maximum value of the saturated drain current can be improved as compared with a conventional metal / semiconductor Schottky junction semiconductor device having the same pinch-off voltage.

Further, from the active layer 3 to the p-type semiconductor gate electrode 20 can be continuously formed on the semi-insulating GaAs substrate 5, and as in the first embodiment, the semiconductor / gate interface is dry. There is no etching and no exposure to the air, and therefore, a better semiconductor / gate interface can be obtained, which is very effective in reliability.

Furthermore, since the low-resistance upper gate electrode 13 is provided on the buried gate electrode 20 made of a p-type semiconductor, it is possible to obtain a junction field-effect transistor having excellent performance in high-frequency operation. Can be.

Embodiment 5 Next, Embodiment 5 of the present invention
Will be described with reference to FIGS. FIG. 11 shows oblique ion implantation according to the fifth embodiment.
It is sectional side view of the semiconductor device by the manufacturing method characterized by forming a buried gate structure at low cost using the annealing method. In the figure, 26 is an n-layer channel region, 2
Reference numeral 7 denotes an n-layer region formed on both sides of the n-layer channel region 26;
This is a WSi sidewall film made of i.

Next, a method of manufacturing the semiconductor device will be described with reference to a sectional side view showing the manufacturing method of FIG. First, an SiO2 insulating film 8 is deposited on the entire upper surface of the semi-insulating GaAs substrate 5, and the SiO2 insulating film 8 is patterned using a photoresist 9, and the SiO2 insulating film 8 existing in the gate forming portion is formed.
2 After the opening of the insulating film 8, as shown in FIG. 12 (a), dry etching is performed by using the opened photoresist 9 as a mask to form the dug portion 5 in the semi-insulating GaAs substrate 5.
a is formed.

Next, after the photoresist 9 is removed, a photoresist 28 is applied as shown in FIG. 12B, and the photoresist 28 is formed on both sides of the gate buried portion so as to have an overhang shape. Is patterned and dry-etched using the photoresist 28 as a mask to remove the SiO2 insulating film 8. The amount of overhang is desirably equal to or approximately twice the depth of the dug portion 5a.

Next, after the photoresist 28 is removed, as shown in FIG. 12C, the channel region is formed by ion implantation using the SiO 2 insulating film 8 remaining around the gate electrode forming region as a mask. The impurity (Si) serving as a donor is implanted into the region under the condition that the acceleration energy is 50 KeV and the dose is 5 × 10 / cm ^2.
The mold channel region 26 is used.

Subsequently, a WSi layer 29 made of the same WSi as the gate metal is deposited on the entire surface of the wafer (FIG. 12D).
The deposited WSi layer 29 is anisotropically etched by reactive ion etching to leave a WSi sidewall film 30 on both sides of the SiO2 insulating film 8 as shown in FIG.

Thereafter, as shown in FIG.
2 Using the insulating film 8 and the WSi sidewall film 30 formed on both sides thereof as a mask, an impurity is implanted by oblique ion implantation to form an n-layer region 27. The acceleration energy at the time of implanting impurities is such that the implantation profile is n
In order to have a peak in the lower part of the layer channel region 26,
For example, implantation is performed with an acceleration energy of 100 KeV or more and a dose of 5 × 10 ¹² to 1 × 10 ¹³ / cm ² . Further, as shown in FIG. 12 (f), the implantation angle is set at a considerably acute angle so as to be 45 degrees or less, so that the SiO 2
2 In the semiconductor region under the insulating film 8, the n-layer region 27 can be formed in a region below the gate buried portion. Further, the SiO2 insulating film 8 and the WS formed on both sides thereof are formed.
Since the i-side wall film 30 serves as a mask, SiO
2 In the semiconductor region below the insulating film 8, the region from the outermost surface to the side wall portion of the gate buried portion is blocked with impurity ions and is not implanted with impurities, and the region remains semi-insulating. Similarly, almost no impurities are implanted into the n-layer channel region 26 under the gate buried portion.

Subsequently, as shown in FIG. 12 (g), using the photoresist 6 for opening the region for forming the n ⁺ ohmic contact region as a mask, the acceleration energy is 60K.
Impurities (Si) are implanted under the condition of eV and a dose amount of 3 × 10 ¹³ / cm ^2, and after removing the photoresist 6, annealing is performed to activate the implanted impurities, n-layer channel region 26, n-layer region 27, n ⁺
Ohmic contact regions 7 are respectively formed.

Thereafter, as shown in FIG.
And a Au upper gate electrode base film 11 serving as a plating power supply layer are deposited on the entire surface of the wafer by sputtering.

Subsequently, as shown in FIG. 12 (i), the photoresist 12 is patterned so that a T-shaped gate shape is obtained, and Au plating is performed using the photoresist 12 as a mask. To form an upper gate electrode 13.

Subsequently, after removing the photoresist 12, using the upper gate electrode 13 as a mask, a gate metal (WSi) 10 serving as a gate electrode and A serving as a plating power supply layer are used.
Unnecessary portions of the u upper gate electrode base film 11 are removed by ion milling and dry etching, respectively, and the SiO2 insulating film 8 is removed by a hydrofluoric acid solution.
A gate electrode (10, 1) having a structure as shown in FIG.
1, 13, 30) are formed.

Thereafter, AuGe is deposited by a vapor deposition / lift-off method.
By forming the drain electrode 15 and the source electrode 16 made of a system metal (FIG. 12 (k)), a semiconductor device as shown in FIG. 11 can be obtained.

As described above, according to the fifth embodiment, the channel region of the junction field effect transistor having the buried gate structure is formed by using the inexpensive implantation / annealing method. A structure equivalent to that formed by using a growth method can be realized by using an inexpensive ion implantation method, so that manufacturing cost can be reduced.

Further, by forming the source / drain regions by oblique ion implantation using a mask, the semiconductor region on the side wall contacting the buried gate electrode can be made to be a semi-insulating region in a self-aligned manner. As a result, a semiconductor device having a buried gate structure having a high gate reverse breakdown voltage can be easily manufactured.

[0077]

As described above, according to the present invention, the bottom surface and the side surface are formed in the recesses of the gate electrode formation region formed by using the epitaxial crystal growth method by using the selective epitaxial crystal growth method. Since the electrode made of the semiconductor layer is formed, the gate electrode made of the semiconductor is formed without any gap in the recess along the vertical plane and the horizontal plane of the recess, and the controllability of the gate length is improved. In addition, there is an effect that reliability can be improved and miniaturization processing such as reduction in gate length can be performed without deteriorating device characteristics. Further, since the gate electrode is not formed by using the sputtering method as in the related art, there is no damage associated with the gate formation by sputtering, and therefore, it is necessary to perform a process such as an annealing step to repair the damage later. Therefore, the number of manufacturing steps can be reduced, and the cost can be reduced.

Further, when the gate electrode is formed, the band gap is made smaller as the upper portion thereof is formed, so that the gate electrode can be easily formed without annealing treatment with a wiring metal formed on the gate electrode. In this case, an ohmic contact can be obtained, which has the effect of simplifying manufacturing.

According to the present invention, a semiconductor layer of the first conductivity type and a semiconductor layer of the second conductivity type are sequentially stacked on the semi-insulating compound semiconductor substrate by epitaxial growth.
By etching the second conductive type semiconductor layer using a mask and removing unnecessary portions thereof, a gate electrode made of the second conductive type semiconductor layer is formed. Then, the intrinsic semiconductor layer is regrown by an epitaxial growth method to form an intrinsic semiconductor region connected to the gate electrode, so that the intrinsic semiconductor layer is formed along the vertical surface of the gate electrode made of a semiconductor processed by etching. That the gate length is better controllable and reliable, and that miniaturization such as shortening the gate length can be performed without deteriorating device characteristics. effective. Further, since the gate electrode is not formed by using the sputtering method as in the related art, there is no damage associated with the gate formation by sputtering, and therefore, it is necessary to perform a process such as an annealing step to repair the damage later. Therefore, the number of manufacturing steps can be reduced, and the cost can be reduced. Further, since the layers from the active layer to the gate electrode are continuously formed on the substrate, the semiconductor / gate interface is not subjected to etching and exposure to the atmosphere, and thus, a better semiconductor / gate interface is provided. Thus, there is an effect that reliability can be improved.

Further, according to the present invention, the channel region of the junction field effect transistor having the buried gate structure is formed by using an inexpensive implantation / annealing method. A structure equivalent to that formed by using an inexpensive ion implantation method can be realized, and the manufacturing cost can be reduced. Further, by forming the source / drain regions by oblique ion implantation using a mask, the semiconductor region on the side wall portion in contact with the buried gate electrode can be made to be a semi-insulating region in a self-aligned manner. There is an effect that a semiconductor device having a buried gate structure having a gate reverse breakdown voltage can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a diagram showing a plane pattern of a junction field-effect transistor which is a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional side view of the semiconductor device taken along line AA of FIG.

FIG. 3 is a sectional side view showing a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4 is a diagram showing a plan pattern of a junction field-effect transistor which is a semiconductor device according to a second embodiment of the present invention;

5 is a cross-sectional side view of the semiconductor device taken along line BB of FIG. 1;

FIG. 6 is a sectional side view showing a manufacturing step of the semiconductor device according to the second embodiment.

FIG. 7 is a cross-sectional side view of a junction field-effect transistor which is a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a cross-sectional side view showing a manufacturing step of the semiconductor device according to the third embodiment.

FIG. 9 is a sectional side view of a junction field-effect transistor which is a semiconductor device according to a fourth embodiment of the present invention.

FIG. 10 is a cross-sectional side view showing a manufacturing step of the semiconductor device according to the fourth embodiment.

FIG. 11 is a sectional side view of a junction field-effect transistor which is a semiconductor device according to a fifth embodiment of the present invention.

FIG. 12 is a cross-sectional side view showing a manufacturing step of the semiconductor device according to the fifth embodiment.

FIG. 13 is a cross-sectional side view of a Schottky junction type field effect transistor which is a conventional semiconductor device.

FIG. 14 is a cross-sectional side view showing a manufacturing process of the Schottky junction type field effect transistor which is the conventional semiconductor device.

[Explanation of symbols]

1,23 i-GaAs layer, 1a dug portion, 2 n
-AlGaAs etching stopper layer, 3n-GaAs
s active layer, 4 buffer layer, 5 semi-insulating GaAs substrate, 5a dug portion, 7 n ⁺ ohmic contact region, 8, 18, 21, 24 SiO2 insulating film, 10
Gate metal (electrode), 11 Au upper gate electrode base film, 13 upper gate electrode, 15 drain electrode, 16
Source electrode, 17, 20 gate electrode, 26 n-layer channel region, 27 n-layer region, 29 WSi layer, 30 W
Si sidewall film.

Claims (9)

[Claims] 1. A source / drain region and a channel region comprising a first conductivity type epitaxial crystal growth layer formed on a semi-insulating compound semiconductor substrate, and formed on the first conductivity type epitaxial crystal growth layer. An intrinsic semiconductor layer comprising an epitaxial crystal growth layer having an opening in the channel region; and a gate electrode comprising a second conductivity type epitaxial crystal growth layer selectively grown in the opening of the intrinsic semiconductor layer. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the gate electrode made of the second conductivity type epitaxial crystal growth layer has a smaller bandgap as it goes upward. 3. A source / drain region and a channel region formed of a first conductivity type epitaxial crystal growth layer formed on a semi-insulating compound semiconductor substrate, and a channel region of the first conductivity type epitaxial crystal growth layer. And a second electrode which is formed on
A semiconductor device comprising: a conductive type region; and an epitaxial crystal growth layer having an intrinsic semiconductor region in a region between the second conductive type region and the source / drain region. 4. A semi-insulating compound semiconductor substrate having a concave portion at a portion where a channel region is formed; a channel region formed by implanting an impurity into the concave portion of the semi-insulating compound substrate; A source / drain region connected to the channel region inside the semi-insulating compound substrate below the mask, which is formed by obliquely implanting impurities using a mask formed so as to surround the impurity; A semiconductor device comprising: an intrinsic semiconductor region formed by sometimes leaving a semi-insulating compound semiconductor substrate region below the mask; and a gate electrode formed in the recess. 5. The semiconductor device according to claim 1, wherein a gate metal layer is provided on the gate electrode. 6. A step of epitaxially growing a semiconductor layer of a first conductivity type on a semi-insulating compound semiconductor substrate; a step of epitaxially growing an intrinsic semiconductor layer on the epitaxial layer of the first conductivity type; Opening a region corresponding to a portion where a gate electrode is to be formed to expose the epitaxial growth layer of the first conductivity type; and forming a second conductive layer on the exposed semiconductor layer of the first conductivity type. Forming a gate electrode by epitaxially growing a semiconductor layer of a mold type. 7. A step of epitaxially growing a first conductivity type semiconductor layer on a semi-insulating compound semiconductor substrate; a step of epitaxially growing a second conductivity type semiconductor layer on the first conductivity type epitaxial layer; Forming a gate electrode made of the second conductive type semiconductor layer by etching the second conductive type semiconductor layer by using the mask to remove unnecessary portions thereof; Forming an intrinsic semiconductor region that is connected to the gate electrode by epitaxially growing an intrinsic semiconductor layer. 8. A step of forming an insulating film on a semi-insulating compound semiconductor substrate, forming an opening in a predetermined portion of the insulating film using a mask, and forming an insulating film in which the mask and the opening are formed. Forming a recess in the semi-insulating compound semiconductor substrate by etching using the film as a mask, and removing the mask, removing the insulating film using a mask covering the recess, and the insulating film near the recess. Etching, leaving the insulating film in the vicinity of the concave portion, and performing impurity implantation using the remaining insulating film as a mask,
A step of forming a channel region in the concave portion; a step of forming a sidewall made of a conductor on the side surface of the insulating film remaining in the vicinity of the concave portion and the side surface of the concave portion; Forming a source / drain region connected to the channel region below the remaining insulating film and the sidewall by injecting impurities obliquely. 9. The method for manufacturing a semiconductor device according to claim 6, further comprising a step of forming a gate metal layer on said gate electrode.