JPS6034073A - Manufacture of schottky gate type field-effect transistor - Google Patents
Manufacture of schottky gate type field-effect transistorInfo
- Publication number
- JPS6034073A JPS6034073A JP14323283A JP14323283A JPS6034073A JP S6034073 A JPS6034073 A JP S6034073A JP 14323283 A JP14323283 A JP 14323283A JP 14323283 A JP14323283 A JP 14323283A JP S6034073 A JPS6034073 A JP S6034073A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- layer
- channel region
- effect transistor
- resistivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 230000005669 field effect Effects 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 5
- 229910052796 boron Inorganic materials 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- 125000004430 oxygen atom Chemical group O* 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はＧ ａ Ａ ｓショットキーゲート型電界効果
トランジスタの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a GaAs Schottky gate field effect transistor.
従来例の構成とその問題点
第１図に従来例のＧ ａ Ａ ｓショットキーゲート型
電界効果トランジスタ（ＭＥＳＦＥＴ）の断面図を示す
。Structure of a conventional example and its problems FIG. 1 shows a cross-sectional view of a conventional GaAs Schottky gate field effect transistor (MESFET).
１は半絶縁性Ｇ ａ Ａ ｓ基板、２，３ばオーミック
接触を行うだめの高濃度Ｎ型領域でそれぞれソース領域
、ドレイン領域である。４は動作層であるチャネル領域
で、一般に能動素子として用いる場合、ゲート電極６．
ンース電極６の間に信号電源を印加し、ゲート電極５に
よるチャネル領域４の空乏層の深さを変化させることに
より、前記チャネル領域４を流れる電流を制御する。そ
のため、高周波用のＭＥＳＦＥＴの特性を向上させるた
めにはチャネル領域のキャリア濃度を大きくし、ゲート
・ソース間の直列抵抗を小さくして相互コンダクタンス
を大きくする必要がある。しかし、チャネル領域の濃度
を大きくすれば、チャネル領域４とゲート電極５との逆
方向耐圧が減少するという問題があり、実用上のゲート
逆耐圧ではチャネル領域の濃度を上げて相互コンダクタ
ンスを大きくすることには限界がある。Reference numeral 1 denotes a semi-insulating GaAs substrate, 2 and 3 highly doped N-type regions for making ohmic contact, which are a source region and a drain region, respectively. 4 is a channel region which is an active layer, and generally when used as an active element, a gate electrode 6.
The current flowing through the channel region 4 is controlled by applying a signal power between the gate electrodes 6 and changing the depth of the depletion layer in the channel region 4 formed by the gate electrode 5. Therefore, in order to improve the characteristics of a high-frequency MESFET, it is necessary to increase the carrier concentration in the channel region, reduce the series resistance between the gate and source, and increase the mutual conductance. However, if the concentration of the channel region is increased, there is a problem that the reverse breakdown voltage between the channel region 4 and the gate electrode 5 decreases, and for practical gate reverse breakdown voltage, the concentration of the channel region must be increased to increase the mutual conductance. There are limits to things.
発明の目的
本発明はＧａＡｓ ＭＥＳＦＥＴ （Ｉｃお伝て、チャ
ネル領域とゲート電極の間に前記チャネル領域より高比
抵抗でかつその厚さがゲート金属の拡散電位で空乏化す
る層を形成することにより相互コンダクタンスが大きく
、かつゲートの逆耐圧が大きいＭＥｓＦＥＴの製造を可
能にするものである。OBJECTS OF THE INVENTION The present invention provides a GaAs MESFET (Ic) which has a high specific resistance between the channel region and the gate electrode, and whose thickness is depleted by the diffusion potential of the gate metal. This makes it possible to manufacture MEsFETs with high conductance and high gate reverse breakdown voltage.
発明の構成
本発明はＧ ａ Ａ ｓ基板の一生面に形成されたＧａ
Ａｓショットキーゲート型電界効果トランジスタの製造
方法において、前記基板の一生面に形成された絶縁膜の
ゲート部分を除去して窓孔部分を設ける工程と、前記ゲ
ート部分の基板露出部に、ゲート金属の拡散電位により
その厚さがすべ−Ｃ空乏化され、かつチャネル層よりも
高比抵抗の高比抵抗層を設ける工程と前記ゲート部分の
高比抵抗層上にゲート金属を形成する工程とを含むこと
を特徴とするＧａＡｓ ７ヨノトキーゲート型電界効果
トランジスタの製造方法を提供するものである。これよ
り実用上のゲート逆耐圧を十分満足し、かつチャネル領
域の濃度を大きくすることができるために、大きな相互
コンダクタンスが得られる。Structure of the Invention The present invention relates to Ga As substrate formed on the entire surface thereof.
A method for manufacturing an As Schottky gate field effect transistor includes the step of removing a gate portion of an insulating film formed on the entire surface of the substrate to provide a window hole portion, and forming a gate metal on an exposed portion of the substrate at the gate portion. the step of providing a high resistivity layer whose thickness is entirely C-depleted by the diffusion potential and having a higher resistivity than the channel layer; and the step of forming a gate metal on the high resistivity layer of the gate portion. The present invention provides a method for manufacturing a GaAs 7-type field effect transistor characterized by the following characteristics. This makes it possible to sufficiently satisfy the practical gate reverse breakdown voltage and increase the concentration of the channel region, resulting in a large mutual conductance.
実施例の説明
第２図は本発明のＭＥＳＦＥＴの製造工程を示したもの
である。第２囲（ａ）はゲート金属形成前の断面図であ
る。半絶縁性Ｇ ａ Ａ ｓ基板１１に、Ｓｌの選択イ
オン注入１７を行ない、ソース領域１２゜ドレイン領域
１３を形成する。イオン注入の条件としては、前記ノー
ス領域１２．ドレイン領域１３のキャリア濃度が１×１
０１８．１７ｎ−３となるようにした。同様にチャネル
領域１４をキャリア濃度１×１０１７釧１３ となるよ
うにＳｉ のイオン注入１８を行なった。DESCRIPTION OF THE EMBODIMENTS FIG. 2 shows the manufacturing process of the MESFET of the present invention. The second box (a) is a cross-sectional view before gate metal formation. Selective ion implantation 17 of Sl is performed in a semi-insulating GaAs substrate 11 to form a source region 12 and a drain region 13 . The conditions for ion implantation are as follows: the north region 12. The carrier concentration in the drain region 13 is 1×1
018.17n-3. Similarly, Si 2 ion implantation 18 was performed in the channel region 14 so that the carrier concentration was 1×10 17 .
次に第２図中）のように表面に絶縁膜１９としてＳｉ３
Ｎ４を堆積し、８５０’（： 、 Ａｒ雰囲気中にて２
０分間熱処理を行った。続いてゲート領域部の保護膜１
９に窓孔部分を設け、リン酸系・エツチング液でチャネ
ル領域の露出部を約５００人′エツチングし、ざらにそ
の上に分子線エピタキシー法でキャリア濃度Ｉ Ｘ １
０１６ｃｍ−” のＮ型層ａＡｓｘピタキンヤル層から
なる高比抵抗層２ｏを５００人成長させ、続いて第２図
（Ｃ）のようにアルミニウムを蒸着しリフトオフ法によ
りゲート電極１５を形成した。この結果、ゲート長１μ
ｍ、ゲート幅２０７、＋ｍ、閾値電圧−２．ＯＶのＭＥ
ＳＦＥＴでは、従来のように高比抵抗層を形成せずにチ
ャネル領域のキャリア濃度がｌＸ１０１７ｏｎ−’ の
場合相互コンダクタンスが２ｍＳ、ゲート逆耐圧が５ｖ
であるのに対し、本発明では、相互コンダクタンスが２
ｍＳ。Next, an insulating film 19 of Si3 is formed on the surface as shown in FIG.
N4 was deposited, 850' (:, 2
Heat treatment was performed for 0 minutes. Next, protective film 1 in the gate area
9, and etched the exposed part of the channel region for about 500 minutes using a phosphoric acid-based etching solution, and roughly formed a carrier concentration I x 1 on top using molecular beam epitaxy.
A high resistivity layer 2o consisting of an N-type layer aAsx pitaquin layer of 0.016 cm-'' was grown by 500 people, and then, as shown in FIG. 2(C), aluminum was deposited and a gate electrode 15 was formed by a lift-off method. , gate length 1μ
m, gate width 207, +m, threshold voltage -2. OV ME
In SFET, when the carrier concentration in the channel region is lx1017on-' without forming a high resistivity layer as in the conventional case, the mutual conductance is 2 mS and the gate reverse breakdown voltage is 5 V.
In contrast, in the present invention, the mutual conductance is 2
mS.
ゲー］・つφ面子圧が８■あった。式へにチ、１．休ル
の濃度を大きくし、２×１０１７ｃｍ−３にした場合、
相互コンダクタンスが３．２ｍＳ、ゲート逆耐圧が７■
であった。従って本発明の結晶成長法を用いだＧ ａ
Ａ ｓショットキーゲート型電界効果トランジスタの製
造方法により相互コンダクタンスが大キく、かつゲート
逆耐圧が大きいＭＥＳＦＥＴの製造が可能となった。Game]・tsuφ face pressure was 8■. Shikihenichi, 1. When the concentration of rest is increased to 2 x 1017 cm-3,
Mutual conductance is 3.2mS, gate reverse breakdown voltage is 7■
Met. Therefore, using the crystal growth method of the present invention, Ga
The method of manufacturing As Schottky gate field effect transistors has made it possible to manufacture MESFETs with high mutual conductance and high gate reverse breakdown voltage.
なお、上記の実施例では高比抵抗層２０を分子線エピタ
キシー法によって形成したが、絶縁膜１９のゲート部分
に窓孔を設けた後、ボロンイオンを加速電圧５０ＫｅＶ
、ドーズ量１．９Ｘ１０１５，７．、−２ 又は酸素イ
オンを加速電圧７０ＫｅＶ、ドーズ量１．５×１０１５
ｃｔｎ−２を注入することにより前記高比抵抗層を形成
した場合も同様な結果が得られた。従って本発明のイオ
ン注入法を用いたＧ ａ Ａ ｓショットキーゲート型
電界効果トランジスタの製造方法でも相互コンダクタン
スが大きく、かつゲート逆耐圧が大きいＭＥＳＦＥＴの
製造が可能となった。In the above example, the high resistivity layer 20 was formed by molecular beam epitaxy, but after providing a window in the gate portion of the insulating film 19, boron ions were formed at an accelerating voltage of 50 KeV.
, dose amount 1.9X1015,7. , -2 or oxygen ions at an accelerating voltage of 70 KeV and a dose of 1.5 x 1015
Similar results were obtained when the high resistivity layer was formed by implanting ctn-2. Therefore, the method for manufacturing a GaAs Schottky gate field effect transistor using the ion implantation method of the present invention also makes it possible to manufacture a MESFET with a large mutual conductance and a large gate reverse breakdown voltage.
なお上記実施例では、ゲート電極１５としてアルミニウ
ムを用いたが、白金などのＧ ６ Ａ ｓと固相反応し
てショットキー障壁がＧ ａ Ａ ｓ内に埋込まれるＭ
ＥＳＦＥＴ についても同様な結果が得られた。In the above embodiment, aluminum was used as the gate electrode 15, but aluminum, such as platinum, reacts with G 6 As in a solid phase and a Schottky barrier is embedded in Ga As.
Similar results were obtained for ESFET.
従って本発明では、ゲート金属としてＮ型Ｇ ａ Ａ
ｓとショットキー接合となるものであればよく、ゲート
金属はなんら限定されるものでない。Therefore, in the present invention, N-type Ga A is used as the gate metal.
The gate metal is not limited in any way as long as it forms a Schottky junction with s.
発明の効果
本発明のＧ ａ Ａ ｓショットキーゲート型電界効果
トランジスタの製造方法により、チャネル領域のキャリ
ア濃度の増大が可能となり、相互コンダクタンスが大き
く、かつゲート電極とチャネル領域間の逆方向配圧の大
きい、すぐれた性能のＭＥＳＦＥＴ を製造することが
可能となった。Effects of the Invention The method for manufacturing a GaAs Schottky gate field effect transistor of the present invention makes it possible to increase the carrier concentration in the channel region, increase mutual conductance, and provide reverse voltage distribution between the gate electrode and the channel region. It has now become possible to manufacture MESFETs with large and excellent performance.
第１図は従来のＭＥＳＦＥＴの断面図、第２図（ａ）〜
（Ｃ）は本発明の一実施例の製造工程の一部を示す断面
図である。
１１・・・・・・半絶縁性Ｇ ａ Ａ ｓ、１２・・・
・・・ソース領域、１３・・・・・ドレイン領域、１４
・・・・・チャネル領域、１６・・・・・・ゲート電極
、１７ ・・・ソース・ドレイン領域の選択イオン注入
、１８・・・・・・チャネル領域の選択イオン注入５１
９ ・・・保護膜、２０・・・・高比抵抗層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名（Figure 1 is a cross-sectional view of a conventional MESFET, Figure 2 (a) -
(C) is a sectional view showing a part of the manufacturing process of one embodiment of the present invention. 11... Semi-insulating Ga As, 12...
... Source region, 13 ... Drain region, 14
... Channel region, 16 ... Gate electrode, 17 ... Selective ion implantation of source/drain region, 18 ... Selective ion implantation of channel region 51
9...protective film, 20...high resistivity layer. Name of agent: Patent attorney Toshio Nakao and one other person (
Claims (3)
ト部分を除去して窓孔部分を設ける工程と、前記ゲート
部分の基板露出部に、ゲート金属の拡散電位によシその
厚さがすべて空乏化されかつチャネル層よりも高比抵抗
の高比抵抗層を設ける工程と、前記ゲート部分の高比抵
抗層上にゲート金属を形成する工程とを含むことを特徴
とするショットキーゲート型電界効果トランジスタの製
造方法。(1) A step of removing the gate portion of the insulating film formed on the whole surface of the GaAs substrate to provide a window hole portion, and forming a window hole portion in the exposed portion of the gate portion depending on the diffusion potential of the gate metal. A Schottky gate type characterized by comprising a step of providing a high resistivity layer which is completely depleted and has a higher resistivity than the channel layer, and a step of forming a gate metal on the high resistivity layer in the gate portion. A method of manufacturing a field effect transistor.
る工程において、ゲート部分の基板露出部をエツチング
し、その後前記基板露出部にチャネル層よりも高比抵抗
の高比抵抗層を結晶成長法により形成することを特徴と
する特許請求の範囲第１項に記載のショットキーゲート
型電界効果トランジスタの製造方法。(2) In the step of providing a high resistivity layer having a higher resistivity than the channel layer, the exposed portion of the substrate at the gate portion is etched, and then the high resistivity layer having a higher resistivity than the channel layer is crystallized on the exposed substrate portion. 2. A method for manufacturing a Schottky gate field effect transistor according to claim 1, wherein the Schottky gate field effect transistor is formed by a growth method.
工程において、ゲート部分の基板露色部にボロンあるい
は酸素原子をイオン注入することを特徴とする特許請求
の範囲第１項に記載のショットキーゲート型電界効果ト
ランジスタの製造方法。(3) In the step of providing a high resistivity layer having a resistivity higher than that of the channel layer, boron or oxygen atoms are ion-implanted into the exposed portion of the substrate in the gate portion. A method for manufacturing a Schottky gate field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14323283A JPS6034073A (en) | 1983-08-04 | 1983-08-04 | Manufacture of schottky gate type field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14323283A JPS6034073A (en) | 1983-08-04 | 1983-08-04 | Manufacture of schottky gate type field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6034073A true JPS6034073A (en) | 1985-02-21 |
Family
ID=15333969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14323283A Pending JPS6034073A (en) | 1983-08-04 | 1983-08-04 | Manufacture of schottky gate type field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6034073A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0196964A (en) * | 1987-10-09 | 1989-04-14 | Oki Electric Ind Co Ltd | Schottky gate field effect transistor |
| JPH08203930A (en) * | 1995-01-31 | 1996-08-09 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH08321518A (en) * | 1994-08-22 | 1996-12-03 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| JP2000150541A (en) * | 1994-08-22 | 2000-05-30 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1983
- 1983-08-04 JP JP14323283A patent/JPS6034073A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0196964A (en) * | 1987-10-09 | 1989-04-14 | Oki Electric Ind Co Ltd | Schottky gate field effect transistor |
| JPH08321518A (en) * | 1994-08-22 | 1996-12-03 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| JP2000150541A (en) * | 1994-08-22 | 2000-05-30 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH08203930A (en) * | 1995-01-31 | 1996-08-09 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
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