JPH024137B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a shot gate field effect transistor.

Short gate field effect transistor (hereinafter referred to as
MESFET (abbreviated as MESFET) is prized as an excellent amplification or oscillation element, especially at ultra-high frequencies. It is also well known that it is an excellent basic component for integrated circuits operating at ultra-high speeds.

The structure of the MESFET most commonly used in the past is shown in Figure 1. Here 1
2 is a high resistivity or semi-insulating semiconductor crystal substrate, and 2 is a conductive semiconductor crystal layer which is usually called an operating layer. 3 is a short gate electrode, 4,
Reference numerals 5 denote source and drain electrodes each having ohmic characteristics.

The carrier concentration Nd and thickness a of this active layer
has a relationship with the pinch-off voltage Vp of the MESFET as shown in the following first equation.

Vp＝Vb－qNd／2εa ² ...(1) However, Vb is the built-in voltage, ε is the dielectric constant of the semiconductor crystal, and q is the elementary charge amount.Vp is given from the circuit design requirements, and this value of Vp is satisfied. The values of Nd and a are determined using equation (1) so that.

One of the drawbacks of the conventional structure as shown in FIG.
The problem is that a sufficiently large value of gm cannot be obtained because the resistance value between the gate and the source is large, and the noise characteristics are deteriorated due to the large series resistance between the gate and the source.
Especially when the absolute value of the pinch-off voltage Vp is small,
Or in normally off (Vp>0),
As is clear from equation (1), since Nd or a must be set to a small value, the series resistance between the gate and source becomes a larger value. Also, the operating layer 2
However, when using GaAs crystal, the gate
High-density surface states exist in the crystal surface area 67 between the source and between the gate and drain, which nearly fixes the surface potential, and a depletion layer is formed near the surface within the semiconductor crystal. The series resistance between the capacitor and the capacitor can reach a very large value, which is a very serious problem, especially in the normally-off type.

One way to solve this problem is to make the active layers 9 and 10 between the gate and source and between the gate and drain thicker than the active layer 8 directly under the gate electrode, as shown in FIG. things are being done. In this method, it is necessary to determine the thickness of the active layer 8 and the carrier concentration to satisfy the conditions of equation (1), but in such a step structure, the thickness of the active layer 8 must be precisely determined by etching, etc. Control with good reproducibility is difficult with current technology.

The present invention provides a new MESFET manufacturing method that solves the above-mentioned drawbacks of the prior art.

The present invention is a process of forming a first semiconductor layer of one conductivity type on one principal surface of a semi-insulating semiconductor substrate by selecting its thickness and carrier concentration so that the pinch-off voltage becomes a desired value. A step of forming a striped pattern with a predetermined thickness on the first semiconductor layer, and using the mask pattern as a mask, selectively ion-implanting or heating an impurity that gives the same conductivity type as the first semiconductor layer. A step of forming a second semiconductor layer by introducing it by a diffusion method, and a step of forming a metal layer thinner than the mask pattern by vapor deposition,
A step of forming an inverted pattern that is exactly inverted with respect to the mask pattern by removing the mask pattern and removing the metal layer thereon, a step of depositing a shot gate metal thinner than the inverted pattern, and a step of forming the inverted pattern. forming a shot gate electrode located on the first semiconductor layer by lift-off;
The method is characterized in that it includes a step of forming source and drain electrodes on the second semiconductor layer.

According to the present invention, since the inversion pattern is made of metal and is formed by vapor deposition, no metal layer is formed on the sidewalls of the mask pattern. Moreover, since the inversion pattern is thicker than the shot gate metal layer and the mask pattern is thicker than the inversion pattern, lift-off can be performed capacitively and completely to improve yield.

The present invention will be explained below based on the drawings.

An example of the MESFET of the present invention is shown in FIG.

FIG. 3 shows a shallow active layer 1 on a semiconductor crystal substrate 1 below a shot gate electrode 20.
5. Source electrode 22, deep active layer 13 below between the gate and source electrodes, and drain electrode 2
3 and a deep active layer 14 below between the gate and drain electrodes. MESFETs with such a structure are excellent in that they have low gate-source resistance and gate-drain resistance and large gm, and at the same time, can be easily manufactured using the manufacturing method of the present invention, as will be explained in detail below. It can be manufactured with high yield.

Figures 4-a to 4-e are according to the present invention.
FIG. 3 is a cross-sectional view for explaining the manufacturing process of MESFET.

First, as shown in FIG. 4a, a semiconductor crystal layer 11 of one conductivity type is formed on the surface of a high resistivity or semi-insulating semiconductor crystal substrate 1. As shown in FIG. At this time, the thickness and carrier concentration of 11 are determined from equation (1) so that Vp becomes a desired value. The manufacturing method 11 may be a vapor phase epitaxial method, a liquid phase epitaxial method, or a method of ion-implanting impurities into the semi-insulating substrate 1.

For example, in order to obtain an active layer with a pinch-off voltage of 0 volts (normally off) by ion-implanting ²⁸ Si ⁺ into a GaAs semi-insulating crystal substrate, the amount of ²⁸ Si ⁺ implanted should be 5.5×
An example is implantation at a dose of 10 ¹¹ /cm ² and an accelerating voltage of 120 KeV. (However, the activation rate was 100%) The carrier concentration distribution in the depth direction at this time is shown by the solid line 23 in FIG.

Next, a striped implantation mask 12 is formed on the surface of the crystal layer 11, as shown in FIG. 4b. SiO ₂ is suitable as the material for 12, but
A material that can be used as a selective mask for ion implantation.
Other materials may be used as long as they can be easily formed and peeled off. Next, using 12 as a mask material, impurities having the same conductivity type as the previously formed crystal layer 11 are introduced into the crystal substrate by ion implantation or thermal diffusion to form deep active layers 13 and 14.

The conditions for implanting the deep active layers 13 and 14 by ion implantation are that the implantation energy is greater than the energy used for implanting the shallow active layer 11 in order to implant the deep active layer 11 deeper than the shallow active layer 11, and the implantation amount is It is preferable to select a value such that the final peak carrier concentration is not extremely excessive compared to the peak carrier concentration of the active layer 11. This is to prevent breakdown from occurring due to the voltage applied to the gate. As an example of such implantation conditions, the implantation energy is 400KeV and the implantation amount is 1.07×
The theoretical value of the carrier density distribution when a value of 10 ¹² dose/cm ² is selected is illustrated by the broken line 24 in FIG. Parts 13, 14 not masked by 12
The concentration of is 2 times higher than that of the first shallow ion implantation.
This value is obtained by adding the concentration obtained by the deep ion implantation of the second time, and its distribution is illustrated by the dashed line 25 in FIG.

As is clear from FIG. 10, the total number of carriers in the deep active layers 13 and 14 is about three times larger than the total number of carriers in the main active layer 15 that provides the pinch-off voltage, so that the active layers 13 and 14 Compared to the case of the conventional method shown in FIG.
Source-to-source resistance can be reduced to less than 1/3. 13,1
When layers 4 and 15 are formed by ion implantation, annealing is then performed for the purpose of activating these ion implanted layers. At this time, the crystal substrate
In the case of chemical semiconductors such as GaAs and InP,
700 to 850℃ while taking care to prevent surface deterioration by performing annealing by controlling As pressure or P pressure.
Anneal for several 10 minutes.

Next, thin films 16, 17, and 18 of Au are formed on the entire surface of the substrate by vacuum evaporation (FIG. 4c). The thin films 16, 17, and 18 need to be thinner than the mask 12, as shown. Also,
Since the thin films 16 to 18 are formed by vapor deposition, Au does not adhere to the sidewalls of the mask 12. Therefore, subsequent lift-off can be performed easily and with high yield.

After that, by removing the SiO ₂ film 12 with HF-based etchant, the Au 17 on the SiO ₂ film 12 is removed at the same time.
When removed by lift-off, Au patterns 16 and 18 are obtained which are inverted with respect to the SiO ₂ pattern 12, as shown in FIG. 4d.

Thereafter, a metal to be used as a shot gate electrode, for example Al 19, 20, 21, is deposited on the entire surface as shown in FIG. 4e. These Al 19 to 21 need to be thinner than the thin films 16 and 17 as shown in the figure. In addition, as this shot gate metal, the thin film 16 mentioned above is used.
It is necessary that the material can be etched separately (selectively) from the constituent materials of ~18.

Next, Au16,18 is removed with an iodine etchant, and at the same time Al19,2 on top of 16,18 is removed.
1 is removed by lift-off, an Al shot gate electrode 20 is formed directly above the shallow active layer 15 at exactly the same position as shown in FIG. 4f.

If the shot gate electrode 20 cannot be accurately aligned and misaligns, there will be a part of the shallow active layer where the shot gate electrode does not exist, resulting in a disadvantage that the series resistance of this part will be large. . However, this method has the advantage that positional displacement essentially does not occur because it is self-aligned.

Next, a source electrode 22 and a drain electrode 23 are formed by a commonly known method to complete the MESFET shown in FIG.

The present invention is not limited to the content explained based on the above drawings, and the purpose of the present invention is to
This can be achieved using many semiconductor crystals such as GaAs, InP, and Si, and is not limited to only one semiconductor crystal. Moreover, the material of the mask etc. can be arbitrarily selected without changing the intention of the present invention.

As described above, according to the present invention, the series resistance between the gate and source is small and the gm is large.
MESFETs can be easily created with a simple process and a high yield.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of a short-gate field effect transistor according to the conventional method, FIG. 3 is a cross-sectional view of a short-gate field effect transistor of the present invention, and FIGS. 4a to 4f are cross-sectional views of a short-gate field effect transistor of the present invention. FIG. 5 is a diagram showing the carrier concentration distribution of the active layer according to the present invention. In the figure, 1 is a semiconductor crystal substrate, 2, 8, 9, 10 are active layers, 3, 20 are shot gate electrodes, 4,
22 is a source electrode, 5 and 23 are drain electrodes, 1
3 and 14 are deep operating layers, 15 are shallow operating layers, 12
is a striped mask, and 16 and 18 are inverted masks.

Claims (1)

[Claims] 1. A first semiconductor layer of one conductivity type is formed on one main surface of a semi-insulating semiconductor substrate, and its thickness and carrier concentration are selected so that the pinch-off voltage becomes a desired value. forming a striped mask pattern with a predetermined thickness on the first semiconductor layer; and using the mask pattern as a mask,
forming a second semiconductor layer on both sides of the semiconductor layer of the mask pattern by selectively introducing impurities that give the same conductivity type as the semiconductor layer of the mask pattern by ion implantation or thermal diffusion; forming a thinner metal layer by vapor deposition, removing the mask pattern and removing the metal layer thereon, thereby forming an inverted pattern of the metal layer that is accurately inverted with respect to the mask pattern; and depositing a shot gate metal that can be selectively removed between the metal layer and the metal layer to be thinner than the inversion pattern, and removing the inversion pattern to form the first semiconductor layer by lift-off. A method of manufacturing a field effect transistor, comprising the steps of: forming an overlying short gate electrode; and forming source and drain electrodes on a second semiconductor layer.