JPS6347982A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress a substrate current generated due to interval between the n<+> type regions of source and drain to an extremely small value thereby to improve the gm of an FET by substantially equalizing in height the bottoms of the source and drain n<+> type regions formed by an ion implanting method on a semiconductor substrate to that of an active layer under a gate electrode. CONSTITUTION:The bottoms of source and drain n<+> type regions 4, 5 formed by an ion implanting method on a semiconductor substrate 7 are substantially equalized to that of an active layer 6 under a gate electrode 2. For example, the regions 4, 5 of an FET are formed by ion implanting with a mask 8 on a high resistance GaAs substrate 7. A film 9 different from the mask 9 is formed on the substrate 7, the mask 9 is removed, and the substrate 7 is etched in a suitable depth. Then, with the mask 9 the active layer 6 is formed by ion implanting. Thereafter, with the mask 9 the electrode 2 is formed, and source and drain electrodes 1, 3 are further formed to complete the FET.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to improvements in semiconductor devices including field effect transistors.

<Conventional technology> Conventionally, Schottky barrier field effect transistors (hereinafter referred to as ME) using compound semiconductors, especially GaAs, have been developed.
SFET (abbreviated as SFET) has excellent performance as an ultra-high speed, ultra-high frequency element and is widely used. This kind of MES
In order to further increase the speed of FETs, it is necessary to shorten the gate electrode length and the distance between the source and drain n+ regions. Furthermore, when a large number of elements are integrated in the same chip, it is effective from the point of view of uniformity to form the active layer and the n+ region using ion implantation.

Figure 2 shows a conventional G manufactured using ion implantation technology.
FIG. 2 is a diagram schematically showing the structure of an aAs MESFET.

In FIG. 2, 11 is a source electrode, and 12 is a gate electrode.
13 is a drain electrode, 14 and 15 are n+ layers for lowering the contact resistance of the source and drain electrodes 11 and 13, 16 is an active layer, and 17 is a high resistance GaAs substrate.

The gate electrode 1.2 can be processed to a thickness of 0.25 μm or less by using electron beam direct exposure technology, and the source and drain electrodes 11 and 13 can be structured extremely close to the gate electrode 12. ing.

<Problems to be Solved by the Invention> In the conventional λIESFET using ion implantation technology, the bottoms of the source and drain n+ regions 14 and 15 are considerably deeper than the bottom of the active layer 16; As the distance between the n+ and drain regions 14 and 15 is reduced, the distance between the drain electrode 13 and the source electrode 11 of the substrate 1 is reduced.
7 increases, effectively increasing the current flowing through gate electrode 1
2 control ability decreases. In this case, even if the distance between the source and drain n+ regions 14 and 15 is shortened, the MESF
Unexpectedly, there was a drawback that the mutual conductance (hereinafter abbreviated as gm) of ET was not improved.

The present invention was devised in view of the above points, and is a new FET structure that suppresses the substrate current that occurs due to the shortening of the distance between the n+ regions of the source and drain to an extremely low level, thereby making it possible to improve the gm of the FET. The purpose of this invention is to provide a semiconductor device equipped with the following.

Means for Solving the Problems> In order to achieve the above object, the semiconductor device of the present invention provides an active layer at the bottom of the source and drain n-regions and under the gate electrode, which are formed on a semiconductor substrate by ion implantation. The structure is such that the heights of the bottoms of the layers are approximately equal.

Further, in an embodiment of the present invention, the semiconductor substrate is formed on the semiconductor substrate using ion implantation technology, with a structure in which the semiconductor near the region on the semiconductor substrate where the gate electrode is formed is selectively removed. The structure is such that the source and drain n- regions and the bottom of the active layer are approximately equal to each other.

Effect> Since the bottoms of the n+ regions of the source and drain are approximately equal to the bottoms of the active layer, even when the distance between the n+ regions of the source and drain is extremely shortened, the current flowing through the substrate can be kept extremely small.

<Embodiment> Hereinafter, one embodiment of the semiconductor device of the present invention will be described according to its manufacturing process with reference to the drawings.

First, the n+ source of the FET is placed on the high resistance GaAs substrate 7.
Region 4 and drain n+ region 5 are formed by ion implantation using mask 8 as shown in FIG. 1(a). The ion implantation conditions were an acceleration voltage of 150 keV and a dose of 5X.
10 cm of S+ ions were implanted. Then the first
As shown in Figure (b), a film 9 different from the mask 8 is made of GaA.
s is formed on the surface of the substrate 7, and the mask 8 is removed. Using the mask 9, the GaAs substrate 7 is etched to a suitable depth, for example, 1500 Å, as shown in FIG. 1(c), from the opening in the region where the gate electrode is to be formed. Next, as shown in FIG. 1(d), an active layer (channel region) 6 is formed by ion implantation using a mask 9. The ion implantation conditions were an acceleration voltage of 60 keV and a dose of 5×1.
0-1 Si ions were implanted. Further, in order to activate each of the above injection layers, annealing was performed at 800° C. for 15 minutes using, for example, a plasma CVDSiNx protective film. Through the above steps, the depth of the bottom of n regions 4 and 5 is 0.25-0.
3 μm, and the depth of the bottom of the active layer 6 is 0.1 to 0.1 μm.
The warpage is 5 μm, and the bottoms of the active layer 6, which is obtained by etching the substrate surface in the vicinity of the region where the gate electrode is formed, are approximately equal. Next, as shown in FIG. 1(e), a gate conductor is formed using a mask 9, and a source electrode 1 and a drain electrode 3 are formed by a known method to form an FET as an embodiment of the present invention. Complete the structure of.

With the above configuration, even if the n+ regions of the source and drain are extremely shortened, the current flowing with the substrate can be kept extremely low, and at the same time, the parasitic resistance between the gate and source electrodes can be kept low.

The masks 8 and 9 may be made of silicon nitride in an amorphous silicon oxide film or a native oxide film of a semiconductor such as GaAs. Etching of the substrate 7 varies depending on the type of semiconductor substrate, but for GaAs For phosphoric acid and Si, hydrazine or the like may be used. However, the order of the steps for forming the active layer 6 and the source and drain n' regions 4 and 5 in FIG. 1 is arbitrary, and it is also possible to carry out the steps in the reverse order of the above description. That is, after etching the vicinity of the gate region, ions can be implanted into the entire region from the source to the drain for forming the active layer, and then the n+ region of the source and drain can be formed.

Furthermore, the above-mentioned ion implantation conditions and etching amount values are not limited to the above-mentioned embodiments, and the present invention is characterized in that the bottoms of the n+ regions of the source and drain are approximately equal to the bottoms of the active layer. Therefore, the etching depth and ion implantation conditions may be set so that the bottoms of n+ regions 4 and 5 and the bottom of active layer 6 are approximately equal.

Although the present invention has been described above in detail by taking the GaAs MESFET as an example, the present invention is not limited thereto, and can be applied to compound semiconductors other than GaAs and semiconductors such as Si.

<Effects of the Invention> As described above, according to the present invention, the bottom of the n+ region of the source and drain of a semiconductor device is made almost equal to the bottom of the active layer, and as a result, the bottom of the n+ region of the source and drain is made almost equal to the bottom of the active layer. Even when the gate length is shortened, the current flowing through the substrate can be kept extremely small, and at the same time, the gate current
Since it is possible to suppress the parasitic resistance between the source electrodes, it is possible to significantly improve the gm of the FET.

[Brief explanation of the drawing]

1(a) to 1(e) are diagrams each schematically showing a cross section of a substrate for explaining an example of the manufacturing process of a device according to an embodiment of the present invention, and FIG. This is a schematic diagram showing an example of the structure of an FET. , 6...active layer, 7...high resistance Ga
As substrate. Agent Patent attorney Takeshi Sugiyama (and 1 other person) (G) (d) (e) Figure 1 Figure 2

Claims (1)

[Claims] 1. The bottom of the source and drain n^+ regions formed by ion implantation on the semiconductor substrate and the bottom of the active layer under the gate electrode are approximately equal in height. Semiconductor equipment. 2. The semiconductor device according to claim 1, wherein the semiconductor near the region where the gate electrode is formed is selectively removed.