JPH0724259B2 - Method for manufacturing compound semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a heat treatment method for activating an ion-implanted layer.

[Conventional technology]

Compound semiconductor devices, especially Schottky barrier gate type field effect transistors (hereinafter ME) using gallium arsenide (GaAs).
SFET) is capable of high speed operation and is used as a basic element of high frequency amplifiers and high speed integrated circuits.

The above-mentioned FET is manufactured, for example, as described in Electronics Letters, Vol. 17, Vol. 17, p. 944. First, impurities such as Si are selectively ion-implanted on a semi-insulating GaAs substrate. After that, a protective film such as silicon dioxide or silicon nitride is used to prevent the evaporation of As.
It is deposited on the entire surface of the GaAs substrate and heat-treated at about 800 ° C to activate the impurities. Next, after forming a Schottky gate electrode made of, for example, Al on the impurity region, source and drain electrodes having ohmic contact such as AuGe-Ni are formed to complete the FET.

The heat treatment of the GaAs substrate includes cap annealing using a silicon dioxide film or a silicon nitride film, and capless annealing performed simply in an arsine atmosphere without using a protective film.
These methods are selected and used.

[Problems to be Solved by the Invention]

When an integrated circuit having a MESFET using a GaAs substrate is manufactured, a so-called side gate effect occurs in which the drain current of the MESFET fluctuates due to the negative potential of another FET in proximity,
There is a problem that the operation of the circuit becomes unstable.

An object of the present invention is to provide a method for manufacturing a compound semiconductor device with a reduced side gate effect.

[Means for Solving the Problems]

A method of manufacturing a compound semiconductor device according to the present invention is a method of manufacturing a compound semiconductor device in which an impurity is selectively introduced into a semi-insulating compound semiconductor substrate by an ion implantation method and then heat treatment is performed to activate the impurity to form an operating layer. In this method, a silicon nitride film is formed only on a region where impurities are introduced, and then heat treatment is performed in an arsine atmosphere.

The side gate effect is F due to the voltage of the electrode near the FET.
It is caused by a potential difference at the ni junction between the operating layer of the ET and the semi-insulating substrate below the operating layer, thus modulating the thickness of the operating layer. In this case, this effect is diminished when the deep rank in the semi-insulating substrate, for example, the trap density of EL2 is small. Further, in the region between the electrode and the FET which are adjacent to each other, the higher the insulating property is, the smaller the potential difference applied to the operating layer portion is, and thus the side gate effect is reduced.

It is known that when heat treatment is performed, the trap density decreases in the vicinity of the surface of the substrate, so that the insulating property decreases. The inventor has found that the reduction amount of the trap density, that is, the insulating property is different between the annealing using the silicon nitride film and the annealing in the arsine, and the annealing in the arsine reduces the trap density more than the case of the silicon nitride film. The inventors have found that they are small and have high insulating properties, and have reached the present invention.

Further, in the ni junction region, as described above, the smaller the trap density is, the smaller the side gate effect is. Therefore, the annealing using the silicon nitride film is advantageous.

As described above, by depositing a silicon nitride film only on the operating layer of the FET and then performing a heat treatment in arsine, the trap density is greatly reduced near the operating layer, and the trap density between the electrode adjacent to the FET is also reduced. Is small, a compound semiconductor device having a small side gate effect can be obtained.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1 (a), a semi-insulating GaAs substrate 5 is used.
Si ions are selectively applied to the surface of Si at an acceleration voltage of 50 keV and a dose of 2
Ions are implanted under the condition of × 10 ¹² cm ^-2 to form the GaAs operating layer 4.

Next, as shown in FIG. 1B, a silicon nitride film 6 having a thickness of 0.5 μm is deposited on the entire surface of the substrate by a plasma CVD method and then patterned by a dry etching method.
The silicon nitride film 6 is left only on the top. Then, in an atmosphere of arsine partial pressure 2 _Torr diluted with argon gas, 800 ° C, 20
The heat treatment for 1 minute is performed to activate Si which is an ion-implanted impurity.

Finally, as shown in FIG. 1 (c), on the GaAs operating layer 4
Gate electrode made of Al 1, source electrode made of AuGe-Ni 2,
The drain electrode 3 is formed, and the fabrication of the FET is completed.

For comparison, in the heat treatment of the above steps, the FET manufactured by the conventional manufacturing method when the heat treatment is performed using only the silicon nitride film, and further the heat treatment is performed only in the arsine atmosphere.
Also made. Then, the side gate effect of the three types of FETs having different heat treatment methods was examined by the change of drain current when a negative voltage was applied to the ohmic electrodes of the adjacent FETs. The results are shown in FIG.

As shown in FIG. 2, in the case of this embodiment, the side gate voltage at which the drain current starts to decrease is higher than that of the conventional example, and the side gate effect is reduced.

The present invention is also applied to an n ⁺ self-aligned structure FET using a heat resistant gate. In the case of this manufacturing, after forming a heat-resistant gate and performing Si implantation for n ⁺ layer formation by self-alignment, a SiN film of 0.5 μm is formed only on the n ⁺ implantation region and heat treatment is performed in an arsine atmosphere. went. Also in this case, it was found that the side gate effect is suppressed as compared with the conventional one type of annealing method.

〔The invention's effect〕

As described above, according to the present invention, after introducing an impurity into a semi-insulating substrate, a silicon nitride film is formed only on a region into which the impurity is introduced, and a heat treatment is performed in an arsine atmosphere to obtain a side gate effect. As a result, the instability of circuit operation can be suppressed.

[Brief description of drawings]

1 (a) to 1 (c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a drain current of an FET obtained by this embodiment and a conventional example. It is a figure which shows the relationship between a side gate voltage and. 1 ... Gate electrode, 2 ... Source electrode, 3 ... Drain electrode,
4 ... GaAs operating layer, 5 ... GaAs substrate, 6 ... Silicon nitride film.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/812

Claims (1)

[Claims] 1. A method of manufacturing a compound semiconductor device, wherein an impurity is selectively introduced into a semi-insulating compound semiconductor substrate by an ion implantation method and then heat treatment is performed to activate the impurity to form an operation layer. A method for manufacturing a compound semiconductor device, comprising: forming a silicon nitride film only on the formed region and then performing heat treatment in an arsine atmosphere.