JPS6292327A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent contamination on ion implantation and deterioration caused by a knock-on effect by implanting ions, penetrating an insulating film consisting of an AlN film, laminating a protective film composed of SiN onto the AlN film and thermally treating the whole. CONSTITUTION:An AlN film 14 is applied onto a GaAs substrate 1. Ions are implanted in order to form a source region 3 and a drain region 4, using a photo-resist 8 as a mask. A photo-resist mask 8' is removed completely, and an SiN film 14' is laminated. The whole is thermally treated in hydrogen. The SiN film 14' is etched through dry etching employing a fluorine group gas, using a photo-resist 8'' as a mask, and the AlN film 14 is etched in a wet type by H3PO4. Source-drain electrode materials 15, 15', 15'' are evaporated, and the SiN film 14' is etched through a dry etching method and the AlN film 14 through wet type etching respectively, employing the photo-resist 8'' as the mask. Accordingly, contamination on ion implantation and deterioration caused by a knock-on effect are prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to m-v group compound semiconductors, and in particular to Ga
The present invention relates to a semiconductor device having a protective film suitable for large-scale integrated circuit devices using As, and a method for manufacturing the same.

[Background of the invention]

In an integrated circuit using a GaAs compound semiconductor as a substrate, a MES-FET using a Schottky barrier of metal-semiconductor contact in the gate portion is used as a basic component. As shown in the cross-sectional view of FIG. 1, this FET consists of an n-type channel layer 2 formed by ion implantation into a substrate 1, an n-type source region 3, a drain region 4, and gates formed on the surfaces of each. electrode 5, source electrode 6,
It is operated by controlling the current flowing between the source electrode 6 and the drain electrode 7 through the channel layer 2 by an electric field applied from the gate electrode 5.

Conventionally, the process of forming a channel layer of an MES-FET on a GaAg substrate is as shown in FIG.
After forming an ion implantation mask 8 having an opening at a predetermined position where a channel is to be formed on the substrate 1, a step of implanting desired ions in a high vacuum and removing the ion implantation mask 8 are performed. 5isN+, AQxos
or AlN, or a protective film 9 made of laminated layers thereof.
is deposited and heat-treated at 800 to 900°C to form channel layer 2.
(Journal of Electrochemical Society: J, Electr.
ocham, Soc+July, 1984. pp167
4-1678). Here, the protective film 9 is deposited to prevent Ga and As in the GaAs substrate from evaporating due to high-temperature heat treatment.

In the conventional process mentioned above, when implanting ions in a high vacuum,
There is a problem in that oil mist generated from the vacuum evacuation device and residual gas in the vacuum chamber are adsorbed on the surface of the channel layer 2, and this enters the channel as unnecessary impurities at the same time as ion implantation and impedes activation. As shown in FIG. 3, the solution to the above problem proposed by the conventional technology is to cover the GaAs surface with SiO2, 5iaNt, An
Surface protection made of zOg or AflN thin film! ! This method prevents the unnecessary impurities from being mixed in by depositing a thin film 11 and implanting ions through this thin film (Applied Physics Letters: Appl, Phys.
s.

Lett, Volume 31, Issue 3, August 1977, pp
158-161). This method is recognized to be effective in preventing the adverse effects on the channel layer due to the surface contamination during ion implantation. However, S i O2, S j, a
N4.

The kQxos protective film has a drawback in that Si and O atoms in the i-retaining film enter the channel layer due to the knock-on effect during ion implantation, degrading the resistance value and electron mobility of the channel layer. In addition, in the activation process by heat treatment of the channel layer, 5iOz*5iaNa, AQxos
When used as a heat treatment protective film, these materials and Ga
Because the coefficient of thermal expansion is significantly different from that of the As substrate, stress is applied to the Ga As substrate during heat treatment, causing abnormal diffusion of the implanted atoms, making it difficult to obtain a channel layer with the desired thickness, or due to this stress. This method has the disadvantage that the deposited film peels off, resulting in a significantly lower yield of device fabrication.

The AlN film is described in US Pat. No. 1,105,8413 and the literature Electronics Letters: Electroni
As shown in csLetters, January 1984, Vol. 20, No. 1, pp. 45-47, the coefficient of thermal expansion is relatively the same as that of the GaAs substrate, and the above-mentioned defects due to stress are rare. In addition, the constituent elements of AlNM are ■
Since these elements belong to groups 1 and 2, the characteristics of the channel layer do not deteriorate even if these elements are knocked on during Q a As during ion implantation. By the way, when an integrated circuit is constructed on a GaAs substrate, processing techniques such as removing the above-mentioned protective film and providing an opening in a portion thereof are essential. The AlN film can be processed using a wet etching method using hot phosphoric acid, etc. or a chlorine-based gas (CCiAt, CHCQs,
A dry etching method based on S i CQt, B Cas, etc.) is used. However, as is well known, microfabrication of 1 μm or less is difficult with the wet etching method.

In addition, dry etching using chlorine gas does not provide etching selectivity with respect to GaAs substrates, so AlN is used as a surface protective film for GaAs large-scale integrated circuit elements that require microfabrication. The disadvantage is that membranes are extremely difficult to use.

[Purpose of the invention]

The purpose of the present invention is to stack SiN or 5ins on ApN thin pancreas to prevent deterioration due to contamination and knock-on effect during ion implantation, and to easily process AlN.
An object of the present invention is to provide a semiconductor device.

[Summary of the invention]

In the present invention, G a As MESF [! , T channels are formed using an AlN film as a surface-retaining film, through which n-type or p-type impurities are ion-implanted, and then SiN or
The method is characterized in that a protective film such as iOz is laminated and a heat treatment is performed using this as a protective film to activate the ion implantation layer. When performing heat treatment on a single AlN layer or a laminated film of 8ΩN, processing is performed by wet etching (HJIPO4), but it is extremely difficult to control processing accuracy with this method.

However, if the first AflN layer is set to 1100n or less,
SiN, Sj, and Ox are formed in the second layer.

Processing accuracy can be easily controlled by processing the second layer film using fluorine-based dry etching and wet etching the first layer AlN using HaPOa.

As shown in FIG. 4, SiN and 5ift are easily etched with fluorine gas and have sufficient selectivity to AlN. Therefore, SiN or 5iOz formed on AlN can be processed with high precision by dry etching.

FIG. 5 shows wet etching characteristics using Ha PO4. As is clear from the figure, AlN is easily etched, but the etch rate of SiN and 5ift is extremely low. Taking advantage of this property, after dry etching the second layer,
By etching the 1N thin film with H8P Oa, it is possible to process AlN with high precision while maintaining the shape of the second layer.

[Embodiments of the invention] The following will explain one embodiment of the invention.

In the examples, a case will be explained in which GaAs is used as the semiconductor substrate, but other I n P , I n
GaAs.

■~ of AQGaAs, InAQAs, InGaAsP, etc.
It is also possible to implement the method for group (Ⅰ) compound semiconductors.

Example 1 The manufacturing procedure of the first example is shown in FIGS. 6(a) to 6(i). First, in (a), an AflN film 14 with a thickness of 200 layers is deposited on the clean surface of the GaAs substrate 1. AlN
The film 14 is formed by sputtering, electron beam evaporation, reactive molecular beam epitaxy, or the like.

Next, moving to (b), a photoresist 8 having openings in the source and drain regions is deposited on the AlN film 14, and using this as a mask, ion implantation is performed to form the source region 3 and the drain region 4. conduct. If the thickness of the AlN film is 200, the energy for ion implantation is:
Approximately 100 KeV is optimal. In addition, the ion implantation concentration is 2×1018 ions/in the case of Si + ion implantation.
Let it be d.

Next, moving to (c), first, after completely removing the photoresist 8, a new photoresist 8' having an opening only in the channel region 2 is formed, and then using this as a mask, Si + ions for forming a channel are implanted. It's crowded. The optimal implantation energy is about 50 K e V when the thickness of the AlN film is 200, and the implantation concentration is 4XIO"/a1 for depletion type FET and 4XIO"/a1 for enhancement type FET.
In ET, it is 2×1012 pieces/d.

Next, move on to (d). First, after completely removing the photoresist mask 8' formed in (C),
Stack the N film. The SiN film is produced using a sputtering method using a sintered 5isN target in a mixed gas atmosphere of argon and nitrogen, or by sputtering with silane (SiHi) and nitrogen or ammonia (
NH3) plasma-enhanced chemical reaction (plasma CVD)
, dichlorosilane (S 1 Hzc Q z) or silane (SiHt) and N 2 Hs are used as raw materials for pyrolysis vapor phase chemical growth (CVD).

Next, using these SiN films and AlN films as surface protective films, heat treatment is performed in hydrogen at 800° C. for 20 minutes to activate the source/drain and channel regions.

Next, move on to (e). Here, a photoresist 8' having an opening in the electrode formation area on the source/drain region is formed by a photoresist process, and using this as a mask, the SiN film 14 is etched by dry etching using a fluorine gas (CF4, NFs, CHF3, etc.). ’ etched,
Further, the AlN film 14 is wet-etched using H4F04 (70°C). At this time, the SiN film 14' is ILRPO
Since etching is hardly caused by the etching process, the machining accuracy of the opening can be controlled extremely well.

Next, move to (f). Here, source/drain electrode materials 15, 15', 15', for example, A u G e /N
When unnecessary electrode material 15' is removed by selectively etching the photoresist 81 or removing it by a lift-off method, the source electrode 15,
The drain electrode 16 is formed, resulting in the structure shown in (g).

Next, as shown in (h), after forming a photoresist 8' having an opening in the gate electrode formation area above the channel region by a photoresist process, using this as a mask, the SiN film 14' is wet etched by the dry etching method. The AflN film 14' is etched by etching. After that, gate electrode material 16, 16', for example, Ti / P t / Au is deposited on the entire surface, and unnecessary gate electrode part 16' is removed using photoresist 8'.
As shown in i), an FET using a semiconductor-metal Schottky junction is completed.

According to this example, the SjN film can be dry-etched selectively with respect to the AflN film, and the AlN film can be wet-etched selectively with respect to SiN and 0sAs. As shown in Figure (i), an FET having a gate length of a submicron can be manufactured.

〔Effect of the invention〕

According to the present invention, in the initial step of the semiconductor device manufacturing process, the first layer used as a penetrating ion implantation protective film or a heat treatment protective film is the second AΩNΩN film layer i.
Covering with an insulating film made of N or S j,02 film has the following effects.

The second layer of SiN or 5iOz can be selectively etched with the AflN film by dry etching, and the first layer of AlN film can be etched with 5iOz or SiN and G s A s
It can be etched selectively with HaPO4. Due to this property, the first layer AflN film is set to 1100n or less, and 2
If SiN or 5iOz is formed in the layer, it becomes a sufficient surface protection film, and microfabrication of 1-μm or less becomes possible.

[Brief explanation of drawings]

Figure 1 shows an FE using a metal-semiconductor Schottky junction.
The cross-sectional structure diagram of T, Figures 2 and 3 are FE according to the conventional technology.
FIG. 4 is a cross-sectional view for explaining problems when forming a T-channel layer.
FIG. 5 is a diagram showing the dry etching rate of the s' film for various types of insulation, FIG. 5 is a diagram showing the wet etching rate using the same ()TsPOt, and FIG. 6 is a process sectional view for explaining one embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Semi-insulating GaAs substrate, 2... Channel layer, 3-... Source region, 4... Drain region, 5
, 16...gate electrode, 6,15...source electrode,
7.15'... Drain electrode, 8... Mask for ion implantation, 9... Protective film for heat treatment, 11... Protective film, 14... AlN film, 14'... SiN film, 17
...Dry etching speed of 5iNlljli, 18
...SiO2 dry etching speed, 19...G
a Dry etching speed of A s, 20... Dry etching speed of 80 N, 21... Wet etching speed of AlN, 22... Wet etching speed of SiN, 23... Wet etching speed of 5 ins 6

Claims (1)

[Scope of Claims] 1. A compound semiconductor device manufactured by a method including a step of covering the ion-implanted semiconductor surface with an insulating film consisting of two layers of AlN and SiN or SiO_2 and heat-treating it, and which includes a process other than the electrode forming part. A semiconductor device, wherein the semiconductor surface is covered with the insulating film. 2. A semiconductor device characterized in that the first layer on the semiconductor surface side is ion-implanted through an insulating film made of an AlN film, the second layer is covered with an insulating film of SiN, SiO_2, etc., and a heat treatment/processing process is included. manufacturing method.