JP4186267B2 - Method for manufacturing compound semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a GaAs compound semiconductor device that suppresses oxidization of a GaAs surface, suppresses generation of a recombination level on the surface, and suppresses the spread of a surface depletion layer, and a manufacturing method thereof.
[0002]
[Prior art]
Field effect transistors (FETs) made of GaAs semiconductors are used exclusively as high-frequency devices because of their high electron mobility in GaAs. However, the GaAs-FET is generally an FET (MESFET) whose gate electrode is formed by a metal-semiconductor junction, and is therefore strongly influenced by the characteristics of the semiconductor surface. In MESFET, a gate signal is applied to a metal gate electrode to control the width of a channel layer formed in the vicinity of the surface, thereby exerting an amplification effect. However, when the surface depletion layer that is essentially present in the semiconductor becomes large, the action of the gate signal is absorbed by the depletion layer, resulting in deterioration of FET performance (for example, mutual conductance).
[0003]
In order to alleviate this influence in the conventional FET, for example, as shown in FIG. 4, a gate electrode forming portion is dug by etching, and an electrode is formed in this recess. According to this method, since the channel layer is formed at a deep position from the surface, the influence of the depletion layer formed on both sides of the gate electrode is mitigated.
[0004]
[Problems to be solved by the invention]
However, since the characteristics of this FET are also determined according to the depth of the depression, that is, the distance from the bottom of the depression to the channel, an FET cannot be fabricated with good reproducibility and uniformity unless the depression depth is sufficiently controlled. There was a problem.
[0005]
[Means for Solving the Problems]
In order to overcome the above problems, the present invention is characterized in that after each electrode of the FET is formed, the semiconductor substrate is surface-treated with plasma containing phosphorus (P) and hydrogen (H). Here, after the surface treatment with hydrogen plasma, the sequential treatment with the surface treatment with phosphorus plasma may be used.
[0006]
[Action]
A natural oxide film is always formed on the surface of the GaAs substrate. As this oxide film, a Ga oxide film and an As oxide film are known, but the Ga oxide film is reduced and removed by decomposed hydrogen in plasma containing phosphine. Therefore, the surface changes to an As-rich state, and this state is passivated by phosphorus in the phosphine, and part of As is replaced with P to be converted into a stable compound in the air called GaP. Covered with. Therefore, the surface treated with phosphine plasma is protected by a clean and stable compound from which oxides have been removed, and is free of impurities and defects that cause the surface depletion layer to expand.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 and FIG. 2 are views for explaining a GaAs-FET processing method and the like according to the present invention, and show cross sections in each manufacturing process of the GaAs-FET. The present invention will be described below based on these drawings. In the following description, an example of an FET having a metal-semiconductor contact (Schottky connection) is shown, but the method according to the present invention is not limited to this, and an optical device, a high mobility transistor (HEMT) is used. ), Devices such as heterojunction bipolar transistors (HBTs).
[0008]
Impurities are selectively introduced onto the semi-insulating GaAs substrate 1 to form an n-type first impurity layer 5 (FIG. 1A). Since the n-type first impurity layer 5 becomes an active layer (channel layer) when the impurity is activated by heat treatment, it is formed between the source and drain regions of the FET formed in a later process. As a method of forming the impurity layer 5, for example, a resist pattern 3 is formed on the substrate 1 using a photolithography technique, and ion implantation is performed using the resist pattern 3 as a mask. As ion implantation conditions, ²⁹ Si is used as an ion species, an acceleration voltage is 30 [keV], and a dose is 2 × 10 ¹² [cm ⁻² ]. This implantation condition is determined on the basis of performance such as the threshold voltage and mutual conductance gm of the FET to be obtained.
[0009]
Next, an n-type impurity is introduced onto the GaAs substrate 1 to form a high-concentration n-type second impurity layer 9 (FIG. 1B). The high-concentration impurity layer 9 activates impurities introduced later by heat treatment and becomes n ⁺ layers in the source and drain regions, respectively. The source and drain regions are formed with the first impurity layer 5 formed in advance. The second impurity layer 9 is formed by ion implantation using the patterned photoresist 7 as a mask in the same way as the first impurity layer 5 is formed. The implantation conditions are ²⁹ Si as an impurity, an acceleration voltage of 120 [keV], and a dose of 2 × 10 ¹³ [cm ⁻² ]. Instead of ²⁹ Si, ²⁸ Si may be used. At this time, ²⁸ N ₂ contained in the beam must be sufficiently removed. In the case of the photoresist 7 or the first impurity layer 5 after the implantation, the resist pattern 3 is removed.
[0010]
After the implantation, a cap film 13 is formed on the surface of the substrate 1 (FIG. 1C). The cap film 13 functions as an annealing protective film, and SiN, SiON or the like is used. These films can be formed by an insulating film forming apparatus using a chemical vapor deposition (CVD) method. When heat treatment is performed on the substrate 1 after the formation of the cap film 13, the n-type first impurity layer and the n-type second impurity layer 9 are annealed, and the impurities introduced into each layer are activated, It becomes an active layer (channel layer) and an n ⁺ layer. After the annealing, the cap film 13 is removed and the substrate surface is exposed.
[0011]
Next, an ohmic metal 17 made of AuGe / Ni is formed on the n + layer (FIG. 2A). These forming methods are performed by physical vapor deposition (PVD) such as sputtering and vapor deposition. After all the metals are formed, for example, heat treatment is performed at 450 ° C. for 1 minute to alloy the GaAs substrate and the formed metal. Ga in GaAs moves to the metal side, and Ge replaces the vacancy after the movement, so that ohmic contact between GaAs and the metal is maintained. Ni is a metal for enhancing the wettability of AuGe to the GaAs surface.
[0012]
Next, the Schottky gate electrode 21 is formed (FIG. 2B). The gate electrode is formed of, for example, a Ti / Pt / Au laminated metal on the active layer 15 sandwiched between the source and drain electrodes. As a forming method, PVD methods such as sputtering and vapor deposition are used in the same manner as ohmic metals.
[0013]
Next, the substrate on which the ohmic and gate electrodes are formed is moved into a plasma irradiation apparatus and irradiated with phosphine plasma (FIG. 2C). The phosphine plasma does not act on the GaAs surface under the electrode metal, but acts on the region between the gate-ohmic electrode and on the substrate surface other than the FET formation region, thereby removing and stabilizing the oxide film on the GaAs surface.
[0014]
As conditions for phosphine plasma treatment,
Substrate temperature: 285 [° C]
Pressure: 0.2 [Torr]
Power density: 0.18 [W / cm2]
Frequency: 13.56 [MHz]
Processing time: 5 minutes. The details of these conditions depend on the FET manufacturing process. Phosphine may contain hydrogen as a base gas, and the plasma frequency is not limited to 13.56 MHz, and may be 2.35 GHz generally used in an ECR plasma apparatus, for example.
[0015]
The oxide on the GaAs surface exposed to the plasma is removed by the phosphine plasma treatment, and this surface is further replaced with P or GaP in which As vacancies in GaAs are filled with P in phosphine. Since it is covered with P, it becomes a very stable surface. By simply removing the surface oxide, the stoichiometry of the surface changes, and the formation of surface states due to this change has the adverse effect of increasing the surface depletion layer on the device characteristics. This surface must be treated with phosphine plasma. Thus, the surface depletion layer is not increased because the surface modification is performed while maintaining the stoichiometry simultaneously with the removal of the surface oxide.
[0016]
FIG. 3 (b) shows the characteristics of the gate voltage (Vg) -drain current (Id) of the FET subjected to the phosphine plasma treatment according to the present invention, in which the influence of light irradiation is observed. The solid line shows the result of measurement in the dark state when there is light irradiation. At this time, the threshold voltage of the FET was almost the same, and the drain voltage was constant at 3V. For reference, FIG. 3A shows the characteristics of an FET not subjected to phosphine plasma treatment.
[0017]
In an FET that is not subjected to plasma treatment, the absolute value of the obtained gate current is small for almost the same gate voltage, and the change in the drain current with respect to the change in the gate voltage (gm: mutual conductance, shown in the figure). The slope of the characteristic line is also small. Furthermore, in the phosphine plasma-untreated FET, the difference in drain current due to the presence or absence of light irradiation is also large.
[0018]
On the other hand, in the FET subjected to the plasma treatment, not only the value of the drain current obtained for the same gate voltage itself is large, but also the mutual conductance which is the slope of the characteristic line is large. Also, the change in drain current due to light irradiation is much smaller than that of unprocessed FETs.
[0019]
【effect】
This is because phosphine plasma treatment limits the size of the surface depletion layer formed between the gate electrode and the source electrode, and suppresses the generation of surface states that cause this surface depletion layer. is there. If the generation of the surface level is limited, the spread of the surface depletion layer due to this level is limited, and the influence on the device characteristics can be eliminated.
[Brief description of the drawings]
FIGS. 1A to 1C are schematic process cross-sectional views illustrating an embodiment of a GaAs-FET manufacturing process according to the present invention.
FIGS. 2A to 2C are schematic process cross-sectional views showing an embodiment of the GaAs-FET manufacturing process according to the present invention.
FIG. 3 is a diagram showing electrical characteristics of a GaAs-FET according to the present invention. The solid line shows the result in the light irradiation, and the broken line shows the result in the dark state.
FIG. 4 is a diagram showing a cross-sectional structure of a conventional MESFET.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semi-insulating GaAs semiconductor substrate 3 ... Resist 5 ... n-type 1st impurity layer 7 ... Resist 9 ... n-type 2nd impurity layer 11 ... Phosphine plasma 13 ... Cap film 15 ... active layer 17 ... ohmic electrode 19 ... n ⁺ layer 21 ... gate electrode

Claims (2)

In a field effect transistor having a source electrode and a drain electrode on the surface of a GaAs substrate and a gate electrode between the two electrodes,
After forming each of the electrodes, at least the substrate surface between the source electrode and the gate electrode is treated with phosphine plasma.
A method of manufacturing a field effect transistor. In a field effect transistor having a source electrode and a drain electrode on the surface of a GaAs substrate and a gate electrode between the two electrodes,
A method of manufacturing a field effect transistor, wherein after forming each electrode, at least a substrate surface between a source electrode and a gate electrode is subjected to a hydrogen plasma treatment and then a phosphorus plasma treatment .

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