JPS6329420B2 - - Google Patents
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- Publication number
- JPS6329420B2 JPS6329420B2 JP6854983A JP6854983A JPS6329420B2 JP S6329420 B2 JPS6329420 B2 JP S6329420B2 JP 6854983 A JP6854983 A JP 6854983A JP 6854983 A JP6854983 A JP 6854983A JP S6329420 B2 JPS6329420 B2 JP S6329420B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- semiconductor layer
- forming
- become
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000004065 semiconductor Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000002844 melting Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 11
- 230000008018 melting Effects 0.000 claims description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- -1 H + Chemical compound 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の製造方法、特にセルフ
アライン型砒比ガリウム電界効果トランジスタ
（以下GaAsFETと略称する）における動作層の
形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an active layer in a self-aligned arsenic gallium field effect transistor (hereinafter abbreviated as GaAsFET).
従来例によるこの種のセルフアライン型
GaAsFETの製造方法を第１図ａないしｄに示
す。
This type of self-aligning type according to conventional examples
A method for manufacturing a GaAsFET is shown in FIGS. 1a to 1d.
まず半絶縁性GaAs基板１上に第１のホトレジ
スト層２を塗着させ、これを通常のホトリソグラ
フイにより加工して、所定の動作層となるべき領
域対応に選択的に開口３を窓開けし、例えばイオ
ン種として 29Si+を用いたイオン注入により、濃
度1016〜1017cm-3の範囲のｎ型半導体層によるチ
ヤネル層となるべき領域４を形成し（第１図ａ）、
また前記ホトレジスト層２を除去したのち、前記
イオン注入層のアニール温度、こゝでは800±50
℃程度の高温熱処理によつても安定なシヨツトキ
障壁特性を維持し得る高融点金属、例えばTiW、
TiTa、TiWシリサイド、TiTaシリサイド、
Ta、Ｗ、およびMoなどを全面スパツタ蒸着、あ
るいは電子ビーム蒸着し、リアクテイブイオンエ
ツチングなどのドライエツチング技術を用いて、
前記領域４の所定の位置に高融点ゲート電極５を
選択的に形成する（第１図ｂ）。 First, a first photoresist layer 2 is coated on a semi-insulating GaAs substrate 1, and this is processed by normal photolithography to selectively form openings 3 in areas that are to become predetermined active layers. Then, by ion implantation using, for example, 29 Si + as the ion species, a region 4 to be a channel layer is formed of an n-type semiconductor layer with a concentration in the range of 10 16 to 10 17 cm -3 (FIG. 1a),
Further, after removing the photoresist layer 2, the annealing temperature of the ion implantation layer, here 800±50
High-melting point metals that can maintain stable shot barrier properties even when subjected to high-temperature heat treatment at temperatures around ℃, such as TiW,
TiTa, TiW silicide, TiTa silicide,
Ta, W, Mo, etc. are sputter deposited or electron beam deposited on the entire surface, and dry etching techniques such as reactive ion etching are used.
A high melting point gate electrode 5 is selectively formed at a predetermined position in the region 4 (FIG. 1b).
ついで前記と同様に第２のホトレジスト層６と
前記ゲート電極５とをマスクにして、このゲート
電極５の両側に、例えばイオン種として 29Si+、
S+、またはSe+などを用いたイオン注入により、
不純物濃度1018cm-3以上の高濃度のn+半導体層と
なるべき領域７を形成し（第１図ｃ）、さらに前
記ホトレジスト層６を除去したのち、水素雰囲気
中で800℃前後の温度によりアニールして、チヤ
ネル層としてのｎ型半導体層８、ソース領域とし
てのn+半導体層９、およびドレイン領域として
のn+半導体層１０を形成させ、かつ各n+半導体
層９，１０にソース電極１１、ドレイン電極１２
を形成させるのである（第１図ｄ）。 Next, in the same manner as above, using the second photoresist layer 6 and the gate electrode 5 as a mask, 29 Si + , for example, as an ion species is applied to both sides of the gate electrode 5.
By ion implantation using S + or Se + ,
After forming a region 7 to become a high-concentration n + semiconductor layer with an impurity concentration of 10 18 cm -3 or more (Fig. 1c), and removing the photoresist layer 6, the temperature is set at around 800°C in a hydrogen atmosphere. Annealing is performed to form an n-type semiconductor layer 8 as a channel layer, an n + semiconductor layer 9 as a source region, and an n + semiconductor layer 10 as a drain region. Electrode 11, drain electrode 12
(Fig. 1d).
しかし乍らこのような従来のセルフアライン技
術を用いた製造方法にあつては、各n+半導体層
９，１０が高融点ゲート電極５と直接接触して形
成されるので、ソース・ゲート間およびドレイ
ン・ゲート間の抵抗RsおよびRdを低減できる半
面、ソース・ゲート間およびドレイン・ゲート間
耐圧VgsoおよびVdsoが著るしく低くなつてしま
うという致命的な欠点を有している。 However, in the manufacturing method using such conventional self-alignment technology, each n + semiconductor layer 9, 10 is formed in direct contact with the high melting point gate electrode 5, so there is a gap between the source and gate and Although it is possible to reduce the drain-gate resistances Rs and Rd, it has a fatal drawback in that the source-gate and drain-gate breakdown voltages Vgso and Vdso are significantly lowered.
すなわち、例えば前記n+半導体層９，１０の
不純物濃度が1018cm-3で、ソース・ゲート間およ
びドレイン・ゲート間距離がそれぞれ2μｍの場
合、その耐圧VgsoおよびVdsoはいずれも約5V
前後の実用上支障をきたす程度の低い値を示す。
また一方、高融点ゲート電極５がソース領域とし
てのn+半導体層９と近接する結果、ゲート・ソ
ース間の寄生容量Cgsが著るしく増大してしまつ
て、素子の遮断周波数fT（＝gm／2πCgs）の低下
に代表される高周波性能の悪化、あるいはデジタ
ル集積回路に用いたときのイントリンシツクな伝
播遅延時間の増大などの素子劣化を招来すること
になるものであつた。 That is, for example, when the impurity concentration of the n + semiconductor layers 9 and 10 is 10 18 cm -3 and the source-gate and drain-gate distances are each 2 μm, the breakdown voltages Vgso and Vdso are both approximately 5V.
The value is so low that it causes problems in practical use.
On the other hand, as a result of the high melting point gate electrode 5 being close to the n + semiconductor layer 9 as a source region, the parasitic capacitance Cgs between the gate and source increases significantly, and the cutoff frequency f T (=gm This leads to deterioration of high-frequency performance, typified by a decrease in /2πCgs), and device deterioration, such as an increase in intrinsic propagation delay time when used in digital integrated circuits.
この発明は従来のこのような欠点に鑑み、高融
点ゲート金属に近接したn+半導体層の部分にの
み、選択的にイントリンシツク層形成のためのイ
オン種を注入して、同部分を低濃度化することに
より、耐圧、高周波特性を改善したものである。
In view of these conventional drawbacks, this invention selectively implants ion species for forming an intrinsic layer only into the portion of the n + semiconductor layer close to the high-melting point gate metal, thereby reducing the density of the same portion. By increasing the concentration, the breakdown voltage and high frequency characteristics are improved.
以下、この発明方法の一実施例につき、第２図
ａないしｆを参照して詳細に説明する。
Hereinafter, one embodiment of the method of the present invention will be described in detail with reference to FIGS. 2a to 2f.
この実施例方法においても、まず半絶縁性
GaAs基板１上に第１のホトレジスト２を塗着さ
せ、これを通常のホトリソグラフイにより加工し
て、所定の動作層となるべき領域対応に選択的に
開口３を窓開けし、イオン注入により不純物濃度
1016〜1017cm-3の範囲のｎ型半導体層によるチヤ
ネル層となるべき領域４を形成し（第２図ａ）、
また前記ホトレジスト層２を除去したのち、今度
は一旦、その全面にシリコン窒化膜Si3N4、ある
いはシリコン酸化膜SiO2などの絶縁膜１３を被
覆し、かつその上に第２のホトレジスト層１４を
塗着してから、所定のゲート電極を形成すべき部
分対応に、ホトリソグラフイにより選択的に開口
１５を窓開けする（第２図ｂ）。 In this embodiment method, first, semi-insulating
A first photoresist 2 is coated on a GaAs substrate 1, processed by normal photolithography, openings 3 are selectively opened in areas that are to become predetermined active layers, and then ion implantation is performed. Impurity concentration
A region 4 to be a channel layer is formed by an n-type semiconductor layer in the range of 10 16 to 10 17 cm -3 (FIG. 2a),
After the photoresist layer 2 is removed, the entire surface is once covered with an insulating film 13 such as a silicon nitride film Si 3 N 4 or a silicon oxide film SiO 2 , and a second photoresist layer 14 is formed on top of the insulating film 13 . After coating, openings 15 are selectively opened using photolithography in locations where predetermined gate electrodes are to be formed (FIG. 2b).
ついで前記第２のホトレジスト層１４をマスク
にして、開口１５の下部の絶縁膜１３を、通常の
プラズマエツチング、またはリアクテイブイオン
エツチングなどのドライエツチング技術によりエ
ツチングするが、このとき横方向へのサイドエツ
チング効果を生ずる（第２図ｃ）。その後、同様
にこの第２のホトレジスト層１４をマスクにし
て、ウエハ全面にスパツタ蒸着法、あるいは電子
ビーム蒸着法により、GaAsへのイオン注入層の
アニール温度、こゝでは800℃±50℃の高温熱処
理によつても安定なシヨツトキ障壁特性を維持し
得る高融点金属、例えばＷ、Ta、Mo、TiW、
TiTa、あるいはそのシリサイド金属を被着し、
引き続いていわゆるリフトオフ法により第２のホ
トレジスト層１４を溶融除去して、前記開口１５
に対応した範囲の領域４上にのみ、高融点ゲート
電極５を形成し、続いてこれらの絶縁膜１３、ゲ
ート電極５をマスクにして、その両者に挾まれた
幅のせまい領域、すなわち前記サイドエツチング
相当分の領域に、H+、O+、あるいはB+イオンな
どのGaAsに高抵抗層を形成するイオン種をイオ
ン注入して第２のｎ型半導体層となるべき領域１
６を形成する（第２図ｄ）。例えば、O+イオンの
注入の場合には、ドーズ量1016cm-3、注入エネル
ギ100keVの注入条件で深さ0.4〜0.7μｍにまで達
するため、前記１６の領域でのみ領域４のｎ型半
導体層の表面近傍より奥の結晶を高抵抗化するこ
とができる。 Next, using the second photoresist layer 14 as a mask, the insulating film 13 below the opening 15 is etched by a dry etching technique such as normal plasma etching or reactive ion etching. This produces an etching effect (Figure 2c). Thereafter, using the second photoresist layer 14 as a mask, the ion-implanted layer is annealed to GaAs at a high temperature of 800°C ± 50°C by sputter deposition or electron beam evaporation over the entire surface of the wafer. Refractory metals that can maintain stable shot barrier properties even after heat treatment, such as W, Ta, Mo, TiW,
Depositing TiTa or its silicide metal,
Subsequently, the second photoresist layer 14 is melted and removed by a so-called lift-off method to form the opening 15.
A high melting point gate electrode 5 is formed only on the region 4 in a range corresponding to A region 1 that is to become a second n-type semiconductor layer is implanted with ion species that form a high resistance layer in GaAs, such as H + , O + ions, or B + ions, into a region equivalent to etching.
6 (Fig. 2d). For example, in the case of O + ion implantation, the implantation conditions are a dose of 10 16 cm -3 and an implantation energy of 100 keV to reach a depth of 0.4 to 0.7 μm. It is possible to increase the resistance of the crystal deeper than near the surface of the layer.
さらに前記絶縁膜１３をドライエツチングによ
り除去した上で、第３のホトレジスト層１７をパ
ターニングし、前記高融点ゲート電極５とこの第
３のホトレジスト層１７をマスクにして、前記領
域４対応に前記と同様にイオン注入によりn+半
導体層となるべき領域７を形成し（第２図ｅ）、
かつ前記第３のホトレジスト層１７を除去したの
ち、水素雰囲気中で800℃±50℃の温度によりア
ニールして、所定濃度のチヤネル層としての第１
のｎ型半導体層８、ソース領域としてのn+半導
体層９、ドレイン領域としてのn+半導体層１０、
およびこれらの各層に挾まれた高抵抗層としての
所望濃度をもつ第２のｎ型半導体層１８を形成さ
せ、かつ各n+半導体層９，１０にソース電極１
１、ドレイン電極１２を形成させるのである（第
２図ｆ）。ここで、前記第２のｎ型半導体層とな
るべき領域１６では、高抵抗層を形成するイオン
種を注入することにより、アニール工程の前で
は、注入領域がアモルフアス化しているため、第
２図ｅに示す工程でのイオン注入において、チヤ
ネリング現象が起こらず、又、アニール時の活性
化率も小さくなる。その結果、第２の半導体体層
１８の注入深さは、n+半導体層９，１０におけ
るそれよりも浅くなると共に、その不純物濃度も
n+半導体層９，１０の1/3〜1/5（５×1016〜３×
1017cm-3）に低減できる。 Furthermore, after removing the insulating film 13 by dry etching, the third photoresist layer 17 is patterned, and using the high melting point gate electrode 5 and this third photoresist layer 17 as a mask, the above-mentioned pattern is patterned corresponding to the region 4. Similarly, a region 7 to become an n + semiconductor layer is formed by ion implantation (Fig. 2e),
After removing the third photoresist layer 17, it is annealed at a temperature of 800°C±50°C in a hydrogen atmosphere to form the first channel layer with a predetermined concentration.
an n-type semiconductor layer 8, an n + semiconductor layer 9 as a source region, an n + semiconductor layer 10 as a drain region,
A second n-type semiconductor layer 18 having a desired concentration as a high-resistance layer is formed between these layers, and a source electrode 1 is formed on each of the n + semiconductor layers 9 and 10.
1. A drain electrode 12 is formed (FIG. 2f). Here, in the region 16 which is to become the second n-type semiconductor layer, by implanting ion species forming a high resistance layer, the implanted region becomes amorphous before the annealing process, as shown in FIG. In the ion implantation in the step shown in e, no channeling phenomenon occurs, and the activation rate during annealing is also reduced. As a result, the implantation depth of the second semiconductor layer 18 becomes shallower than that of the n + semiconductor layers 9 and 10, and the impurity concentration also decreases.
1/3 to 1/5 of n + semiconductor layers 9 and 10 (5×10 16 to 3×
10 17 cm -3 ).
ここでこの実施例の場合、第２図ｃの工程にお
いて横方向へのサイドエツチング効果に伴ない、
第２図ｄにみられるように高融点ゲート電極５と
絶縁膜１３との間に形成されるところの極めて微
細なスリツト状部分から、選択的に所定加速エネ
ルギとドーズ量のイオン注入により、基板結晶に
ダメージを加えて高低抗層１６を形成させ、さら
に第２図ｅの工程でのイオン注入により、この高
抵抗層１６にも重ねてイオン注入がなされ、第２
図ｆでのアニール処理により高抵抗の第２のｎ型
半導体層１８を得ており、これによつて高融点ゲ
ート電極５と各n+半導体層９，１０との間に、
例えば0.2〜0.5μｍ程度の幅の第２のｎ型半導体
層１８が介在されることとなり、ソース・ゲート
間およびドレイン・ゲート間抵抗RsおよびRdの
低減効果を損うことなく、ゲート・ソース間耐圧
Vgsoおよびドレイン・ソース間耐圧Vdsoを飛躍
的に増大することができ、併せてゲート・ソース
間寄生容量Cgsを従来に比較して充分に小さく抑
え得て、GaAsFETのマイクロ波領域における高
周波特性およびGaAsデイジタル集積回路に適用
したときの伝播遅延時間特性を著るしく向上でき
るのである。そしてまた第２のｎ型半導体層１８
の形状は、ドライエツチング時の絶縁膜１３のサ
イドエツチング量、およびイオン注入条件によつ
てのみ決定されるので、微細な制御が可能とな
り、素子特性の再現性に優れているという利点も
ある。 In the case of this embodiment, due to the side etching effect in the lateral direction in the step of FIG. 2c,
As shown in FIG. 2d, the substrate is selectively implanted with a predetermined acceleration energy and dose from an extremely fine slit-shaped portion formed between the high melting point gate electrode 5 and the insulating film 13. The crystal is damaged to form a high-low resistance layer 16, and ions are further implanted into this high-resistance layer 16 in the step shown in FIG. 2e to form a second layer.
A high - resistance second n-type semiconductor layer 18 is obtained by the annealing process shown in FIG.
For example, the second n-type semiconductor layer 18 having a width of about 0.2 to 0.5 μm is interposed, so that the gate-source distance can be reduced without impairing the effect of reducing the source-gate and drain-gate resistances Rs and Rd. Pressure resistance
Vgso and the drain-source breakdown voltage Vdso can be dramatically increased, and the gate-source parasitic capacitance Cgs can be suppressed to a sufficiently small level compared to the conventional method. When applied to digital integrated circuits, propagation delay time characteristics can be significantly improved. And also the second n-type semiconductor layer 18
The shape is determined only by the amount of side etching of the insulating film 13 during dry etching and the ion implantation conditions, so there is an advantage that fine control is possible and the reproducibility of device characteristics is excellent.
以上詳述したようにこの発明方法によれば、
GaAs動作層の高融点金属を囲む微細な領域に、
ｎ型半導体層を再現性よく形成できるために、ゲ
ート・ソース間およびドレイン・ソース間耐圧を
低下させずに、高周波特性の優れたGaAsFETを
セルフアライン技術によつて容易に製造できる特
長がある。
As detailed above, according to the method of this invention,
In the fine region surrounding the high melting point metal of the GaAs active layer,
Since the n-type semiconductor layer can be formed with good reproducibility, GaAsFETs with excellent high frequency characteristics can be easily manufactured using self-alignment technology without reducing the gate-source and drain-source breakdown voltages.
第１図ａないしｄは従来例によるセルフアライ
ン型GaAsFETの製造方法を工程順に示す断面
図、第２図ａないしｆはこの発明の一実施例によ
るセルフアライン型GaAsFETの製造方法を工程
順に示す断面図である。
１……半絶縁性GaAs基板、２，１４，１７…
…第１、第２、第３のホトレジスト層、３，１５
……開口、５……高融点ゲート電極、８，１８…
…第１のｎ型半導体層（チヤネル領域）、第２の
ｎ型半導体層（高抵抗領域）、９，１０……n+半
導体層（ソース、ドレイン領域）、１１，１２…
…ソース、ドレイン電極、１３……絶縁膜。
1A to 1D are cross-sectional views showing a conventional method for manufacturing a self-aligned GaAsFET in order of process, and FIGS. 2A to 2F are cross-sectional views showing a method for manufacturing a self-aligned GaAsFET in order of process according to an embodiment of the present invention. It is a diagram. 1... Semi-insulating GaAs substrate, 2, 14, 17...
...first, second, and third photoresist layers, 3, 15
...Opening, 5...High melting point gate electrode, 8, 18...
...First n-type semiconductor layer (channel region), second n-type semiconductor layer (high resistance region), 9, 10...n + semiconductor layer (source, drain region), 11, 12...
...source, drain electrode, 13...insulating film.
Claims (1)
作層となるべき領域を選択的に形成する工程と、
全面に絶縁膜を被覆し、かつこの絶縁膜上にホト
レジスト層を塗着して、このホトレジスト層のゲ
ート電極を形成すべき部分対応に選択的に開口を
窓開けする工程と、開口下部の絶縁膜をサイドエ
ツチング効果を伴なうエツチングにより選択的に
部分除去する工程と、前記動作層となるべき領域
上にあつて前記開口対応に高融点ゲート電極を形
成し、かつこの高融点ゲート電極と前記絶縁膜間
のサイドエツチングされたせまい領域にイオン注
入によつて高抵抗層を形成する工程と、前記絶縁
膜を除去したのちに、前記高融点ゲート電極をマ
スクとして、前記動作層となるべき領域に、イオ
ン注入によりn+半導体層となるべき領域を形成
する工程と、水素雰囲気中で高温度アニールし
て、所定濃度のチヤネル層としての第１のｎ型半
導体層、ソースおよびドレインとしてのn+半導
体層、およびこれらの各層に挟まれた第２のｎ型
半導体層を形成させる工程とを含むことを特徴と
する半導体装置の製造方法。1. A step of selectively forming a region to become an active layer on a semi-insulating GaAs substrate by ion implantation,
A process of coating the entire surface with an insulating film, applying a photoresist layer on the insulating film, and selectively opening an opening in the photoresist layer corresponding to the part where the gate electrode is to be formed, and insulating the lower part of the opening. a step of selectively removing a portion of the film by etching with a side etching effect; forming a high melting point gate electrode corresponding to the opening on the region to become the active layer; A step of forming a high resistance layer by ion implantation in the side-etched narrow region between the insulating films, and after removing the insulating film, using the high melting point gate electrode as a mask, forming a high resistance layer to become the active layer. A step of forming a region to become an n + semiconductor layer in the region by ion implantation, and high-temperature annealing in a hydrogen atmosphere to form a first n-type semiconductor layer with a predetermined concentration as a channel layer, a source and a drain. A method for manufacturing a semiconductor device, comprising the steps of forming an n + semiconductor layer and a second n-type semiconductor layer sandwiched between these layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6854983A JPS59194476A (en) | 1983-04-18 | 1983-04-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6854983A JPS59194476A (en) | 1983-04-18 | 1983-04-18 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59194476A JPS59194476A (en) | 1984-11-05 |
| JPS6329420B2 true JPS6329420B2 (en) | 1988-06-14 |
Family
ID=13376945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6854983A Granted JPS59194476A (en) | 1983-04-18 | 1983-04-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59194476A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04264445A (en) * | 1991-02-19 | 1992-09-21 | Brother Ind Ltd | Image forming device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0824132B2 (en) * | 1985-10-18 | 1996-03-06 | 株式会社日立製作所 | Method for manufacturing field effect transistor |
-
1983
- 1983-04-18 JP JP6854983A patent/JPS59194476A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04264445A (en) * | 1991-02-19 | 1992-09-21 | Brother Ind Ltd | Image forming device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59194476A (en) | 1984-11-05 |
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