JPS6258154B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a Schottky gate field effect transistor (hereinafter referred to as "field effect transistor") using a compound semiconductor such as GaAs.
(referred to as MESFET).

[Technical background of the invention and its problems]

GaAs MESFETs are widely used as individual semiconductor elements that constitute high-frequency amplifiers and oscillators. Recently, it is also playing an important role as a basic element of GaAsIC. In both of these applications, it is necessary to fully exploit the performance of GaAsFETs. As is well known, the high frequency figure of merit of GaAsFET is described by C _gs 〓 _gn . Here C _gs
is the gate-source capacitance, and g _n is the mutual conductance of the FET. The high frequency figure of merit is improved by reducing C _gs and increasing g _n . Focusing on g _n , the actual g _n of the FET
It is known that g _n =g _np /1+g _np R _s . g _np is the intrinsic transconductance determined by the characteristics of the channel section of the FET. This is the maximum g _n that can be extracted, but in reality there is a series resistance R _s between the source and the gate, and as shown in the above equation, the actual g _n becomes smaller than g _np . Therefore, how to reduce this R _s is one of the keys to obtaining a large mutual conductance and improving the high frequency characteristics of the FET.

The other is to increase g _np itself.
An effective means of increasing g _np without increasing C _gs is to shorten the gate length (L _g ). This is because there is a relationship C _gs ∝L _g , g _np ∝ ¹ /L _g .

As described above, as technologies for improving the high frequency performance of GaAs MESFETs, it is desired to develop (1) technology for reducing parasitic resistance and (2) technology for shortening gate length.

A self-alignment method is known as a method for reducing the series resistance R _s of MESFET. There are several methods for this, but a typical one is to implant high-concentration ions using the gate electrode 13 as a mask, as shown in Figure 1, to increase the electron concentration.
Source/drain regions 14, 15 of 10 ¹⁸ cm ^-3 or more
In this method, the gate electrode 13 is formed close to the gate electrode 13. 11 is a semi-insulating GaAs crystal, 12 is an active layer,
16 and 17 are source and drain electrodes, respectively. The most difficult technique in this method is the selection of a heat-resistant gate electrode metal. An annealing process is required to transform the source/drain regions into high electron concentration layers into which high concentration ions are implanted using the gate electrode as a mask, and the annealing temperature for the donor ion implanted layer into GaAs is usually about 800°C. Even after such a high-temperature annealing process, it is necessary that the gate electrode used as a mask and the GaAs have a good Schottky barrier. There are only a few metals that can form a good Schottky barrier with GaAs under these harsh conditions. Heat-resistant metals such as W, Mo, Ta, and Ti, and heat-resistant metal alloys such as Ti/W mainly have this potential. In fact, experimental examples of self-aligned GaAs MESFETs with Ti/W gates have been reported (for example, N. YOKOYAMA
etal.1981ISSCC). However, these heat-resistant metals generally have poor mechanical adhesion to GaAs, making it difficult to obtain good bonding with good reproducibility.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a high-performance self-aligned MESFET that solves the above-mentioned problems.

[Summary of the invention]

In the method of the present invention, a relatively thick first insulating film is first deposited on a compound semiconductor substrate, and this is selectively etched using an anisotropic etching method to etch a source layer.
The substrate surface of the drain formation region is exposed and ion implantation is performed to form source/drain regions.
Thereafter, the side surface of the first insulating film is partially etched by an isotropic etching method while leaving the first mask used for etching the first insulating film intact. After that, the first mask is removed, a second insulating film with good step coverage is deposited on the entire surface, and this is etched on the entire surface using an anisotropic etching method, leaving only the sidewalls of the first insulating film. let Then, an organic film is applied to planarize the surface, a second mask having an opening slightly larger than the gate electrode region is formed thereon, and the organic film is selectively etched to form the first mask in the gate electrode formation region. The surface of the insulating film is exposed, and the exposed first insulating film is removed by etching to expose the surface of the substrate in the gate electrode formation region. Next, a first metal film is deposited, and this is subjected to a lift-off process by removing the organic film to form a gate electrode. Next, a second metal film is deposited to form an ohmic electrode on the gate electrode and the source/drain region, which is automatically separated by the second insulating film remaining in a convex shape around the gate electrode. .

〔Effect of the invention〕

According to the present invention, after ion implantation is performed using the first insulating film patterned by an anisotropic etching method as a mask to form source/drain regions, the first insulating film is side-etched to form a gate. The length can be shortened with good controllability, and the gate electrode and the source/drain regions can be separated by a minute distance with good controllability. In addition, since the second insulating film is deposited on the uneven surface of the first insulating film used as an ion implantation mask, if an annealing process is performed to activate the ion-implanted impurities in this state, the surface of the thin active layer will be is protected. Furthermore, with this second insulating film remaining on the sidewall of the first insulating film, a first metal film is deposited, and this is subjected to a lift-off process to form a gate electrode, and then a second metal film is deposited. By depositing the source and drain electrodes, the source and drain electrodes are formed in self-alignment with the gate electrode, separated by the width of the second insulating film.

From the above, it is possible to obtain a self-aligned MESFET with sufficiently low source resistance, small gate capacitance, high-speed operation, and high drain breakdown voltage.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below using FIGS. 2 a to i. Si ⁺
Ion acceleration energy: 60keV, dose: 1.1×10 ¹²
Selective ion implantation at cm ^-2 in arsine atmosphere
Annealed at 850°C for 15 minutes to form n-type active layer 2.
2, a SiO ₂ film 23 with a thickness of 1 μm is deposited as a first insulating film by CVD.
Next, a resist pattern 24 is formed as a first mask having openings in the source/drain formation regions, and is etched by reactive ion etching (RIE).
The SiO ₂ film 23 is etched to expose the substrate surface, and Si ⁺ ions are implanted at 200 keV and 3.0 to 10 ¹³ cm ^2.
forming n ⁺ layers 25 ₁ and 25 ₂ b. At this time RIE
Since the selectivity ratio of SiO ₂ to photoresist can be as large as 5:1 or more, the sides of the SiO ₂ film 23 are steep at approximately 90°. Additionally, _SiO2
Since the selectivity to GaAs is also 10:1 or more, it is easy to finish the etching of the SiO ₂ film 23 on the GaAs surface.

Next, the SiO ₂ film 23 is etched using a normal cylindrical plasma etching apparatus while leaving the resist pattern 24. As an etching gas
Using a mixture of _CF4 and _O2 , the flow rate was 15% each.
cc/min, 5c.c./min, etching gas pressure
At 0.1Torr, the high frequency power is 100W. In the cylindrical plasma etching apparatus under these conditions, the SiO ₂ film is etched isotropically, and the etching rate is
It is 100 Å/min.

If etching is performed for 20 minutes under these conditions, the resist pattern 24 and the GaAs substrate are not etched, so the side surface of the SiO ₂ film 23 recedes by 0.2 μmc.

In this way, first, after processing the side wall of the SiO ₂ film 23 vertically using RIE, which is anisotropic dry etching,
Since side etching is performed using plasma etching, which is isotropic dry etching, the amount of side etching can be controlled very precisely. In addition, since it is all dry etched,
Uniformity within the wafer and between wafers is also very good.

Furthermore, in general, during ion implantation, the substrate is tilted at an angle of about 5 to 10 degrees to avoid the influence of planar channeling, so if the SiO ₂ film 23 is etched only by isotropic etching, either the source or drain region will be etched. There is a risk that one side may be placed closer to the gate area than necessary. However, in this example, since side etching is performed after ion implantation, the n ⁺ layer 25
₁ , 25 ₂ and the SiO ₂ film 23 can be precisely controlled.

After thinning the SiO ₂ film 23 on the gate electrode formation region as described above, the resist pattern 24 is removed and a second insulating film is formed by plasma CVD.
Depositing a Si ₃ N ₄ film 26 of 1 μm d. This method has very good step coverage and can completely cover irregularities on the substrate.

In this state, annealing is performed at 800° C. for 10 minutes to electrically activate the n ⁺ layers 25 ₁ and 25 ₂ . At this time, the entire GaAs surface is covered with a SiO ₂ film 23 or a Si ₃ N ₄ film 26, and these films act as a protective film during annealing, so the normal
Annealing can be performed in an atmosphere of N ₂ , H ₂ , Ar, or the like.

After this, perform RIE with CF ₄ gas on the entire surface...
The Si ₃ N ₄ film 26 is etched by an amount corresponding to its thickness. As a result, due to the anisotropy of RIE, the part where the film thickness was effectively thickened, that is, the SiO ₂ film 2
The Si ₃ N ₄ film 26 remains only on the side walls of 3 e.

Next, a resist film 27 is applied to flatten the surface. At this time, use a positive resist with a viscosity of 20 cp.
When spin coating is performed at 6,000 rpm for 30 seconds, the surface of the resist becomes flat because the side walls of the concave and convex portions on the wafer are gentle and the area of the concave portions is smaller than that of the convex portions. Further, the film thickness is normally about 1 μm on the convex portions, that is, the SiO ₂ film 23, and about 2 μm on the concave portions due to its viscosity.
Following the application of this resist film 27, a Mo film 28 serving as a second mask is deposited to a thickness of 1000 Å, and then a resist pattern 29 having an opening slightly larger than the gate portion is formed f. At this time, the resist pattern 29 can have a margin of about 1 μm with respect to the gate portion, and patterning can be performed by normal alignment.

Then, the Mo film 28 is coated with a mixed gas of CF ₄ and O _2.
After etching by RIE, using this as a mask, the resist film 27 is etched by RIE using O ₂ gas to expose the surface of the SiO ₂ film 23g. The RIE conditions are an O ₂ gas flow rate of 10 c.c./min and a gas pressure of 10 c.c./min.
When 0.05 Torr and high frequency power are selected as 100 W, the resist film 27 is etched at a rate of 800 Å/min. When etching is performed for 15 minutes under these conditions, the SiO ₂ film 23 and the SiN film 2 on its sidewall are removed as shown in the figure.
The head of 6 is exposed, and the other parts are covered with resist film 2.
7 remains. At this time, RIE has excellent controllability and uniformity in the processability of the resist film 27, and also has a thinner part of the resist film 27, that is, the upper part of the SiO ₂ film 23.
μm, the thick part is 2 μm on the GaAs substrate, and there is a margin of 1 μm, so it is impossible to finish RIE so that the top of the SiO ₂ film 23 is exposed and the resist film 27 is left in other parts of the pattern. It's very easy.

After this, the SiO ₂ film 23 whose head is exposed is selectively removed. If an aqueous mixed solution of ammonium fluoride and hydrofluoric acid is used, only the SiO ₂ film 23 can be etched without etching the Si ₃ N ₄ film 26. After removing the SiO ₂ film 23 in this way, Ti/Ti/
A laminated film is formed by continuously depositing Pt/Au to a thickness of 500 Å, 500 Å, and 1500 Å, respectively, and a lift-off process is performed to remove unnecessary metal on the resist film 27 together with SiO ₂ membrane 2
Gate electrode 30 is formed only in the area marked 3h. At this time, metal is also attached to the exposed portion of the Si ₃ N ₄ film 26, but the side walls of the Si ₃ N ₄ film 26 are covered with the SiO ₂ film 2.
It is vertically cut reflecting the shape of 3, and the metal inside the gate and the metal on the top of the Si ₃ N ₄ film 26 are separated as shown in the figure.

Next, a resist pattern is formed that is the same as the active layer or as wide as the margin during patterning, an Au--Ge film is deposited as a second metal film, and this is subjected to a lift-off process. At this time, for the same reason as mentioned above, the ohmic electrode 31 ₁ is automatically separated into the inside of the gate and the source/drain part.
~ ₃₁₃ is formed. Furthermore, the distance between the gate electrode and the source/drain electrode is determined by the width of the Si ₃ N ₄ film 26 and is as small as 0.6 to 0.8 μm, and is not affected by misalignment during patterning. Furthermore, on the top of the gate electrode
Since the Au--Ge ohmic electrode ₃₁₃ is attached, gate resistance can be reduced.

As a result of prototyping MESFET using the above process, the n ⁺ layer 25 ₁ , determined by the minimum dimension of the mask,
25 Despite the fact that the distance between ₂ is 1 μm, the actual gate length is as small as 0.6 μm, and the distance between the gate electrode, source region, and drain region is 0.2 μm.
The distance between the gate electrode and the source/drain ohmic electrodes is 0.6 to 0.8 μm, which is sufficiently small, so the source resistance and gate capacitance are small.Furthermore, since there is an AuGe alloy on the top of the gate electrode, the gate resistance is also small enough. Therefore, it is a high-performance FET that is capable of high-speed operation and has a drain breakdown voltage of 10V or more.
was gotten. Moreover, since the processing of the pattern of the insulating film transferred to the gate electrode was performed entirely in a dry etching process, the FET characteristics had very uniformity with little variation within the wafer and between wafers. .

Note that the present invention is not limited to the above embodiments. For example, the active layer of the substrate may be an epitaxially grown layer. Moreover, as the first and second insulating films,
In addition to the combination of SiO ₂ and Si ₃ N ₄ , it is possible to select a combination that allows anisotropic etching and has different etching characteristics.

Furthermore, the organic film for surface flattening is not limited to photoresist, but may be made of polyimide as long as it can be dry etched and subsequently lifted off. In addition, although a Mo film was used as the second mask in the example, a resist pattern 2 was used instead of this Mo film to etch it.
9 may be made of a different material from the underlying resist film 27 for planarization, and may itself be used as a second mask. In addition, the present invention can also be applied to cases where other compound semiconductors such as InP are used.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the structure of a GaAs MESFET according to a conventional method, and FIGS. 2 a to 2 i are diagrams showing the manufacturing process of a GaAs MESFET according to an embodiment of the present invention. 21...Semi-insulating GaAs substrate, 22...n-type active layer, 23...SiO ₂ film (first insulating film), 24...
...Resist pattern (first mask), 25 ₁ ,
25 ₂ ...n ⁺ layer (source/drain region), 26
...Si ₃ N ₄ film (second insulating film), 27 ... resist film (organic film), 28 ... Mo film (second mask),
29...Resist pattern, 30...Ti/Pt/
Au gate electrode (first metal film), 31 ₁ to 31 ₃
...Au-Ge ohmic electrode (second metal film).

Claims (1)

[Claims] 1. A step of depositing a first insulating film on a compound semiconductor substrate, and forming a first mask having openings in source/drain formation regions on the first insulating film to obtain anisotropic properties. A step of selectively etching the first insulating film by an etching method to expose the substrate surface, and performing ion implantation using the first mask and the first insulating film thereunder as masks to form source/drain regions. a step of partially etching the side surface of the first insulating film left under the first mask using an isotropic etching method;
removing the mask and depositing a second insulating film with good step coverage over the entire surface, and etching the second insulating film uniformly over the entire surface by an anisotropic etching method to form the sidewalls of the first insulating film. 2nd only
a step of leaving an insulating film, a step of coating the entire surface with an organic film to flatten the surface, and forming a second mask having an opening in a region including the gate electrode formation region on the organic film. selectively etching the organic film to expose the surface of the first insulating film in the gate electrode forming region; selectively etching the exposed first insulating film to expose the substrate surface in the gate electrode forming region; After that, by depositing a first metal film and removing the organic film,
A step of forming a gate electrode by lift-off processing, and depositing a second metal film while leaving the second insulating film around the gate electrode, and depositing a second metal film on the gate electrode and on the source/drain regions, respectively. A method of manufacturing a Schottky gate field effect transistor, comprising the step of forming an ohmic electrode separated by the second insulating film. 2 The compound semiconductor substrate has an active layer formed on the surface of a semi-insulating GaAs substrate, the first metal film is a Ti/Pt/Au stacked film, and the second metal film is an Au layer.
- A method for manufacturing a Schottky gate field effect transistor according to claim 1, which is a Ge film. 3 The first insulating film is a SiO ₂ film made by CVD method, and the second insulating film is made by plasma CVD method.
A method for manufacturing a Schottky gate field effect transistor according to claim 1, which is a Si ₃ N ₄ film.