JPH04350945A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To improve uniformity and reproducibility by prescribing the gate length which requires microdimension with first and second side wall thicknesses. CONSTITUTION:After first side walls 1a, 15b made of a high melting point metal or a high melting point silicide are formed into an insulation film pattern 13, second side walls 16a, 16b made of an insulation film are formed into the insulation film pattern 13. Next, that side 15b of the first side walls 15a, 15b which does not serve as a gate electrode and a similar side 16b of the second side walls 16a, 16b are obliquely etched off. A thus obtained insulation film pattern 13 having first and second side walls 15a, 16a only on one side and a photoresist are used a mask for high concentration implantation of an impurity of the same conductivity type as that of an active layer 12 to form a high-doped region serving as source-drain regions 18a, 18b. This process provides high uniformity and reproducibility.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to field effect transistors, and more particularly to a method for manufacturing an asymmetric n+ structure field effect transistor having low source resistance and high drain breakdown voltage.

0002

[Prior Art] Conventional transistors of this type include:
The distance L1 between the gate electrode 23 and the source (n+) region 26a as shown in FIG.
There is a field effect transistor (FET) with an asymmetric n+ structure in which the distance between the regions 26b is smaller than the distance L2. This is L1=L2
Compared to the symmetric n+ structure FET, it has the advantage of being able to achieve both low source resistance and high drain breakdown voltage. In addition, in the figure,
21 is a GaAs semi-insulating substrate, 22 is an n-type active layer, 28
, 29 are a source electrode and a drain electrode, respectively.

FIGS. 9, 10 and 11 show conventional asymmetric n
A method for manufacturing a FET with a + structure is shown. As shown in FIG. 9, Si ions are selectively implanted into a semi-insulating GaAs substrate 21 to form an n-type active layer 22, and a refractory metal silicide such as WSi or WN is deposited on the entire surface, followed by RIE ( A gate electrode 23 is formed by a reactive ion etching method. Next, as shown in FIG. 10, after covering the entire surface with an insulating film 24 such as a SiN film or a SiO2 film, Si ions are implanted using the photoresist 25 as a mask to form a source region 26a and a drain region 26b. Next, as shown in FIG. 11, after removing the insulating film 24, ohmic metals AuGe/Ni/Au are deposited using a photoresist 27, lift-off is performed, and an ironing process is performed to form the source electrode 2.
8. Form the drain electrode 29 to obtain the FET shown in FIG.

0004

[Problem to be solved by the invention] In the above conventional method, FIG.
As shown in FIG. 0, an asymmetric structure was obtained by properly aligning the gate 23 and the photoresist 25. However, the conventional manufacturing method, which relies on alignment in the photolithography process to control L1 and L2, has a gate length La≦0.1 μm, L1 to 0.1 μm, and L2=0.
．． Ultra-high frequency FE that requires fine dimensions of 2 to 0.5 μm
It is unreasonable to apply it to T in terms of alignment accuracy,
It is very difficult to obtain high yield, high within-wafer uniformity, and high wafer-to-wafer uniformity.

The present invention was made in view of these problems, and an object of the present invention is to provide a method for manufacturing an asymmetric n+ structure FET having a gate with La≦0.1 μm.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the method for manufacturing a field effect transistor of the present invention involves performing ion implantation to form an active layer on the main surface of a semiconductor substrate, and then implanting ions on the same surface. forming an insulating film pattern on the active layer when forming a field effect transistor by juxtaposing a source electrode, a gate electrode, and a drain electrode;
forming a first sidewall made of a high melting point metal or high melting point metal silicide on the insulating film pattern; and a second sidewall further made of an insulating film on the insulating film pattern having the first sidewall of the high melting point metal. and forming a side of both sides of the first side wall that does not become a gate electrode and the same side of the second side wall using an oblique RIE (reactive ion etching) method or an oblique ECR (electron cyclotron resonance) etching method. and ion implantation of an impurity having the same conductivity type as the active layer at a high concentration using the insulating film pattern and photoresist having the first sidewall and the second sidewall on one side obtained by this step as a mask. a step of forming a high concentration region to become a source and drain region; a step of activating the active layer and the high concentration layer region by heat treatment; and a step of forming source and drain electrodes on the high concentration layer region. It is characterized by containing.

[0007]

[Operation] In the FET manufacturing method of the present invention, La and L1, which require minute dimensions, are defined by the thicknesses of the first and second side walls, respectively. Therefore, unlike the conventional manufacturing method that relies on a photolithography process that is difficult to control at the 0.1 μm level, these controls rely on a sidewall forming process that can be precisely controlled.
High uniformity and reproducibility can be easily obtained.

[0008]

[Examples] Examples of the present invention will be described below. 1 to 7 are diagrams for explaining the manufacturing process of the present invention. First, as shown in FIG. 1, a photoresist (not shown) is used as a mask on a semi-insulating GaAs substrate 11, and S
An n-type active layer 12 is formed by selectively implanting i ions. The implantation conditions were 50 KeV and 2 x 1012 cm-2. After that, a 500 nm SiO2 film was deposited on the entire surface and RI
The insulating film pattern 13 is obtained by processing and forming by the method E. The dimension (L2) of the insulating film pattern in the source/drain direction was 0.3 μm. The RIE processing conditions are CHF3 gas (3
0SCCM), RF power of 100 W, back pressure of 10 Pa, and etching rate of 30 nm/min. Furthermore, WN film 1
4 is deposited to a thickness of 100 nm over the entire surface.

Next, as shown in FIG. 2, first side walls 15a and 15b are formed by RIE. The RIE processing conditions at this time are CF4 (30SCCM) + O2 (3SCCM)
Mixed gas, RF power of 100 W, back pressure of 5 Pa, and etching rate of 50 nm/min. Next, as shown in FIG. 3, after depositing a SiN film to a thickness of 100 nm over the entire surface (not shown), second side walls 16a and 16b are formed by RIE. The RIE processing conditions at this time are CHF3 (45SCCM
)+O2 (5SCCM) mixed gas, RF power 100W
, a back pressure of 2 Pa, and an etching rate of 100 nm/min.

Next, as shown in FIG. 4, the side walls 15b and 16b on one side are removed using the oblique ECR method.

[0011]The ECR processing conditions at that time were CF4 (30S
CCM) + O2 (3SCCM) mixed gas, RF power 1
00W, back pressure 10Pa. Total etching time is 4
It was a minute. The incident angle of ECR gas is 60 degrees from the substrate surface.
It was set as degree.

Next, as shown in FIG.
7. Using the insulating film pattern 13, the first sidewall 15a, and the second sidewall 16a as a mask, Si ions are implanted to form a source region 18a and a drain region 18b. The implantation conditions were 100 KeV and 2×10 13 cm −2 . After removing the photoresist 17, activation heat treatment is performed. The heat treatment conditions were RTA (rapid annealing) at 850°C;
It is 5 seconds.

Next, as shown in FIG.
Ohmic metal AuGe (130 nm)/
Ni (30 nm)/Au (200 nm) is deposited and lifted off to form a source electrode 110a and a drain electrode 110.
b is formed, and alloying is performed at 440° C. for 1 minute in a hydrogen atmosphere to complete the desired FET shown in FIG.

In order to investigate the effect of this example, L1 (0.1 μm) and L2 (0.3 μm), which are the same as the FET of this example, were used.
and La (0.1 μm) by conventional manufacturing method.
When T was fabricated, the manufacturing method of this example was superior in terms of yield of 30% or more and uniformity (both within the wafer surface and between wafers) of 20% or more.

In this embodiment, the insulating film pattern is made of SiO
Although the second film and the second side wall were made of a SiN film, other types of insulating films may be used as long as the desired processed shape can be obtained. 1st
Similarly, the side walls of the film may be made of other than WN film.

[0016]

[Effects of the Invention] As is clear from the above, the present invention has an extremely short gate suitable for an ultra-high frequency FET,
In addition, FETs with an asymmetric n+ structure can be manufactured with high yield and high uniformity.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a first step of a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a configuration explanatory diagram showing the second step of the manufacturing process in the above embodiment.

FIG. 3 is a configuration explanatory diagram showing the third step of the manufacturing process in the above embodiment.

FIG. 4 is a configuration explanatory diagram showing the fourth step of the manufacturing process in the above embodiment.

FIG. 5 is a configuration explanatory diagram showing the fifth step of the manufacturing process in the above embodiment.

FIG. 6 is a configuration explanatory diagram showing the sixth step of the manufacturing process in the above embodiment.

FIG. 7 is a configuration explanatory diagram showing the seventh step of the manufacturing process in the above embodiment.

FIG. 8 is a configuration explanatory diagram showing a conventional example.

FIG. 9 is a configuration explanatory diagram showing the first step of a conventional manufacturing method.

FIG. 10 is a configuration explanatory diagram showing the second step of the conventional manufacturing method.

FIG. 11 is a configuration explanatory diagram showing the third step of the conventional manufacturing method.

[Explanation of symbols]

11 GaAs semi-insulating substrate 12 Active layer 13 Insulating film pattern 14 Insulating film 15 Gate electrodes 15a, 15b First sidewall (gate electrode) 16
a, 16b Second sidewalls 17, 19 Resist 18a Source region 18b Drain region 110a Source electrode 110b Drain electrode

Claims (1)

[Claims] Claim 1: When ion implantation is performed to form an active layer on the main surface of a semiconductor substrate, and then a source electrode, a gate electrode, and a drain electrode are juxtaposed on the same surface to form a field effect transistor, forming an insulating film pattern on the active layer; forming a first sidewall made of a refractory metal or a refractory metal silicide on the insulating film pattern; A step of further forming a second sidewall made of an insulating film on the insulating film pattern, and etching the side of both sides of the first sidewall that does not become a gate electrode and the same side of the second sidewall using an oblique reactive ion etching method or an oblique process. A step of removing by electron cyclotron resonance etching method, and using the insulating film pattern and photoresist having the first side wall and the second side wall on one side obtained by this step as a mask, the pattern becomes the same conductivity type as the active layer. a step of ion-implanting impurities at a high concentration to form high concentration regions that will become source and drain regions; a step of activating the active layer and the high concentration layer region by heat treatment; A method for manufacturing a field effect transistor, comprising the step of forming a drain electrode.