JPH03289142A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To improve the voltage resistance of a drain by forming the lateral end face of a resist layer in inclination to a substrate so that the vertical projection length of a gate electrode to the substrate be larger than the gate length of the gate electrode. CONSTITUTION:A resist layer 3 is formed on a GaAs substrate 1 on the surface of which an active layer 2 is formed by ion implantation. The resist layer 3 is formed to be tapered so that the lateral end face 3b thereof has a prescribed angle to the substrate 1. In succession, a high-melting metal layer 4 is deposited uniformly on the surfaces of the substrate 1 and the resist layer 3 by a sputtering method. Next, the high-melting metal layer 4 is etched uniformly from above by an RIE method and thereafter the resist layer 3 is removed. Then a gate electrode 4b is formed of a highmelting metal on the substrate. Next, an N<+> conductive layer 5 is formed in the substrate 1 by ion implantation into the substrate from above. After an annealing process is applied to the substrate, a pair of ohmic electrodes 6 are formed on the N<+> active layer 5 by a lift-off method or the like. According to this constitution, the lowering of the voltage resistance of a drain can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device. More specifically, the present invention provides M
The present invention relates to a novel method for manufacturing an ESFET.

MESF is widely used in conventional technology, especially digital logic circuits, etc.
ET is required to operate at high speed and consume less power. Therefore, the active layer is generally designed to be thin in order to reduce the pinch-off voltage vP and operate with a small logic amplitude. However, when using a material such as a compound semiconductor such as GaAs, in which a surface depletion layer is generated due to surface states, the active layer is thin, so the surface depletion layer occupies a large proportion of the active layer, effectively forming a channel. is narrowed down. As a result, especially the source parasitic resistance Rs
becomes large and the mutual conductance g decreases.

Therefore, in order to reduce the parasitic resistance R3 of the MESFET as much as possible, various structures have been proposed in which the influence of the surface depletion layer is small. FIGS. 2(a) to 2(f) are diagrams showing MESFET manufacturing steps using a typical self-line process as a method for realizing such a structure.

First, as shown in FIG. 2(a), a resist layer 3 of a predetermined thickness is formed on a GaAs substrate 1 on which an active layer 2 is formed by ion implantation. Here, resist layer 3
is patterned so that its side end surface 3a corresponds to the position of a gate metal, which will be described later.

Subsequently, as shown in FIG. 2(b), a high melting point metal layer 4 such as WSL (tungsten silicide) is formed on the surface of the substrate 1 (on the active layer 2) and the surface of the resist layer 3 by sputtering. Deposit evenly.

Next, as shown in FIG. 2(C), the high melting point metal layer 4 is uniformly etched from above by a reactive ion etching method (hereinafter referred to as RIE method), and then a second etching process is performed.
As shown in Figure (d), the resist layer 3 is removed. In this way, a gate electrode 4a made of a high melting point metal is formed on the substrate.

Next, ions are implanted from above into the substrate on which the gate electrode 4a formed as described above is mounted, to form a conductive layer 5 in the substrate 1, as shown in FIG. 2(e). do. At this time, since the gate electrode 4a acts as a mask, the active layer 2 remains directly under the gate electrode 4a, and the conductive layer 5 remains in other regions adjacent to the gate electrode 4a.
is formed. Although not shown, the substrate 1 including the n' conductive layer 5 is usually subjected to an annealing treatment here.

Next, a lift-off method using a photoresist made of materials such as AuGe, Ni, and Au is used to form a photoresist as shown in Fig. 2 (f).
), l pairs of ohmic electrodes 6 are formed on the n+ active layer 5 and subjected to heat treatment for alloying.

In the MESFET manufactured by the self-line process as described above, the active layer 2 is formed only directly under the gate electrode 4a, so an increase in the parasitic resistance R8 due to the generation of a surface depletion layer is prevented.

Problems to be Solved by the Invention As described above, in the Selfaline process, the n layer is formed by performing ion implantation using the Schottky gate electrode of a high melting point metal as a mask, so the MESFET manufactured by this process has the following problems: The distance between the gate electrode and the n' conductive layer is very narrow. Therefore, the parasitic resistance due to the surface depletion layer of the active layer is significantly reduced.

On the other hand, however, the MESFET having such a configuration has a drawback that the drain breakdown voltage is low because the distance between the pair of n' conductive layers constituting the source electrode and the drain electrode is extremely narrow.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a new manufacturing method that can solve the problems of the prior art described above and manufacture a MESFET with high drain breakdown voltage while taking advantage of the advantages of the Selfaline process.

According to the present invention, a resist layer is formed on a compound semiconductor substrate having an active layer on the surface, a high melting point metal layer is deposited on the surface of the substrate and the resist layer, and then the high melting point metal layer is deposited on the surface of the substrate and resist layer. A compound semiconductor device comprising a step of forming a gate electrode by etching a melting point metal layer, and further forming an n''-conductive layer by performing ion implantation using the gate electrode as a mask after removing the resist layer. The manufacturing method includes the step of forming a side end face of the resist layer at an angle with respect to the substrate so that a vertical projection length of the gate electrode with respect to the substrate is longer than a gate length of the gate electrode. A method for manufacturing a compound semiconductor device is provided.

The main feature of the method for manufacturing a compound semiconductor device according to the present invention is that it includes the step of forming an overhang on the gate electrode by slanting the side edge of the resist layer for forming the gate electrode. .

That is, in the conventional Self-Line process, when the gate electrode formed on the substrate is used as a mask in the ion implantation process for forming the conductive layer, the gate electrode is upright, so the electrode of the gate electrode is For a long time, in FIG. 2, the width 〉 served as the mask width. For this reason, the distance between the pair of conductive layers formed on both sides of the electrode is very narrow, and the drain breakdown voltage of the MESFET ultimately obtained must be low.

On the other hand, in the manufacturing method according to the present invention, as will be specifically described later, the gate electrode is formed at an angle, so when the gate electrode is used as a mask during ion implantation, the actual gate The effective width as a mask is wider than the length (width). Therefore, the final completed ME
In SFET, the distance between a pair of conductive layers is widened,
The gate electrode will be offset on the active layer,
Drain breakdown voltage is improved. Note that if the slope of the gate electrode is known in advance, the amount of offset can be controlled by the amount of deposition when forming the gate electrode and the height of the electrode after etching.

In order to form the gate electrode at an angle, for example, when patterning a resist mask for forming the gate electrode, there is a method in which a resist layer loaded with a mask is exposed obliquely from above.

Hereinafter, the present invention will be described in more detail with reference to the drawings, but the following disclosure is only one embodiment of the present invention, and does not limit the technical scope of the present invention in any way.

Embodiment FIGS. 1(a) to 1(f) are diagrams showing each step of a method for manufacturing a compound semiconductor device according to the present invention.

First, as shown in FIG. 1(a), ion implantation (acceleration energy 30 keV, dose amount 2
A resist layer 3 of a predetermined thickness is formed on a GaAs substrate 1 on which an active layer 2 is formed using ion species 29Sl+). Here, the resist layer 3 has a side end surface 3b.
is patterned to correspond to the position of the gate metal described later, and is formed into a tapered shape so that the side end surface 3b has a predetermined angle with respect to the substrate l by oblique exposure during patterning. .

Subsequently, as shown in FIG. 1(b), the surface of the substrate l (on the active layer 2) and the surface of the resist layer 3 are coated with a sputtering method (RF power: 200 WSAr gas pressure: 4 mtorr).
) to uniformly deposit a refractory metal layer 4 of WSi with a thickness of 2000 nm.

Next, as shown in FIG. 1(C), the high melting point metal layer 4 is uniformly etched from above by RIE using CF as an etching gas, and then the resist layer 4 is etched as shown in FIG. 1(d). Remove layer 3. In this way, a gate electrode 4b made of a high melting point metal is formed on the substrate. here,
It should be noted that the gate electrode 4b formed on the substrate 1 is formed at an angle on the substrate 1.

Next, ions were implanted from above into the substrate on which the gate electrode 4b formed as described above was mounted (acceleration energy 50 keV, dose amount 2 x 1013 cm).

Ions 2aSi-) are applied to form an n conductive layer 5 in the substrate 1, as shown in FIG. 1(e). At this time, the gate electrode 1b acts as a mask, but since the gate electrode 4b is inclined, a region wider than the actual width of the gate electrode 4b is masked against ion implantation and remains as the active layer 2. Here, as seen in the figure, the gate electrode 4
b is mounted offset to the side of the wide active layer 2.

After annealing treatment (800°C, 10 minutes) in an arsine (ASH3) dehydrogen (H2) atmosphere to the substrate on which the n' conductive layer 5 was formed as described above, AuG
As shown in FIG. 1(f), by using a photoresist using materials such as e/Ni/Au or by a foot-off method,
n゛A pair of ohmic electrodes 6 are formed on the active layer 5,
ME after heat treatment for alloying (450℃, 1 minute)
SFET is completed.

In the MESFET manufactured by the above steps,
The width of the active layer 2 is longer than the gate electrode 4b, and the gate electrode 4a is mounted laterally offset within the active layer 2.

Therefore, while the increase in parasitic resistance Rs due to the generation of the surface depletion layer is minimized, the drain breakdown voltage is also improved.

As described in detail, according to the method of the present invention, a MESFET with extremely little influence of a surface depletion layer can be easily manufactured by a self-line process, while a gate electrode can be sloped. Accordingly, an appropriate offset can be formed in the active layer that is punished by the self-line, and an extreme decrease in drain breakdown voltage can also be prevented.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(f) are diagrams showing each step of the method for manufacturing a compound semiconductor device according to the present invention, and FIGS.
(f) is a diagram showing each step in a conventional method for manufacturing a compound semiconductor device. [Main reference numbers] 1...GaAs substrate, 2...Active layer, 3...Resist layer, 4...High melting point metal film, 4aS4b...Gate electrode, 5...n゛conductive layer, 6... ohmic electrode

Claims (1)

[Claims] A resist layer is formed on a compound semiconductor substrate having an active layer on the surface, a high melting point metal layer is deposited on the surfaces of the substrate and the resist layer, and then the high melting point metal layer is etched. A method for manufacturing a compound semiconductor device comprising forming a gate electrode, and further forming an n^+ conductive layer by performing ion implantation using the gate electrode as a mask after removing the resist layer. A compound semiconductor device comprising the step of forming side end faces of the resist layer at an angle with respect to the substrate so that the vertical projection length with respect to the substrate is longer than the gate length of the gate electrode. Production method.