JPH0324060B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor.

FIG. 1 shows an example of a conventionally used field effect transistor. In the figure, 1 is a substrate made of a high-resistance semiconductor, 2 is a primary ion implantation layer, and 3 is a substrate made of a high-resistance semiconductor.
Reference numeral 4 indicates a source electrode made of metal, 4 a gate electrode made of metal, and 5 a drain electrode also made of metal. That is, this is called a Schottky junction gate field effect transistor, and has a flat structure in which the gate channel region and the other active layers have the same impurity density distribution.

The field effect transistor having the above configuration has the advantage of low power consumption and has been widely used in the past, but the resistance of the active layer between the source electrode 3 and the gate electrode 4 (hereinafter referred to as source resistance) As a result, the desired high-frequency properties and high-speed performance are limited, and furthermore, there are problems such as the operation becomes unstable due to changes over time in the surface of the active layer between the source electrode 3 and the gate electrode 4. Ta.

In order to solve this problem, a structure and a manufacturing method as shown in FIG. 2 have been proposed. That is, a primary ion implantation layer 7 made of an N-type semiconductor is formed on the main surface of a substrate 6 made of, for example, high-resistance gallium arsenide by ion implantation of, for example, silicon (FIG. 2A). Next, a gate electrode 8 forming a shot junction is formed on the main surface,
By performing high-density ion implantation of, for example, silicon using this gate electrode 8 as a mask, a high-density ion implantation layer 9 is formed in the active layer other than the gate channel region consisting of the primary ion implantation layer 7 (FIG. 2). B). Next, by forming a source electrode 10 and a drain electrode 11 on the high-density ion implantation layer 9, a field effect transistor with low source resistance can be manufactured (FIG. 2C).

However, in such a manufacturing method, after forming the high-density ion-implanted layer 9, heat treatment is performed at a high temperature of around 800°C for the purpose of activating it. In order to prevent deterioration of the shot junction, the selection of the metal constituting the gate electrode 8 is severely restricted. Furthermore, due to the lateral spread of the high-density ion implantation, contact between the gate electrode 8 and the high-density ion-implanted layer 9 as a high carrier density active layer is unavoidable, and this causes leakage current of the shottock junction. High-speed
This causes deterioration of high-frequency characteristics, and is also a factor that limits shortening the gate length.

The present invention has been made in view of the above circumstances, and its purpose is to manufacture a field effect transistor in which the distance between the effective gate junction and the high-density injection layer can be freely controlled. The purpose is to provide a method.

In order to achieve such an objective, the present invention
After forming a high-density ion implantation layer using a resist mask having a multilayer structure, a lift/lift process using the resist mask is performed on the high-density ion implantation layer.
An insulating film is formed by turning it off, and a gate electrode is further formed between this insulating film. Hereinafter, the present invention will be explained in detail using Examples.

FIGS. 3A to 3E are cross-sectional views showing a field effect transistor at various steps during manufacturing according to an embodiment of the present invention. This example is an example in which a shotgun junction field effect transistor is formed on a high-resistance gallium arsenide substrate, and the steps will be explained step by step below.

First step: Add N-type impurities such as Si, Se, S,
A primary ion implantation layer 13 is formed by selective ion implantation of Te or the like (FIG. 3A). Second step A silicon nitride film 14 with a thickness of 0.05 to 0.2 μm is formed on the main surface by, for example, plasma CVD. deposit. Furthermore, a resist 15 and an insulating film 1 are formed on this so as to cross the primary ion implantation layer 13.
6. Form a three-layer resist having a three-layer structure of resist 17. In this case, as the intermediate layer insulating film 16, for example, a SiO ₂ film deposited to a thickness of 0.1 to 0.4 μm by magnetron sputtering method or ion beam deposition method can be used. In order to prevent the lowermost layer of resist 15 from being altered in the deposition process, a deposition method with a low deposition temperature must be used, or a resist with heat resistance higher than the deposition temperature must be used. Next, the uppermost layer resist 17 of the three-layer resist is patterned by a known method, and using this as a mask, the lower layer insulating film 16 is patterned, and the lowermost layer resist 15 is sequentially patterned using the insulating film 16 as a mask. The silicon nitride film 14 is processed using reactive ion etching or reactive ion beam etching having etching anisotropy.
selectively exposed. During this process, the uppermost layer of resist 17 may be completely removed.

Next, the above three-layer resist (if resist 17 is completely removed as described above,
In reality, high-density ion implantation is performed using the pattern (which is already a two-layer resist) as a mask, but
In this case, the next step depends on whether so-called side etching has occurred, in which the pattern of the bottom resist 15 of the three-layer resist is inside the pattern of the upper insulating film 16 used as a mask during patterning. is divided into the following two steps: the third one step and the third two steps. Note that whether or not the side etch is caused depends on the resist 15.
It can be freely controlled depending on the processing conditions.

When there is third one-step side etching In this case, the middle insulating film 16 of the three-layer resist is used as a mask to form an N-type impurity.
Selective ion implantation of Si, Se, S, Te, etc. is performed to form a high-density ion implantation layer 18 having an impurity density approximately 10 times that of the primary ion implantation layer 13 (third
Figure B). In this case, the high-density ion-implanted layer 18 actually spreads laterally beyond the area defined by the insulating film 16 used as a mask, but the positional relationship between this high-density ion-implanted layer 18 and the bottom layer resist 15 is teeth,
It can be freely controlled by controlling the amount of side etching of the resist 15. That is, if the side etching is small, the high-density ion implantation layer 18
contacts the resist 15, and by increasing the side etching and narrowing the width W of the resist 15, it is possible to provide an appropriate distance between the resist 15 and the high-density ion implantation layer 18. As will be described later, in a later step, the pattern of this resist 15 is reversed to form an insulating film, for example, the SiO ₂ film 19, and this is further reversed to form the gate electrode 22. Therefore, by controlling the amount of side etching of the resist 15, the high-density ion implantation layer 1
The positional relationship between SiO ₂ film 19 and gate electrode 22 can be freely controlled. Furthermore, in that case, the width W of the resist 15 determines the dimensions of the gate electrode 22, that is, the effective gate length.
Being able to narrow the width of the resist 15 also means that the effective gate length can be shortened.

When there is no third two-step side etching In this case, since the width dimensions of the intermediate layer insulating film 16 and the bottom layer resist 15 are almost the same, both are used as a mask and the N-type impurity, for example, Si, is A high-density ion implantation layer 18 having an impurity density approximately 10 times that of the primary ion implantation layer 13 is formed by selective ion implantation of Se, S, Te, etc. In this case, unlike the third step, not only the intermediate layer insulating film 16 but also the lowest layer resist 15 act as a mask for implantation, so the insulating film 16 is
It is possible to make the film thinner than when using one step. Next, using the insulating film 16 as a mask, only the resist 15 is laterally etched by plasma etching, reactive ion etching, or the like.
A desired amount of side etching is introduced into this resist 15 (FIG. 3B). In exactly the same way as explained in the third step, by controlling the side etching amount, the high density ion implantation layer 18 and the resist 1
5, and eventually the SiO ₂ film 19 and the gate electrode 22
You can freely control the positional relationship with the Furthermore, as described above, it is possible to shorten the effective gate length.

Fourth step: On the main surface of the substrate thus formed, an insulating film, e.g., an SiO ₂ film with a thickness of 0.1 to 0.4 μm, is formed using a low temperature process that does not cause alteration of the lowermost resist layer 15, such as a magnetron sputtering method. deposit.
Subsequently, the SiO ₂ film deposited on the three-layer resist is removed by lift-off together with the resist 15, insulating film 16, and resist 17 that constitute the three-layer resist, thereby removing the bottom resist of the three-layer resist. An SiO ₂ film 19 having a pattern that is an inversion of the pattern of 15 is formed on the silicon nitride film 14 (FIG. 3C). In this case, lift-off is easy because the resist has a multilayer (three-layer) structure. This lift-off formation allows
The SiO ₂ film 19 is formed almost directly above the high-density ion implantation layer 18, but the degree of overlap depends on the side etching of the resist 15 with respect to the lateral spread of the high-density ion implantation, as described above. Adjustment is possible by controlling the amount. Next, in order to activate the ion-implanted layer, heat treatment is performed at 800° C. for 20 minutes in a nitrogen atmosphere, for example.
The silicon nitride film 14 is provided as a protective film to prevent arsenic from evaporating from the ion-implanted layer at this time. Therefore, this silicon nitride film 14 is
The SiO ₂ film 19 may be deposited after patterning and the heat treatment described above may be performed, in which case the deposition of the silicon nitride film 14 in the above (second step) is not necessary. Alternatively, the silicon nitride film 14 as such a protective film may not be provided at all, and the heat treatment may be performed in an atmosphere containing arsenic.

Fifth step: On the main surface of the substrate on which the silicon nitride film 14 and the SiO ₂ film 19 are mounted, a resist pattern is formed in which holes are formed only in the portions corresponding to the source and drain electrodes, and using this as a mask, the SiO ₂
Of the film 19 and the underlying silicon nitride film 14, portions corresponding to the formation regions of the source and drain electrodes are removed by, for example, reactive ion etching and plasma etching. Next, using the above resist pattern, after depositing an ohmic metal such as AuGe/Ni, lift-off is performed, and the remaining portion is alloyed.
A source electrode 20 and a drain electrode 21 are formed (FIG. 3D).

Next, of the silicon nitride film 14, SiO ₂ film 1
9 is removed by, for example, plasma etching or reactive ion beam etching using the SiO ₂ film 19 as a mask, thereby exposing the surface of the primary ion implantation layer 13 formed on the substrate 12 made of gallium arsenide. Next, using a mask made of a resist pattern, a metal such as Al that forms a shot junction with gallium arsenide is vapor deposited on this region, and lift-off is performed to form the gate electrode 22.
By forming this, the desired field effect transistor can be obtained (FIG. 3E). In this case, since the etching rate of the silicon nitride film 14 by plasma etching or the like is sufficiently higher than the etching rate of the SiO ₂ film 19,
The surface of the substrate 12 can be exposed without substantially changing the shape of the SiO ₂ film 19.
Therefore, the gate electrode 22 can be formed to have substantially the same dimensions as the distance between the SiO ₂ films 19. Therefore, as described above, by controlling the amount of side etching of the resist 15 as the inverted pattern of the SiO ₂ film 19, the gate electrode 22 can be etched in the primary injection layer 1.
3, that is, the effective gate junction portion, and the high-density ion implantation layer 18 can be freely controlled, and the amount of side etching can be set to be larger than the lateral spread of the high-density ion implantation. If the gate electrode 22 is placed in the high density ion implanted layer 18
You can avoid contact with.

In addition, in the above embodiment, only the case where the gate electrode 22 is formed after forming the source electrode 20 and the drain electrode 21 was explained.
Conversely, it is also possible to form the gate electrode 22 first by using the following steps instead of the fifth step. That is, after removing the portion of the silicon nitride film 14 that is not covered with the SiO ₂ film 19 by, for example, plasma etching, for example,
Deposit Mo. Next, a resist pattern is formed with openings only in the portions corresponding to the source and drain electrodes, and this is used as a mask to
film and SiO ₂ film 19, followed by silicon nitride 14
is removed by, for example, reactive ion etching and plasma etching. At this time, an appropriate side etch is introduced into the remaining Mo film. Next, using the above resist pattern, an ohmic metal such as AuGe/Ni is deposited and lifted off to form a source electrode 20 and a drain electrode 21. Next, residual Mo
After removing the portion of the film other than the region corresponding to the gate electrode 22, by alloying the ohmic metal, a field effect transistor having the same purpose as shown in FIG. 3E can be obtained. can.

Further, in the embodiment described above, in the second step, the resist 15 as a multilayer resist and the insulating film 1 serving as a mask for processing the resist 15 are used.
6. Furthermore, a three-layer resist composed of the resist 17 which serves as a mask for processing this was formed, but this multi-layer resist may also have the above structure, for example, a metal film etc. in place of the insulating film 16. Even if a resist-resist two-layer structure, or a multilayer structure of four or more layers is used, the upper layer relative to the bottom layer can be used as a mask during high-density ion implantation. If it can be used, the same effects as described above can be obtained. However, if an insulating film or metal film is added,
It is possible to form a sharper pattern than when using only resist. Furthermore, when electron beam exposure is used, the addition of a metal film has the advantage that it is possible to avoid adverse effects caused by charging of the mask.

Further, all of the above explanations have been made by taking as an example the case where the present invention is applied to the manufacture of a Schottky junction gate type field effect transistor, but the present invention is not limited to this, and the present invention is not limited to this. It is also possible to apply the present invention to the production of type field effect transistors or insulated gate type field effect transistors. That is, for example, after lift-off forming the SiO ₂ film 19 in the fourth step described above,
For example, a step of ion-implanting Be as a P-type impurity is added, and in the fifth step, the P-type impurity formed above is added instead of the metal forming the shot junction.
By depositing a metal that makes ohmic contact with the type ion implantation layer, the desired PN junction gate type field effect transistor can be obtained. Further, for example, in the fifth step, the step of removing the silicon nitride film 14 in the portion between the SiO ₂ films may be omitted, or a step of depositing an insulating film on the surface of the substrate 12 in that portion may be added later. By this,
The desired insulated gate field effect transistor is obtained.

As explained above, according to the present invention, it is possible to form an effective gate junction between low-resistance high-density ion-implanted layers and by freely controlling the distance to the high-density ion-implanted layers. Since the gate junction part can be prevented from contacting the high-density ion-implanted layer, the source resistance is reduced, and the high-frequency and high-speed characteristics inherent to field effect transistors can be effectively exhibited, and the active layer surface It is possible to reduce operational instability caused by deterioration of the Additionally, by preventing the effective gate junction from contacting the high-density ion-implanted layer sandwiching it, additional gate-source and gate-drain capacitances can be reduced, and at the same time, shortening the gate length reduces the electric field. It is possible to reduce the so-called short channel effect in which the threshold voltage of the effect transistor changes. Furthermore, since high-temperature heat treatment is not included after depositing the gate electrode metal, the gate electrode metal can be freely selected depending on the purpose. In addition, by side etching the bottom layer of the multilayer resist, the length of the effective gate junction can be increased.
In other words, the ability to shorten the effective gate length is also useful for high frequency and
It has various excellent effects such as being an advantageous factor for high-speed characteristics.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an example of a conventional field effect transistor, FIGS. 2A to C are sectional views showing a field effect transistor at each step of manufacturing by a conventional manufacturing method, and FIGS. 3A to E are sectional views showing an example of a conventional field effect transistor. FIG. 3 is a cross-sectional view showing a field effect transistor at various steps during manufacturing according to an embodiment of the present invention. 12...Substrate, 13...Primary ion implantation layer, 1
4...Silicon nitride film, 15, 17...Resist, 16...Insulating film, 18...High density ion implantation layer, 19...SiO ₂ film, 20... Source electrode, 2
1...Drain electrode, 22... Gate electrode.

Claims (1)

[Claims] 1. A step of forming a semiconductor active layer in a partial region on the main surface of a high-resistance semiconductor substrate, and a step of forming a first photoresist film on the semiconductor active layer.
forming a first insulating film made of an inorganic material on the first photoresist film; forming a second photoresist film on the first insulating film; a step of opening the photoresist film into a predetermined pattern by photolithography, removing the first insulating film and the first photoresist film by etching through the opened predetermined pattern, and removing the second photoresist film by etching. resist film, first insulating film, first
a step of forming a multilayer resist mask including a photoresist film; a step of forming a high-density ion implantation layer by performing high-density ion implantation using the multilayer resist mask; and a semiconductor on which the multilayer resist mask is formed. A second insulating film made of an inorganic material is placed on the main surface of the first layer of the multilayer resist mask.
forming the second insulating film so that it is deposited up to the edge of the photoresist film, and then removing the second insulating film together with the multilayer resist mask, leaving only the part facing the high-density ion implantation layer; , a heat treatment step for activating the high-density ion implantation layer;
After removing a portion of the second insulating film corresponding to the source electrode and drain electrode formation region, forming a source electrode and a drain electrode in ohmic contact in the portion, and removing the portion of the second insulating film on the semiconductor active layer. 1. A method for manufacturing a field effect transistor, comprising the step of forming a gate electrode in a region between insulating films. 2. forming a semiconductor active layer in a partial region on the main surface of a high-resistance semiconductor substrate; forming a first photoresist film on the semiconductor active layer;
forming a first insulating film made of an inorganic material on the first photoresist film; forming a second photoresist film on the first insulating film; a step of opening the photoresist film into a predetermined pattern by photolithography, removing the first insulating film and the first photoresist film by etching through the opened predetermined pattern, and removing the second photoresist film by etching. resist film, first insulating film, first
a step of forming a multilayer resist mask including a photoresist film, and side etching the first photoresist film constituting the multilayer resist mask so that the sidewall of the first photoresist film is larger than the sidewall of the upper layer. forming a T-shape so as to have an inwardly recessed configuration; forming a high-density ion implantation layer by performing high-density ion implantation using the T-shaped multilayer resist mask; After forming an insulating film made of a second inorganic material on the main surface of the semiconductor on which the multilayer resist mask is mounted, so as to cover the end of the first photoresist film of the T-shaped multilayer resist mask,
a step of leaving only a portion of the second insulating film facing the high-density ion implantation layer and removing the rest along with the multilayer resist mask; a heat treatment step of activating the high-density ion implantation layer; a step of removing a portion of the insulating film corresponding to the source electrode and drain electrode formation region of step 2, and then forming a source electrode and a drain electrode in ohmic contact with the said portion; and a step of forming the insulating film on the semiconductor active layer. 1. A method for manufacturing a field effect transistor, comprising the step of forming a gate electrode in a region between. 3 forming a semiconductor active layer in a partial region on the main surface of a high-resistance semiconductor substrate; forming a first photoresist film on the semiconductor active layer;
forming a first insulating film made of an inorganic material on the first photoresist film; forming a second photoresist film on the first insulating film; a step of opening the photoresist film into a predetermined pattern by photolithography, removing the first insulating film and the first photoresist film by etching through the opened predetermined pattern, and removing the second photoresist film by etching. resist film, first insulating film, first
a step of forming a multilayer resist mask including a photoresist film; a step of performing high-density ion implantation using the multilayer resist mask to form a high-density ion implantation layer; and a step of forming the multilayer resist mask. forming a T-shaped multilayer resist mask in which the sidewalls of the first photoresist film are recessed inwardly from the sidewalls of the upper layer by subjecting the first photoresist film to a predetermined side etching; After forming an insulating film made of a second inorganic material on the surface so as to cover it up to the end of the first resist film of the T-shaped multilayer resist mask, the high-density ions of the second insulating film are formed. A step of leaving only a portion facing the implantation layer and removing the rest along with the T-shaped multilayer resist mask, a heat treatment step of activating the high-density ion implantation layer, and a step of removing the source electrode and the second insulating film. After removing a portion corresponding to the drain electrode formation region, forming a source electrode and a drain electrode that are in ohmic contact in the portion, and forming a gate electrode in a region between the insulating film on the semiconductor active layer. A method for manufacturing a field effect transistor, comprising the steps of: