JPS5935479A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5935479A JPS5935479A JP14737882A JP14737882A JPS5935479A JP S5935479 A JPS5935479 A JP S5935479A JP 14737882 A JP14737882 A JP 14737882A JP 14737882 A JP14737882 A JP 14737882A JP S5935479 A JPS5935479 A JP S5935479A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- layer
- mask
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 7
- 239000000243 solution Substances 0.000 description 7
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 6
- 229910007277 Si3 N4 Inorganic materials 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 235000011118 potassium hydroxide Nutrition 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
（ａｌ 発明の技術分野
本発明は半導体装置の製造方法に係り、特に、所望のゲ
ート耐圧を得ることの出来るセルフアライメント方式に
よる電界効果型半導体装置（ＦＥＴ）の製造方法に関す
る。Detailed Description of the Invention (al) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a field effect semiconductor device (FET) using a self-alignment method that can obtain a desired gate breakdown voltage. Regarding.
（ｂ） 従来技術と問題点
半導体装置の動作周波数或いは動作速度を高めるために
、半導体装置のパターンはますます微細化されている。(b) Prior Art and Problems In order to increase the operating frequency or operating speed of semiconductor devices, the patterns of semiconductor devices are becoming increasingly finer.
この微細パターンを形成する方法として、セルフアライ
メント（自己整合）方式が半導体装置の製造工程におい
て多く用いられている。As a method for forming this fine pattern, a self-alignment method is often used in the manufacturing process of semiconductor devices.
ＭＥＳ ＦＥＴ、或いはＭＩＳ ＦＥＴ等のゲート
電極をセルフアライメント方式により製作する場合、従
来は通常下記の製造工程に従っていた。When manufacturing gate electrodes of MES FETs, MIS FETs, etc. by a self-alignment method, the following manufacturing process has conventionally been followed.
即ち、ソース領域及びドレイン領域をイオン注入法によ
り形成する際に、ゲート部にイオンが注入されるのを阻
止するための金属膜と絶縁膜との二重層を設け、或いは
金属層のみを設け、これをマスフとしてイオン注入工程
を施し、ゲート電極。That is, when forming the source region and the drain region by ion implantation, a double layer of a metal film and an insulating film is provided to prevent ions from being implanted into the gate region, or only a metal layer is provided. This was used as a mask and an ion implantation process was performed to form the gate electrode.
ソース及びドレインのコンタクト領域を形成していた。Source and drain contact regions were formed.
上記製造方法によれば、ゲート電極とソース及びドレイ
ン領域との相互位置関係は完全に自己整合され、位置ず
れを生じることはない。しかしその反面、ショットキ金
属（ゲート電極）がソース及びドレインの高濃度領域と
接触或いは近接するため、ショットキ耐圧（ゲート耐圧
）を十分に高くすることが出来ない。According to the above manufacturing method, the mutual positional relationship between the gate electrode and the source and drain regions is completely self-aligned, and no positional deviation occurs. However, on the other hand, since the Schottky metal (gate electrode) is in contact with or close to the high concentration regions of the source and drain, the Schottky breakdown voltage (gate breakdown voltage) cannot be made sufficiently high.
（Ｃ） 発明の目的
本発明の目的は上記問題点を解消し、ゲート耐圧を十分
に高くすることが可能なセルファライン方式による電界
効果型半導体装置の製造方法を提供することにある。(C) Object of the Invention An object of the present invention is to provide a method for manufacturing a field effect semiconductor device using a self-line method, which solves the above problems and makes it possible to sufficiently increase the gate breakdown voltage.
（ｄ＋ 発明の構成
本発明の特徴は、半導体基板表面に第１の絶縁膜を形成
する工程と、該第１の絶縁膜上の所定の位置に前記第１
の絶縁膜とはエツチング材料の異なる第２の絶縁膜をオ
ーバーハング状に形成する工程と、該第２の絶縁膜をマ
スクとして前記半導体基板表面に所定の不純物を選択的
に導入する工程と、前記第１及び第２の絶縁膜のいずれ
ともエツチング材料の異なる第３の絶縁膜を前記第２の
絶縁膜の側壁部には被着せしめることなく前記第１の絶
縁膜の表面の露呈せる部分に被着せしめる工程と、前記
第２の絶縁膜を除去して前記第１の絶縁膜表面を露呈せ
しめる工程と、該開口内に首呈せる第１の絶縁膜を選択
的に除去する工程と、表出された半導体基板表面に所定
の導電材料を選択的に被着してゲート電極を形成する工
程とを含むことにある。(d+ Structure of the Invention The present invention is characterized by a step of forming a first insulating film on the surface of a semiconductor substrate, and a step of forming the first insulating film at a predetermined position on the first insulating film.
forming an overhanging second insulating film using a different etching material from the insulating film; selectively introducing predetermined impurities into the semiconductor substrate surface using the second insulating film as a mask; A portion of the surface of the first insulating film is exposed without depositing a third insulating film made of a different etching material from both the first and second insulating films on the side wall portion of the second insulating film. a step of removing the second insulating film to expose the surface of the first insulating film; and a step of selectively removing the first insulating film extending inside the opening. , and forming a gate electrode by selectively depositing a predetermined conductive material on the exposed surface of the semiconductor substrate.
Ｔｅｌ 発明の実施例
以下本発明の一実施例として、ＧａＡｓ ＭＥＳＦＥ
Ｔを製作する例を、第１図〜第９図を用いて製造工程の
順に説明する。Tel Embodiments of the Invention Below, as an embodiment of the present invention, GaAs MESFE
An example of manufacturing a T will be explained in the order of manufacturing steps using FIGS. 1 to 9.
〔第１図参照〕
半絶縁性のＧａＡｓ基板Ｉ上に、所定のパターンに従っ
てレジスト膜２を選択的に形成し、このレジスト膜２を
マスクとして、イオン注入法により例えばシリコン（Ｓ
ｉ）を、注入エネルギ凡そ１４５〔ｋｅＶ）Ｉ ドー
ズ量凡そ２．４Ｘ １０１２（１０１２（にて注入し、
イオン注入層３を形成する。[See Figure 1] A resist film 2 is selectively formed on a semi-insulating GaAs substrate I according to a predetermined pattern, and using this resist film 2 as a mask, silicon (S), for example, is implanted by ion implantation.
i) was implanted at an implantation energy of approximately 145 [keV] I and a dose of approximately 2.4X 1012 (1012),
An ion implantation layer 3 is formed.
〔第２図参照〕
上記マスクとして用いたレジスト膜２を除去した後、ス
バンタ法等により窒化アルミニウム（ＡＩＮ）膜４を凡
そ５０（ｎｍ）の厚さに形成し、その上に化学気相成長
法（ＣＶＤ法）等により二酸化シリコン（５ｉ０２ ）
膜５とその上に窒化シリコン（Ｓｉ３ Ｎ４ ）膜６を
、それぞれ凡そ３００（ｎｍ）の厚さに形成する。なお
上記ＡＩＮ膜４はＧａＡｓ基板１の表面を保護するため
のもので第１の絶縁膜、また５ｉ０２膜５及びＳ３３
Ｎ４膜６は１＆述する如くオーバーハング状の第２の絶
縁膜を形成するためのものである。[See Figure 2] After removing the resist film 2 used as the mask, an aluminum nitride (AIN) film 4 is formed to a thickness of approximately 50 (nm) by the Svanta method, and then chemical vapor deposition is performed on the aluminum nitride (AIN) film 4. silicon dioxide (5i02) by method (CVD method) etc.
A film 5 and a silicon nitride (Si3 N4) film 6 are formed thereon, each having a thickness of about 300 (nm). Note that the AIN film 4 is used to protect the surface of the GaAs substrate 1, and serves as a first insulating film, as well as the 5i02 film 5 and S33.
The N4 film 6 is for forming an overhang-shaped second insulating film as described in 1&.
〔第３図参照〕
次いでまず、例えば四弗化炭素（ＣＦａ ）と水素（Ｈ
２）との混合ガスを反応ガスとするドライエツチング法
により上記Ｓｉ３ Ｎ４膜６を選択的に除去して、所定
のパターンを有するＳｉ３ Ｎ４１９８を形成し、更に
これをマスクとしてその下層の５ｆ０２膜５を緩衝弗酸
（バッファＨＦ）溶液を用いて選択的に除去する。上記
緩衝弗酸溶液は等方性エツチング液であるため、残留せ
る５ｉ０２膜７はサイドエツチングされて、図示した如
く、上層の残留せるＳｉ３Ｎ４膜８より僅かに小さい横
方向寸法を有するパターンに形成される。[See Figure 3] Next, first, for example, carbon tetrafluoride (CFa) and hydrogen (H
The Si3 N4 film 6 is selectively removed by a dry etching method using a mixed gas with 2) as a reactive gas to form Si3 N4198 having a predetermined pattern, and using this as a mask, the underlying 5f02 film 5 is removed. is selectively removed using a buffered hydrofluoric acid (buffer HF) solution. Since the buffered hydrofluoric acid solution is an isotropic etching solution, the remaining 5i02 film 7 is side-etched and is formed into a pattern having a slightly smaller lateral dimension than the remaining Si3N4 film 8 of the upper layer, as shown in the figure. Ru.
上記５ｉ０２膜７は本実施例においてゲートパターンを
定めるものであり、Ｓｉ３ Ｎ ａ ｌｔ’ ８はソー
ス及びドレイン領域を定めるものである。このように材
質の異なる、従ってエツチング材料の異なる２つの絶縁
膜を用い、選択エツチングを行なってまず上層の絶縁膜
を所定のパターンに形成し、次いでこれをマスクとして
その下層の絶縁膜を等方性エツチング液により処理する
ことにより、自己整合法により両者の相互位置関係を決
定し、且つ下層のパターンを上層のパターンより僅かに
小さく形成し得る。そして後述する如く、このようにオ
ーバーハング状に形成した２層の絶縁膜よりなる第２の
絶縁膜を以後の工程のマスクとして、ソ−ス及びドレイ
ン領域、並びにゲート電極を自己整合させて形成する。The 5i02 film 7 defines the gate pattern in this embodiment, and the Si3N alt' 8 defines the source and drain regions. In this way, using two insulating films made of different materials, and thus different etching materials, selective etching is first performed to form the upper insulating film into a predetermined pattern, and then using this as a mask, the underlying insulating film is etched isotropically. By processing with a chemical etching solution, the mutual positional relationship between the two can be determined by a self-alignment method, and the pattern in the lower layer can be formed to be slightly smaller than the pattern in the upper layer. Then, as described later, the second insulating film made of the two-layer insulating film formed in an overhang shape is used as a mask for the subsequent process, and the source and drain regions and the gate electrode are formed by self-aligning. do.
〔第４図参照〕
次いで上記５ｉ０２膜７とその上のＳｉ３Ｎ４膜８より
なる第２の絶縁膜をマスクとしてイオン注入法により、
Ｓｔを注入エネルギ凡そ３５０ （ｋ ｅＶ） 。[See FIG. 4] Next, using the 5i02 film 7 and the second insulating film made of the Si3N4 film 8 thereon as a mask, ion implantation was performed.
St was implanted at an energy of approximately 350 (keV).
ドーズ量凡そ１×１０１４〔ｃｍ−２〕にて注入し、２
つの高濃度領域（ドレイン領域及びソース領域）９及び
１０を形成する。Injected at a dose of approximately 1 x 1014 [cm-2],
Two high concentration regions (drain region and source region) 9 and 10 are formed.
ここで形成された２つの高濃度領域９及び１０の間隔、
即ちイオン注入層３の長さは、マスクとして用いた第２
の絶縁膜の上層部９Ｓｉ３Ｎ４膜８の寸法と略等しい。The distance between the two high concentration regions 9 and 10 formed here,
That is, the length of the ion-implanted layer 3 is determined by the length of the second layer used as a mask.
The dimensions of the upper layer portion 9 of the insulating film 9 are approximately equal to the dimensions of the Si3N4 film 8.
次いで加熱処理を施して上記イオン注入層３及び高濃度
領域９．ＩＯに注入されたイオンを活性化する。Next, heat treatment is performed to form the ion-implanted layer 3 and the high concentration region 9. Activates the ions implanted into the IO.
〔第５図参照〕
次いでプラズマＣＶＤ法により、上記第２の絶縁膜（Ｓ
ｉ３ Ｎ４１＊８及び５ｉ０２模７ ）上を含むＧａＡ
ｓ基板上全面にＳｉ３ Ｎ４膜（第３の絶縁膜）１１を
被着せしめる。本工程において、第２の絶縁膜の上層の
５ｉ３Ｎ４Ｎ！ｌ！８のひさし部の下にも、新たに形成
されたＳｉ３Ｎ４膜１１は被着する。但しその厚さは図
示した如（５ｉ０２膜７ （第２の絶縁膜の基部）に近
づく程薄くなり、その形状はテーパ状となって隙間１２
が形成されるが、イオン注入層３と高濃度領域９及び１
０との境界の上部は、この５ｔ３Ｎ４膜１１により被覆
される。[See Figure 5] Next, the second insulating film (S
i3 N41*8 and 5i02 model 7) GaA including above
A Si3 N4 film (third insulating film) 11 is deposited on the entire surface of the s-substrate. In this step, the upper layer of the second insulating film is 5i3N4N! l! The newly formed Si3N4 film 11 is also deposited under the eaves 8. However, as shown in the figure, the thickness becomes thinner as it approaches the 5i02 film 7 (base of the second insulating film), and its shape becomes tapered to close the gap 12.
is formed, but the ion implantation layer 3 and high concentration regions 9 and 1
The upper part of the boundary with 0 is covered with this 5t3N4 film 11.
〔第６図参照〕
次いで上記ＳｉＯ３膜７を、Ｓｉ３Ｎ４膜１１は侵さな
いエツチング液２例えば緩衝弗酸溶液を用いてエツチン
グを行う。前述の如（５ｉ０２膜７の側壁部には隙間１
２が存在するので、５ｉ０２膜７は側壁部より緩衝弗酸
溶液により順次エツチングされる。[See FIG. 6] Next, the SiO3 film 7 is etched using an etching solution 2 that does not attack the Si3N4 film 11, such as a buffered hydrofluoric acid solution. As mentioned above (there is a gap 1 on the side wall of the 5i02 film 7).
2 is present, the 5i02 film 7 is sequentially etched from the side wall portion by the buffered hydrofluoric acid solution.
このように５ｉ０２膜７を選択的に除去することにより
、開口１３を形成する。このとき５ｉｏ２膜７上に被着
せるＳｉ３ Ｎ４膜８及びその上に被着せるプラズマ５
ｉ３Ｎａ ｍ１ｔｔも同時に除去される。By selectively removing the 5i02 film 7 in this manner, the opening 13 is formed. At this time, the Si3N4 film 8 to be deposited on the 5io2 film 7 and the plasma 5 to be deposited thereon.
i3Na m1tt is also removed at the same time.
本工程において形成された開口１３の寸法は、除去した
５ｉ０２膜８の寸法と略等しく、従ってイオン注入層３
と高濃度領域９及びＩＯとの境界部は露出しない。The dimensions of the opening 13 formed in this step are approximately equal to the dimensions of the removed 5i02 film 8, and therefore the ion-implanted layer 3
The boundary between the high concentration region 9 and IO is not exposed.
なお、前記第４図の説明中に述べた加熱処理工程は、上
記第５図の工程または第６図の工程のあとに施しても良
い。The heat treatment step described in the explanation of FIG. 4 may be performed after the step of FIG. 5 or the step of FIG. 6.
〔第７図参照〕
次いで上記開口１３部で表面を露出せるＡＩＮ膜６を、
苛性カリ （ＫＯＨ）のようなアルカリ溶液を用いて選
択的に除去し、イオン注入層３表面を露呈せしめる。[See FIG. 7] Next, the AIN film 6 whose surface is exposed at the opening 13 is
The surface of the ion-implanted layer 3 is exposed by selectively removing it using an alkaline solution such as caustic potash (KOH).
〔第８図参照〕
次いで蒸着法等により上記開口１３部にアルミニウム（
八１）を選択的に被着せしめ、露出せるイオン注入Ｎ３
表面とショットキ接触するゲート電極１４を形成する。[See Figure 8] Next, aluminum (
81) Ion implantation N3 to selectively deposit and expose
A gate electrode 14 is formed in Schottky contact with the surface.
このように上記ゲート電極１４を第２の絶縁膜の除去跡
に形成するので、ゲート電極１４はイオン注入層３と高
濃度領域９及び１０との境界部とは離隔し、しかもその
相互位置関係は自己整合して形成される。Since the gate electrode 14 is formed on the area where the second insulating film has been removed, the gate electrode 14 is separated from the boundary between the ion implantation layer 3 and the high concentration regions 9 and 10, and the mutual positional relationship between the gate electrode 14 and the ion implantation layer 3 is maintained. is formed in a self-aligned manner.
〔第９図参照〕
この後上記５ｔ３Ｎ４膜１１及びＡＩＮ膜３を選択的に
除去して高濃度領域９及び１０表面に開口を設け、次い
で金・ゲルマニウム／金（ＡｕＧｅ／ Ａｕ）を選択的
に被着せしめて、ドレイン電極１５及びシース電極１６
を形成し、本実施例によるＧａＡｓ ＭＥＳ ＦＥ
Ｔが完成する。[See Figure 9] After that, the 5t3N4 film 11 and the AIN film 3 are selectively removed to form openings on the surfaces of the high concentration regions 9 and 10, and then gold/germanium/gold (AuGe/Au) is selectively removed. The drain electrode 15 and the sheath electrode 16 are then deposited.
and GaAs MES FE according to this example.
T is completed.
このようにして本実施例により得られたショットキ・ゲ
ート型ＭＥＳ ＦＥＴは、ゲート電極１４が高濃度領
域であるドレイン領域及びソース領域と接触しないので
、従来のセルフアライメント方式により製作した場合の
ようなゲート耐圧の低下を招くことがなく、しかもゲー
ト電極、並びにドレイン領域９及びソース領域１０の各
部の位置を、総て自己整合して決定するセルフアライメ
ント方式の特徴をいささかも損なうことはない。In the Schottky gate type MES FET thus obtained in this example, since the gate electrode 14 does not come into contact with the drain region and source region, which are high concentration regions, the Schottky gate type MES FET obtained in this example does not come into contact with the drain region and the source region, which are highly doped regions. This does not cause a decrease in gate breakdown voltage, and does not impair the characteristics of the self-alignment method in which the positions of the gate electrode, drain region 9, and source region 10 are all determined by self-alignment.
なお本発明は上記一実施例に限定されることなく、種々
変形して実施し得る。Note that the present invention is not limited to the above-mentioned embodiment, and can be implemented with various modifications.
例えば、上記一実施例においてはオーバーハング状の絶
縁膜をエツチング材料の異なる２種類の絶縁膜を以て構
成し、このエソチン材料の異なることを利用して選択エ
ツチングを施すことにより下層の絶縁膜を上層より小さ
く形成した。For example, in the embodiment described above, the overhang-shaped insulating film is composed of two types of insulating films made of different etching materials, and by performing selective etching using the different etching materials, the lower insulating film is etched into the upper layer. Made smaller.
しかしこのオーバーハング状の絶縁膜は上記一実施例の
如く上層にひさしを形成した２Ｎ構造に変えて、第１０
図に示す如（上部を広く下部を狭くした逆台形状２０と
しても良い。この場合には１層構造とすることも可能で
ある。However, this overhang-shaped insulating film is changed to a 2N structure with an eaves formed on the upper layer as in the above-mentioned embodiment.
As shown in the figure, it may be an inverted trapezoidal shape 20 with a wide upper part and a narrow lower part. In this case, it is also possible to have a one-layer structure.
また半導体材料は、ＧａＡｓ等化合物半導体に限定され
る必要はなく、シリコン（Ｓｉ）であっても良い。Further, the semiconductor material is not limited to a compound semiconductor such as GaAs, and may be silicon (Si).
更に半導体基板表面を保護するための保護するための第
１の絶縁膜及びオーバーハング状の第２の絶縁膜の材質
も、前記一実施例に限定されるものではなく、要はそれ
ぞれエツチング材料が異なり、選択エツチング可能な材
料の組合せであれば良い。Furthermore, the materials of the first insulating film for protecting the surface of the semiconductor substrate and the overhanging second insulating film are not limited to the above-mentioned embodiment, and in short, the materials of each of the etching materials Any combination of materials that can be selectively etched may be used.
（［１発明の詳細
な説明した如く本発明により、電界効果型半導体装置の
ゲート耐圧を十分に高くすることの出来る、セルフアラ
イメント方式の半導体装置の製造方法が提供される。([1] Detailed Description of the Invention As described above, the present invention provides a self-alignment semiconductor device manufacturing method that can sufficiently increase the gate breakdown voltage of a field-effect semiconductor device.
第１図〜第９図は本発明の一実施例を製造工程の順に示
す要部断面図、第１０図は本発明の変形例を示す要部断
面図である。
図において、１は半導体基板、３はイオン注入層、４は
第１の絶縁膜、５は５ｉ０２膜、６はＳｉ３Ｎ４膜、７
及び８はオーバーハング状の第２の絶縁膜を構成する５
ｉ０２膜及びＳｉ３ Ｎ４膜、９及びｌＯは高濃度領域
でそれぞれドレイン領域及びソース領域、１１は第３の
絶縁膜、１２は隙間、１３は開口、１４はゲート電極、
１５及び１６はドレイン電極及びソース電極を示す。
、 Ｎ ０怯
味 法
Ｅ ｒ
ぐ の
法 味
区 ８ 〆ω
さ の味
法 法ヒ
Ｅ
の ０
味 涯1 to 9 are sectional views of essential parts showing an embodiment of the present invention in the order of manufacturing steps, and FIG. 10 is a sectional view of essential parts showing a modification of the invention. In the figure, 1 is a semiconductor substrate, 3 is an ion implantation layer, 4 is a first insulating film, 5 is a 5i02 film, 6 is a Si3N4 film, and 7
and 8 constitutes an overhang-shaped second insulating film 5
i02 film and Si3 N4 film, 9 and lO are high concentration regions, drain region and source region, respectively, 11 is a third insulating film, 12 is a gap, 13 is an opening, 14 is a gate electrode,
15 and 16 indicate a drain electrode and a source electrode. , N0 fear
Taste law E rgu no law Ajiku 8 〆ω
taste of sa
law law
E's 0 taste life
Claims (1)
１の絶縁膜上の所定の位置に前記第１の絶縁膜とはエツ
チング材料の異なる第２の絶縁膜をオーバーハング状に
形成する工程と、該第２の絶縁膜をマスクとして前記半
導体基板表面に所定の不純物を選択的に導入する工程と
、前記第１及び第２の絶縁膜のいずれともエツチング材
料の異なる第３の絶縁膜を前記第２の絶縁膜の側壁部に
ぼ被着せしめることなく前記第１の絶縁膜の表面の露呈
せる部分に被着せしめる工程と、前記第２の絶縁膜を除
去して前記第１の絶縁膜表面を露呈せしめる工程と、該
開口内に露呈せる第１の絶縁膜を選択的に除去する工程
と、表出された半導体基板表面に所定の導電材料を選択
的に被着してゲート電極を形成する工程とを含むことを
特徴とする半導体装置の製造方法。forming a first insulating film on the surface of the semiconductor substrate, and forming a second insulating film using a different etching material from the first insulating film at a predetermined position on the first insulating film in an overhang shape; a step of selectively introducing a predetermined impurity into the surface of the semiconductor substrate using the second insulating film as a mask; and a step of etching a third insulating film using a different etching material from both the first and second insulating films. a step of depositing a film on an exposed portion of the surface of the first insulating film without overly covering the side wall portion of the second insulating film; and removing the second insulating film to remove the first insulating film. a step of exposing the surface of the insulating film, a step of selectively removing the first insulating film exposed in the opening, and a step of selectively depositing a predetermined conductive material on the exposed surface of the semiconductor substrate. 1. A method for manufacturing a semiconductor device, comprising the step of forming a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14737882A JPS5935479A (en) | 1982-08-24 | 1982-08-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14737882A JPS5935479A (en) | 1982-08-24 | 1982-08-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5935479A true JPS5935479A (en) | 1984-02-27 |
Family
ID=15428882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14737882A Pending JPS5935479A (en) | 1982-08-24 | 1982-08-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5935479A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61176162A (en) * | 1985-01-31 | 1986-08-07 | Fujitsu Ltd | Field-effect semiconductor device and manufacture thereof |
| JPS62254470A (en) * | 1986-04-28 | 1987-11-06 | Seiko Instr & Electronics Ltd | Manufacture of junction type thin film transistor |
| JPS63263770A (en) * | 1987-04-20 | 1988-10-31 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Gaas mesfet and manufacture of the same |
| JPH01244666A (en) * | 1988-03-25 | 1989-09-29 | Nec Corp | Manufacture of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5860574A (en) * | 1981-10-06 | 1983-04-11 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field-effect transistor |
| JPS58130575A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Manufacture of field effect transistor |
-
1982
- 1982-08-24 JP JP14737882A patent/JPS5935479A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5860574A (en) * | 1981-10-06 | 1983-04-11 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field-effect transistor |
| JPS58130575A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Manufacture of field effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61176162A (en) * | 1985-01-31 | 1986-08-07 | Fujitsu Ltd | Field-effect semiconductor device and manufacture thereof |
| JPS62254470A (en) * | 1986-04-28 | 1987-11-06 | Seiko Instr & Electronics Ltd | Manufacture of junction type thin film transistor |
| JPS63263770A (en) * | 1987-04-20 | 1988-10-31 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Gaas mesfet and manufacture of the same |
| JPH01244666A (en) * | 1988-03-25 | 1989-09-29 | Nec Corp | Manufacture of semiconductor device |
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