JPS6323366A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain an FET having a short gate length and low gate resistance and source resistance by a method wherein the second insulating film, having L-shaped cross-section, is formed on the opposing side walls of the first insulating film and a semiconductor layer and the exposed surface of a semiconductor. CONSTITUTION:The semiconductor layer 15, consisting of an N-type semiconductor layer 16 and a high density N-type semiconductor layer 17, is formed on the high resistance semiconductor substrate 15 consisting of GaAs and the like. Then, the insulating film 21, consisting of two layers of a silicon nitride film 19 and a silicon oxide film 20, is formed on the whole surface of the semiconductor, and then an insulating film 21 having an aperture part is formed using a photoresist layer. Then, the high density N-type semiconductor layer 17 is removed using the insulating film 21 as a mask, and the N-type semiconductor layer 16 is etched until the threshold voltage of an FET reaches the prescribed value. Subsequently, an SiO2 film 22 is formed on the whole surface as the second insulating film, an Si3N4 film 23 is formed on the whole surface as the third insulating layer, the Si3N4 film 23 is etched by performing an RIE, and the SiO2 film 22 is etched using an Si3N4 film 24 as a mask. The SiO2 film 25 left on the part directly below the Si3N4 film 24 is formed into an L-shaped cross-section.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a field effect transistor,
Specifically, it relates to a method for manufacturing field effect transistors suitable for ultra-high frequency applications.

[Conventional technology]

In ultra-high frequency field effect transistors (hereinafter referred to as FETs), it is important to reduce the date length to submicron.
Fine exposure techniques such as F and B exposure are used. FIG. 4 shows an example of a conventional method for manufacturing this type of field effect transistor. In the manufacturing method shown in FIG. 4, an n-type semiconductor M, which becomes an active layer of FgT, is implanted into a high-resistance semiconductor substrate 1 made of CraAs, for example, by ion implantation.
A semiconductor layer 4 consisting of a high concentration n-type semiconductor layer 3 for reducing parasitic resistance is formed (FIG. 4(a)). Next, a source electrode 5 and a drain electrode 6 are formed by a known method (FIG. 4fb)), and a striped photoresist pattern 8 having an opening 7 of α5 μm or less is formed using an exposure technique such as 18g light. , using this photoresist batten 8 as a mask, the high concentration n-type semiconducting layer 3 and the n-type semiconductor layer 2 are formed.
is removed by an etching method with isodirectional etching characteristics to provide an appropriate active layer thickness 9 and side etching 10, and then a gate metal 11 is deposited (see FIG. 4(6)).
Then, the resist is removed using a solvent to form the gate electrode 13 (FIG. 4(d)).

The conventional manufacturing methods described above have various drawbacks.

First, the shortening of the gate length depends on the progress of exposure technology such as EBJI light, and it is currently difficult to realize a gate length of α3 μm or less with a good yield. Next, gate resistance, which has the same effect as gate length on high-frequency characteristics, increases as the product of gate length (Figure 4 (d)) and gate electrode thickness (Figure 4 (d)) increases. This improves high frequency characteristics. But the fourth
As shown in Figure (e), lateral growth 12 of the gate metal 11 occurs during gate metal deposition, and this lateral growth closes the opening 7. Therefore, the thickness hg of the gate electrode is determined by the amount of evaporation that closes the opening 7, and the cross-sectional shape is triangular as shown in FIG. 4(c). Therefore, as the gate length tg is shortened, the thickness hg becomes smaller, and the gate becomes triangular in shape, which has the disadvantage that the gate resistance becomes extremely large with a short gate length.

Furthermore, in order to improve high frequency characteristics, it is important to reduce the source resistance by shortening the source-gate electrode spacing of 1.14 mm (Figure 4 (d)), but controlling this spacing depends on the alignment accuracy of the exposure technology. It has the disadvantage that it is difficult to shorten the length to 0.5 μm or less at °C.

[Purpose of the invention]

The purpose of the present invention is to solve the drawbacks of the conventional FEET manufacturing method as described above, and to reduce the gate resistance by making the gate length small and making the cross-sectional shape of the gate T-shaped, regardless of the gate length. In addition, the distance between the source and gate electrodes is reduced to reduce source resistance, and the drain breakdown voltage is increased to achieve high frequency characteristics.

An object of the present invention is to provide a method for manufacturing an F'ET with improved high output characteristics.

[Structure of the invention]

The present invention provides a second insulating film having an L-shaped cross section formed on opposing side walls of the first insulating film and the semiconductor layer and a part of the exposed surface of the semiconductor.
), it is possible to shorten the gate length, control the distance between the source and gate electrodes, the distance between the high-concentration semiconductor layer on the source side and the gate electrode, and make the cross-sectional shape of the gate electrode T-shaped. Drain 1! The most important feature is that the highly doped semiconductor layer between the electrode and the gate electrode can be selectively removed.

Conventional technology allows shortening of gate length and fine control of source-gate electrode spacing, high-concentration n-type semiconductor layer on the source side, and gate electrode without relying on exposure technology. [Embodiment] Fig. 1 shows a first embodiment of the method for manufacturing an FET according to the present invention, in which a resistive semiconductor such as GaAs is used. Substrate 15
FETs are formed on the top using, for example, ion implantation or vapor phase growth.
For example, a carrier concentration of 10 to 10 cm, which becomes the active layer of
N-type semiconductor TA16 with a thickness of about CLl ~ CL311m
In order to reduce the source resistance of the FET, a semiconductor layer 18 consisting of a highly doped n-type semiconductor layer 17 with a carrier concentration of 10 crs or more and a thickness of approximately α1 to Q2 μm is formed (see FIG. 1 (resistance)). For example, as a first insulating film on the entire surface of the
An insulating film 21 consisting of two layers: a silicon nitride film 19 (hereinafter abbreviated as Si, N, film) of ~0.8 μm and a silicon oxide film 20 (hereinafter abbreviated as slQ, film) with a thickness α1~Q of 2 μm. , then apply 7 otresist layers to the entire surface,
A well-known method is used to form a perforated batten, and using this photoresist layer as a mask, the SiO2 film 20 r 5 is removed.
After etching the f3N4 film 19 by reactive ion etching (hereinafter abbreviated as RIE) using a fluorocarbon gas such as CF4, the photoresist is removed to form an insulating film 21 having openings (FIG. 1(b)). ). Next, using this insulating film 21 as a mask, the exposed semiconductor layer is etched using an anisotropic etching method such as reactive ion beam etching (hereinafter referred to as RI) using a chlorine-based gas such as BCLa.
(abbreviated as BE) to remove the high concentration n-type semiconductor layer 17,
Furthermore, the n-type conductor layer 16 is made to have a thickness (α05 to Q, 15 μ
(Fig. 1(C)).

Next, as a second insulating film, S10! is formed by, for example, a plasma CVD method. The film 22 is formed over the entire surface to a thickness of, for example, α1 to α5 μm (FIG. 1(d)), and a third layer, Th.
For example, as an i-film, Si made by the plus V CVD method,
A N4 film 25 is formed on the entire surface to a thickness of, for example, α1 to α5 μm (FIG. 1(e)), and then this 5ijN4 film 23 is etched by RIE using an etching method having anisotropic etching characteristics, such as CF. do. At this time, Si and N attached to the side wall, and 5ixN+ attached to this side wall because the thickness of the film in the depth direction is thicker than other parts.
Only M24 remains (Fig. 1(f)). Next, etching methods with anisotropic etching characteristics, such as CF4 and H!
The St 2 O film 22 is etched using a mixed gas of RIgK, St, N, and the film 24 as a mask. At this time, 810! attached to the side walls of the semiconductor layer 18 and the insulating film 21!
Since the thickness of the film in the depth direction is thicker than other parts, the 311N4 film 24 is selectively etched by plasma etching using, for example, CF, using a mask for etching the sio film attached to this side wall. It is etched and removed (Fig. 1(h)). At this time, the remaining 5 lots of film 25 have an L-shaped cross section, and the length is 2. is α1~05μm1
The height is α7 to 1.6 μm. Next, a single layer or a multilayer film is formed with a metal that makes Schottky contact with the n-type semiconductor layer 16 as the bottom layer, for example, the metal that makes Schottky contact is aluminum, a C1 aluminum layer, or a double layer of aluminum and nickel, or a layer of aluminum and nickel. The film 26, such as a double layer of aluminum, sin, or the like, is formed to have a sufficient thickness α5 to the extent that the groove 27 is flattened by, for example, sputtering.
The film 26 is then etched to a thickness of about 1.5 .mu.m (FIG. 111), and then the film 26 is etched by an etching method having anisotropic etching characteristics, such as ion milling using Ar ions. At this time, since the thickness of the groove 27 and the deposited film in the depth direction is 10°C thicker than other parts, only this part remains, and the gate electrode 28 is formed (Fig. 1 (j)). The insulating film 21 is removed using, for example, RIE using CF and plasma etching to expose the high concentration n-type semiconductor layer 17 (see FIG. 1(k)).
)). Next, a metal that makes ohmic contact with this high concentration n-type semiconductor layer 17, such as a double layer of gold germanium alloy and nickel, or a gold germanium alloy, nickel, butane, etc.
The metal film 29, such as four layers of gold, has a thickness of 0.1 to α3μ, for example.
It is attached by vacuum evaporation method etc. (Fig. 1(
4). Next, a photoresist layer 30 is applied to a thickness of, for example, about 1.0 to 5.0 ljm so that the surface thereof is flattened, and dried by heating (FIG. 1&n)). Next, this photoresist layer 30 is etched using an etching method having anisotropic etching characteristics, for example, 0! The metal film 31 deposited on the 81 ox film 25 and the gate electrode 28 is exposed by RIE using etching (FIG. 1(n)). Next, this metal film 31 is removed by, for example, ion milling using Ar ions, and the remaining photoresist a is removed.
60 is removed using a solvent or the like, and the source electrode 62. A drain electrode 36 is formed (FIG. 1(p)).

In the FETIA manufacturing method of the first embodiment described above, as shown in FIG. 1(p), the gate length tg is C, Sin, twice the length tl of the film 25, with respect to the dimension determined by the exposure technology. Therefore, an extremely short gate length can be obtained without using exposure technology. For example, if t is about 1.0 .mu.m, which can be fully realized by ordinary exposure technology, then t3 in the above embodiment is from 111 .mu.m or less to about 0.08 .mu.m.

The cross-sectional shape of the gate electrode 30 is T-shaped with thicker X as shown in FIG. 1(p), and the length of the upper part of the gate electrode is tm.
can be made large regardless of the gate length tg, and the gate resistance can be reduced regardless of the gate length. As an example of the dimensions, when L is about 1.0 μm, the maximum value α can be about 9 μm. Furthermore, the distance between the source and gate electrodes and the distance between the high concentration n-type semiconductor layer on the source electrode side and the gate electrode are 810 as shown in FIG.
Therefore, the source resistance can be lowered because it can be made shorter regardless of the exposure technology.

FIG. 2 shows a second embodiment of the method for manufacturing FEINT according to the present invention, and the numbers in the figure are the same as the corresponding numbers in FIG. The steps are also the same as in the second embodiment up to FIG. 1 (ml-(k)), and only the subsequent steps are shown for simplicity.
kl is the same as kl in FIG. 1(j), and after forming the gate electrode 28 (FIG. 2(j)),
1 is removed to expose the highly doped n-type semiconductor layer 17 (FIG. 2(k)). Next, a metal film 29 making ohmic contact with this high concentration n-type semiconductor layer 17 is formed using a film forming technique with directionality, such as a vacuum evaporation method, to form an arrow 34 which is inclined by 30° to 80" with respect to the vertical direction. For example, the metal film is deposited by α1 to α3 μm in an arrangement where the deposition material reaches from the direction.At this time, the metal film does not adhere to the region 35 that is in the shadow of the film 25, and the length t! of this region is α1 to α3 μm. It is about 0 μm (Figure 2 (4). Next, Figure 1-9 (n), (
Source electrode 32.p) in the same manner as in p). A drain electrode 36 is formed (Fig. 2-, (n), (pi)). Next, a source electrode 32, a drain electrode 33, a gate electrode 30,
8in! RIB using an etching method having anisotropic etching characteristics, such as BCl, using the film 25 as a mask.
The exposed portion 35 of the semiconductor layer 18 is etched using E until at least the high concentration n-type semiconductor layer 17 is removed to form a recess 11936 on the drain side (FIG. 2(q)).
).

FzT! of the second embodiment explained above! ! In the manufacturing method, as shown in FIG. 2(q), compared to the first embodiment, the distance between the drain and gate electrodes and the distance between the high concentration n-type semiconductor layer on the drain side and the gate electrode were changed by changing the distance between the source and gate electrodes. and the distance t between the high concentration n-type semiconductor layer on the source side and the gate electrode,
For 1. Increase by 2゜+1. The difference is that it is possible to Thereby, the drain breakdown voltage of the FgT can be increased, and the output can be increased. Furthermore, it is possible to reduce the capacitance between the gate electrode and the drain electrode.

Further, FIG. 3 shows a third embodiment of the FET manufacturing method according to the present invention. The process is shown in the first embodiment and in Figures 1 (&) to (k
) are the same, and the steps after (j) are shown here for simplicity. Therefore, FIG. 3(j) and (k) are the same as FIG. 1(j) and (k), and after forming the gate 'c4 pole 28 (FIG. 3(j)), the insulating film 21 is removed. , exposing the highly doped n-type semiconductor layer 17 (FIG. 3(k)).

Next, a metal film 29 is formed in the same manner as in FIG. 2 (4) of the second embodiment (FIG. 3(a)). The metal film 29 is not attached to 35. Next, using this metal film 29 as a mask, an etching method having anisotropic etching characteristics, such as BOt,
Semiconductor layer 1 of exposed portion 55 of RIBE IC processing using
8 is etched until at least the high concentration n-type semiconductor layer 17 is removed to form a trench 36 on the drain side (FIG. 3(b)). Next, Figure 1 (ml, (n).

Similarly to (p), the source electrode 32. drain electrode 36
(Fig. 3 tn), fp), (q)
).

The third embodiment explained above is the dug groove 6 on the drain side.
Immediately after forming the metal film 29, the step of forming FgT 6 is carried out immediately after the formation of the metal film 29.Although the point Yx is different from that of the second embodiment, the cross-sectional structure of the completed FgT (FIG. 3(q)) is the same as that of the second embodiment (FIG. 3(q)). Figure 2 (q))
and has the same effect as the second embodiment.

〔Effect of the invention〕

As explained above, according to the method of manufacturing an FBT according to the present invention, it is possible to realize an FET with a short gate length and low gate resistance and source resistance, thereby improving the high frequency characteristics of the FET. Furthermore, a manufacturing method in which a trench is provided on the drain side can improve the high output characteristics of FgT.

[Brief explanation of the drawing]

FIG. 1(&) to tp) show the manufacturing process of the first embodiment of the present invention. Fig. 2 (jl to fq+ show manufacturing steps of the second embodiment of the present invention. The same steps as those of the first embodiment are omitted. Fig. 5 (j) to (q) 1 shows the manufacturing process of the third embodiment of the present invention.The same steps as in the first embodiment are 1...
- High resistance semiconductor substrate, 2... N-type semiconductor device 3... High concentration n-type semiconductor layer 4... Semiconductor layer 5... Source electrode 6... Drain electrode 7... Opening part 8 ...7 Otoresist button 9...Appropriate active layer thickness 10...Side etching 11...Gate metal 12...Lateral growth 13...Gate electrode 14...Source/gate electrode Spacing 15... High resistance semiconductor substrate 16... N-type semiconductor layer 17... High-magneticity n-type semiconductor layer 18... Semiconductor layer 19... Si, N4 film 20... StO film 21 ... Insulating film 22 ... S10 film 23 ... 3i3N4 film 24 ... 5tlN4 film on side wall 25 ... Stow film 26 ... film 27 ... groove 28 ... gate electrode 29 ... ...Metal film 30...Photoresist 31...Metal film 32...Source electrode 33...Drain electrode 64...Arrow 35...Exposed portion

Claims (3)

[Claims] (1) A step of forming a semiconductor layer on the main surface of a high-resistance semiconductor substrate, consisting of at least two layers, including a semiconductor layer with a high carrier concentration as the top layer and the next layer as a semiconductor active layer, and this semiconductor layer. forming a first insulating film having an opening in the semiconductor active layer; using this insulating film as a mask, etching the semiconductor layer in the opening, removing at least the high carrier concentration semiconductor layer; forming a second insulating film on the entire surface including opposing sidewalls of the first insulating film and the semiconductor layer; and forming a third insulating film on the opposing side of the second insulating film. a step of forming a film; and a step of removing the second insulating film in other parts, leaving the second insulating film in the part sandwiched between the third insulating film, the first insulating film, and the semiconductor layer. , removing the third insulating film, forming a metal that makes Schottky contact with the semiconductor active layer on the exposed surface of the semiconductor active layer and the surface of the second insulating film on the semiconductor active layer, and forming a gate electrode. a step of forming;
a step of removing the first insulating film to expose the high carrier concentration semiconductor layer; a step of depositing a metal on the entire surface that makes ohmic contact with the high carrier concentration semiconductor layer; A method for manufacturing a field effect transistor, comprising the step of removing metal attached to the top of the second insulating film and gate electrode to form a source electrode and a drain electrode. (2) A step of forming a semiconductor layer on the main surface of a high-resistance semiconductor substrate, consisting of at least two layers, with a semiconductor layer with a high carrier concentration as the top layer and the next layer as a semiconductor active layer, and this semiconductor layer. forming a first insulating film having an opening in the semiconductor active layer; using this insulating film as a mask, etching the semiconductor layer in the opening, removing at least the high carrier concentration semiconductor layer; forming a second insulating film on the entire surface including opposing sidewalls of the first insulating film and the semiconductor layer; and forming a third insulating film on the opposing side of the second insulating film. a step of forming a film; and a step of removing the second insulating film in other parts, leaving the second insulating film in the part sandwiched between the third insulating film, the first insulating film, and the semiconductor layer. , removing the third insulating film, forming a metal that makes Schottky contact with the semiconductor active layer on the exposed surface of the semiconductor active layer and the surface of the second insulating film on the semiconductor active layer, and forming a gate electrode. a step of forming;
The step of removing the first insulating film to expose the high carrier concentration semiconductor layer, and the step of forming a metal that makes ohmic contact with the high carrier concentration semiconductor layer using a directional film forming method such as a vacuum evaporation method, a step of attaching metal from a direction in which one of the surfaces of the high carrier concentration semiconductor layer along the second insulating film is shaded, and forming an ohmic contact on the entire surface other than the shaded area; A step of removing metal attached to the upper part of the second insulating film and the gate electrode to form a source electrode and a drain electrode, and using the second insulating film, the gate electrode, the source electrode, and the drain electrode as a mask, A method for manufacturing a field effect transistor, including a step of etching the exposed semiconductor layer in the shadow region and removing at least the high carrier concentration semiconductor layer. (3) Forming a semiconductor layer on the main surface of a high-resistance semiconductor substrate, consisting of at least two or more layers, with a semiconductor layer with a high carrier concentration as the top layer and the next layer as a semiconductor active layer, and this semiconductor layer forming a first insulating film having an opening in the semiconductor active layer; using this insulating film as a mask, etching the semiconductor layer in the opening, removing at least the high carrier concentration semiconductor layer; forming a second insulating film on the entire surface including opposing sidewalls of the first insulating film and the semiconductor layer; and forming a third insulating film on the opposing side of the second insulating film. a step of forming a film; and a step of removing the second insulating film in other parts, leaving the second insulating film in the part sandwiched between the third insulating film, the first insulating film, and the semiconductor layer. , removing the third insulating film, forming a metal that makes Schottky contact with the semiconductor active layer on the exposed surface of the semiconductor active layer and the surface of the second insulating film on the semiconductor active layer, and forming a gate electrode. a step of forming;
The step of removing the first insulating film to expose the high carrier concentration semiconductor layer, and the step of forming a metal that makes ohmic contact with the high carrier concentration semiconductor layer using a directional film forming method such as a vacuum evaporation method, a step of forming a metal that is deposited from a direction in which one of the surfaces of the high carrier concentration semiconductor layer along the second insulating film is in the shadow, and making ohmic contact with the entire surface other than the region in the shadow; and masking this metal. etching the exposed semiconductor layer in the shaded region, etching at least the high carrier concentration semiconductor layer; Remove the source electrode,
A method for manufacturing a field effect transistor including a step of forming a drain electrode.