JPS63137481A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the projection of a gate electrode sufficiently by forming a gate opening section at two stages, minimizing parasitic capacitance while applying a fluid substance by using an upper opening and dry-etching a substrate from the vertical direction. CONSTITUTION:Si<+> ions are implanted selectively into a semi-insulating GaAs substrate 11 to shape a semiconductor active layer 12, and an Si3N4 film 13 in thickness of 2000Angstrom and an SiO2 film 14 in thickness of 3000Angstrom are applied onto the surface of the active layer 12 in succession. A photo-resist pattern 15 is formed into a region in which a gate electrode must be shaped, and the film 14 and the film 13 are etched successively to form an opening 52. A photo- resist is removed, and a gate metal 53 consisting of Ti-Pt-Au is evaporated. A photo-resist 16 is applied onto the whole surface, and the resist 16 and the gate metal 53 on the film 14 are removed from the direction vertical to a wafer to form a T-shaped gate 55. Source and drain electrodes 31, 32 are shaped. Accordingly, parasitic capacitance can be reduced while the upper projection of the gate 55 can be scaled down.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having fine electrodes.

[Conventional technology]

In order to improve the performance of semiconductor devices (higher frequency, higher speed), it is essential to miniaturize the electrodes provided in this semiconductor device. This miniaturization of the electrode can shorten the time required for electrons to travel through the semiconductor layer under the electrode, making it possible to improve the so-called current cutoff frequency f〒. This can be explained using GaAs on a semi-insulating gallium arsenide (GaAs) substrate.
A GaAs barrier gate field effect transistor (GaAs MESFE) uses a semiconductor layer as an active layer.
T).

FIG. 3 is a schematic cross-sectional view of the structure of a conventional GaAs MESFET, which is a device in which the current flowing between the source 31 and fillet 320 electrodes is modulated by the voltage applied to the gate electrode 33 to provide an amplification effect. .

To improve the performance of GaAs MESFETs, it is necessary to shorten the gate length (Lc), and recently GaAs MESFETs with quarter micron (α25 μm) gates have been
ESF'ET has also been developed. One problem associated with such short gate lengths is an increase in gate resistance (RG).

As a method of shortening this gate electrode and reducing gate resistance, a T-type gate electrode as shown in FIG.
is proposed.

FIG. 5(8) is a sectional view schematically illustrating an example of a method for forming a conventional T-shaped gate. First, in the case shown in Figure 5, 1) ni
A GaAs semiconductor active layer is formed, and this n-type GaA
8i0.s semi-coated layer 12 with a thickness of 0.5 μm. membrane 51
An opening (length α25 μm) 52 in which a gate electrode is to be formed is formed in a predetermined region on this Sin film 51 by selective dry etching using ordinary photolithography technology. Next, as shown in Fig. 5, for example, Ti(500A)-Pt(100O
A) A gate metal 53 consisting of a stack of Au (4000A) is deposited by vacuum evaporation, followed by forming a predetermined photoresist pattern 54 as shown in FIG. 5(q), and masking this photoresist pattern 54. By removing unnecessary gate metal as shown in FIG. 5, a T-type gate 55 as shown in FIG.
The GaAs MESFET shown in FIG. 4 is obtained.

[Problem that the invention seeks to solve]

As described above, the conventional T-type gate formation method has the following two major drawbacks. First, as shown in FIG. 5 (CI), when the photoresist pattern 54 for forming the T-type gate is formed in multiple layers for alignment, its length is extremely large considering the alignment margin. The parasitic capacitance between the overhang and the semiconductor layer increases.The second drawback is that when the 8i01 film 51 is made thicker to reduce this parasitic capacitance, the aspect ratio of the opening (opening depth/opening length) increases. ) is large, making it difficult to completely fill the opening with gate metal.

An object of the present invention is to solve these problems and provide a method for manufacturing a semiconductor device that can reduce parasitic capacitance and obtain a high-performance semiconductor device with a small opening aspect ratio. .

[Means for solving problems]

The structure of the method for manufacturing a semiconductor device of the present invention includes the steps of providing a semiconductor active layer on a semiconductor substrate and stacking first and second dielectric films on the semiconductor active layer; forming a predetermined photoresist pattern on the photoresist pattern, etching the second dielectric film by isotropic etching using the photoresist pattern as a mask to expose the surface of the first dielectric film, and further using the photoresist pattern as a mask. etching the first dielectric film by anisotropic etching to expose the surface of the semiconductor substrate and forming an opening; and after removing the photoresist pattern, depositing an electrode metal on the entire surface thereof. A flowable substance is applied to the entire surface on which the electrode metal is provided, and the entire surface is dry-etched in a direction perpendicular to the semiconductor substrate to expose a different surface of the second dielectric film and to apply a fluid material only to the opening. The method of manufacturing a semiconductor device is characterized by including the step of leaving the electrode metal.

〔Example〕

It is a preliminary sectional view. First, in FIG. 1 (5), the semiconductor active layer 12 is formed by selectively implanting 1c, 8i+ ions (50 kev, lXl0LS ions y /cl) into the semi-insulating GaAs substrate 11, and the semiconductor active layer 12 is formed on the surface thereof. Thickness 2000A O8i3N, film 13, further thickness 300A
o;, -8i0. Films 14 are deposited in sequence. Next, as shown in FIG. 1(B), a photoresist pattern 15 is provided in a region where a gate electrode is to be formed. In this case, the length of the opening is 0.25 μm. Next, Figure 1 (
The 5i02 film 14 is etched by isotropic etching, for example, etching using HF, as described above, and the 5isN+ film 13 is layered. The etching at this time does not necessarily have to be just etching, and slight over-etching and etching are allowed. Next, the lower layer 5isN
Then, the film 13 is etched using CF4 gas or active ion etching to form an opening 52.

Next, the photoresist is removed and a gate metal 53 of Ti-Pt-Au similar to the prior art is deposited on the entire surface (
Figure 1 (Q). The important point here is that the opening 52 for the gate electrode is in two stages, and the total dielectric film thickness is 500 OA.
The point is that the aspect ratio of the bottom of the opening is reduced while maintaining the same value.

Next, a photoresist 16 is applied to the entire surface using a spade in FIG. T as shown in
A fi gate 55 is obtained. Here, the size of the upper protruding portion of the T-shaped gate electrode can be made sufficiently small as long as it corresponds to the opening area of approximately 85N. Next, if the source and drain %L poles 31 and 32 are formed using the usual method, a GaAsME8PE'l as shown in FIG.
We can obtain r.

FIG. 2 is a sectional view of the manufacturing process of the second embodiment of the present invention. First, in FIG. 2 (5), the process up to the step of providing an opening for the gate electrode is the same as the embodiment shown in FIG. A
21, and then, as shown in Figure 2 (CJ), the bottom Si,
The WSi film was left only in the opening, and as shown in Figure 2q, 'l' 1 (500^) - u (5000
A) Sequentially evaporate 22, eclipse etch Bayl, method Kl),
The Ti-Au film is left in the 5i01 opening. According to this method, the upper part of the W8i metal with high reliability can be
It is possible to realize a highly reliable GaAs MESFET with a structure in which i-Au is placed like a hat.

〔Effect of the invention〕

As explained above, in the method for manufacturing a semiconductor device according to the present invention, the gate opening is formed in two stages, the aspect ratio of the bottom opening is kept small, and the thickness of the entire dielectric film is increased, thereby reducing the parasitic capacitance. At the same time as possible, fiT was applied using a fluid material using the top opening, and by the Chivac method.
This method has the advantage that the amount of upper protrusion of the mold gate can be automatically controlled, making it possible to realize a high-performance semiconductor device.

[Brief explanation of the drawing]

1 (8) to (8) and FIG. 2 (4) to (4) are cross-sectional views showing the first and second embodiments of the method for manufacturing a semiconductor device according to the present invention in the order of steps, and FIGS. 3 to 5 are sectional views of conventional FIG. 2 is a cross-sectional view showing the technique. 11...Semi-insulating substrate, 12...Semiconductor active layer, 13...8i, N, film, 14, 51
......Membrane to 8i, 15°54...Photoresist pattern, 16...Photoresist, 21
=-WS i film, 22-----T i P t
AuHK. 31... Source, 32... Drain,
33... Gate electrode, 52... Opening,
53...Gate metal, 55...T-type gate electrode. ￥Jj diagram 20

Claims (1)

[Claims] a step of providing a semiconductor active layer on a semiconductor substrate and laminating first and second dielectric films on the semiconductor active layer; forming a predetermined photoresist pattern on these dielectric films; The second dielectric film is etched by isotropic etching using the photoresist pattern as a mask to expose the surface of the first dielectric film, and then the first dielectric film is etched by anisotropic etching using the photoresist pattern as a mask. a step of etching the body film to expose the surface of the semiconductor substrate to form an opening; a step of removing the photoresist pattern and then depositing an electrode metal on the entire surface; and a step of depositing an electrode metal on the entire surface on which the electrode metal is provided. The method further comprises a step of applying a substance and dry etching the entire surface in a direction perpendicular to the semiconductor substrate to expose the surface of the second dielectric film, leaving the electrode metal only in the opening. A method for manufacturing a semiconductor device.