JPS6112079A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To realize a MESFET capable of high-speed operations on high frequencies by a method wherein source/drain regions and source/drain electrodes are formed by self-alignment so that the source/drain electrodes may be positioned nearer to a gate metal. CONSTITUTION:On a GaAs semi-insulating substrate 11, an activation layer 12 is formed by low-concentration ion implantation, whereafter a W layer 13 is deposited by CVD. Further, Ni is deposited for the formation of a gate pattern 14, which serves as a mask in a process wherein side etching is accomplished for the W layer 13 to be developed into a gate electrode 13, and source-drain regions 15, 16 are formed by high-concentration ion implantation. Next, a coating of Si3N4 is provided, to be removed except on the sides of the gate electrode 13 for the retention of an insulating side wall 17. The gate pattern 14 is removed, and then a capping SiO2 film 18 is formed to be subjected to annealing for activation. The SiO2 film 18 is removed, a mask is formed in regions outside the semiconductor element, an film of ohmic metal is deposited on the surface for the building of source/drain electrodes 19, 20, and, finally, an ohmic treatment is accomplished.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a Schottky gate field effect transistor (hereinafter referred to as a 5FET).

(Prior art) Conventionally, the technology in this field was disclosed in Japanese Patent Application Laid-open No. 50-1298.
It is described in Publication No. 5. There, semi-insulating GaA
An n-type active layer is formed on an s-substrate, and a heat-resistant metal is deposited thereon. A gate pattern body of a 5t5N4 film is formed on this, and the metal is side-etched using this gate pattern body as a mask to obtain a gate electrode. Next, using the gate/mother turn body as a mask, donor impurity ions are implanted to form source/drain regions in a self-aligned manner.

(Problems to be Solved by the Invention) An object of the present invention is to bring the source/drain electrodes of the prior art closer to the gate metal by forming the source/drain regions in a self-aligned manner. It solves the drawbacks that make it difficult to
The object of the present invention is to obtain a MESFET that performs high frequency operation.

(Means for Solving the Problem) In the present invention, as shown in FIG. 2, side etching is performed on the active layer 2 of the semiconductor substrate using a gate pattern body (not shown) as a mask to form the gate electrode 3. Then, using this gate pattern body as a mask, ions are implanted to form source/drain regions in a self-aligned manner, and then an insulating film is deposited on the entire surface and selectively removed using ion milling. After that, the gate pattern body is removed, and an ohmic metal is laminated on the surface using the gate electrode 3 and its side wall 7 as a mask, thereby forming the source/drain electrodes 9 and 10 in a self-aligned manner. Form.

(Function) In the present invention, source/drain regions and source/drain electrodes are formed in a self-aligned manner, and the distance between the gate electrode and the source/drain regions and source/drain electrodes is determined by adjusting the side etching amount and the gate etching amount. It can be determined by the thickness of the side wall formed on the side surface of the electrode.

(Example) FIGS. 1(a) to 1(c) are sectional views of an element for explaining the present invention in detail, and the following description will be made along the drawings.

First, as shown in FIG. 1(, ), the surface of the GaAs semi-insulating substrate 11 other than the element region is masked and a pn type active layer 12 is formed by low concentration silicon ion implantation.
The W layer 13 of the heat-resistant case material is coated with a thickness of 500 mm by the CVD method.
Layers about 0x5000x. In addition, it has a high ion blocking ability,
Ni having dry etch resistance is laminated to a thickness of about 2500X, and then patterned to form a dirt pattern body 14.
The gate electrode 13 is formed by side etching the W layer 13 using a mask, and then high-concentration silicon ion implantation is performed using the gate pattern body 14 as a mask to form n+7i.
Source/drain regions 15 and 16 of i are formed.

Next, as shown in Fig. 1(b), by CVD method: > 5
After depositing a 13N4 film and selectively removing the S13N4 film other than the side surfaces of the gate electrode by ion milling, leaving an insulating sidewall 17, and further removing the gate/main turn body 14, a 5102 film is formed. cap 18
is formed, and activation annealing is performed at about 800°C.

Next, as shown in FIG. 1(c), after removing the cap 18, a mask (not shown) is formed in the region outside the element, and an ohmic metal is laminated on the surface to a thickness of about 3000×. c), source/drain electrodes 19 separated from the ohmic metal on the gate electrode 13;
20 is obtained. Finally, the source/drain region 15.1
6 and the source/drain electrodes 19 and 20 are subjected to ohmic treatment at about 400°C.

According to an embodiment of the present invention, the gate electrode 13 is
Since the gate pattern body 14 is formed with a thickness of about 2500X, the height of the side wall is about 7500X. 9. Source and r-rain electrodes J separated from the gate electrode 13, respectively. , 20 can be formed.

Further, since the side wall 17 is an insulating film, it can be used without being removed.

Since the material, source/drain regions, and source/drain electrodes are formed in a self-aligned manner, difficult mask alignment is not required.

Furthermore, the spacing between the source/drain electrodes 19, 20 and the 17-to electrode 13 can be determined depending on the amount of side etching and the thickness of the side wall 17.
FET can be formed.

(Effects of the Invention) As explained above, in the present invention, since the source/drain regions and the source/drain electrodes are formed in a self-aligned manner, the distance between the gate electrode and the source/drain regions and the source/drain electrodes is can be determined by the amount of side etching and the thickness of the side walls formed on the side surfaces of the gate electrode, and a MESFET with low parasitic resistance can be easily obtained with good reproducibility.

[Brief explanation of drawings]

1(a) to 1(c) are sectional views of an element for explaining the present invention in detail, and FIG. 2 is a sectional view of an element for explaining the invention in detail. 11... GaAs semi-insulating substrate, 12... active layer,
13·°·gate electrode, 14···gate pattern body,
15... Source region, 16... Drain region, 17
...Side wall, 18...Cap, 19...Source electrode, 20...Drain electrode.

Claims (1)

[Claims] a step of forming an active layer on a semiconductor substrate; a step of laminating a heat-resistant metal that forms a Schottky barrier with the active layer on the active layer to a thickness greater than a predetermined thickness of the source/drain electrode; a step of forming a gate pattern body on the heat-resistant metal; a step of forming a gate electrode by performing side etching of the heat-resistant metal using the gate pattern body as a mask; a step of forming a source region and a drain region by performing ion implantation on the gate electrode; a step of depositing an insulating film on the entire surface including the side surfaces of the gate electrode; a step of leaving a sidewall by removing the gate pattern body; and a step of forming a source electrode and a drain electrode in a self-aligned manner by layering metal that makes ohmic contact on the surface after removing the gate pattern body. A method for manufacturing a semiconductor device, characterized in that: