JPH0682688B2 - Method for manufacturing field effect transistor - Google Patents

Description

The present invention relates to a field effect transistor, and more particularly to a method for manufacturing a field effect transistor having an offset gate structure.

[Conventional technology]

In general, in order to improve the performance of a field effect transistor, it is known to reduce the parasitic resistance Rs by reducing the distance between the source and the gate. Therefore, the self-alignment method using the gate electrode A method of forming the drain region is used. However, this method has a structure in which the source and drain are symmetrically arranged with respect to the gate electrode, and as the distance between the gate and the source decreases, the distance between the gate and the drain also decreases.
Factors that hinder the characteristics such as breakdown voltage reduction and increase in gate-drain capacitance will also increase.

In order to prevent this, an offset gate structure having different gate-source and gate-drain distances is used. As a method of manufacturing this offset gate structure,
For example, a method of forming a source / drain region by offsetting a gate electrode by a positioning technique, or a method of forming a gate electrode first and then offsetting a source / drain region by a positioning technique are known. .

[Problems to be solved by the invention]

However, in such a method of forming the offset amount, that is, the position of the gate electrode with respect to the source / drain region by setting (alignment) technology, it is possible to form the offset amount between the gate and the drain with high accuracy. There is a problem that it is difficult and it is difficult to realize this with good reproducibility.

An object of the present invention is to provide a method for manufacturing a field effect transistor capable of offsetting a gate electrode with respect to a source / drain region with high accuracy and reproducibility without using alignment technology.

[Means for solving problems]

A method of manufacturing a field effect transistor according to the present invention comprises forming a gate metal on an active layer formed on a semi-insulating substrate and selectively etching the gate metal to form an offset amount of a source / drain region of the field effect transistor. A step of forming a first gate electrode and a second gate electrode which are spaced apart according to the above, and at least a space area between the first gate electrode and the second gate electrode is covered with a film. A step of forming a high concentration impurity region as a source / drain region in the semi-insulating substrate by ion implantation using this film and the first and second gate electrodes as a mask; and masking the first gate electrode Then, the step of etching away the second gate electrode is included.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1A to 1F are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and here, an example applied to a GaAs Schottky gate type field effect transistor is shown.

First, as shown in FIG. 1A, a gate metal 3 is deposited on the entire surface of an active layer 2 formed on a semi-insulating substrate 1.
For example, WSi, which is a heat-resistant metal, is formed to a thickness of 5000 Å by a sputtering method.

Next, as shown in FIG. 1B, a first gate pattern 4a and a second gate pattern 4b to be a temporary gate are simultaneously formed by a photoresist. In this case, the dimensions of the patterns 4a and 4b are as follows: first gate length 0.3 μm, second gate length
The distance between the first gate and the second gate is 0.5 μm.

After that, dry etching is performed using, for example, a mixed gas of CF ₄ + SF ₆ , and as shown in FIG.
And the second gate electrode 3b as a temporary gate is formed.

Next, as shown in FIG. 1 (d), after masking the space between the first and second gate electrodes 3a and 3b with the photoresist 5, ion implantation is performed to the outer regions of the first and second gate electrodes 3a and 3b. Then, N ⁺ layers 6 and 6 to be source / drain regions are formed. The implantation conditions are, for example, E = 100 KeV, Φ = 1 × 10
^{It is 13} cm ^-2 .

Next, as shown in FIG. 1 (e), only the first gate electrode 3a is masked with the photoresist 7, and the second gate electrode 3b is dry-etched with a mixed gas of CF ₄ + SF ₆ as described above. The offset gate structure shown in FIG. 1 (f) is obtained.

According to this manufacturing method, the gate electrode 3a finally left
And the distance between the N ⁺ layer 6 on the right side of the drawing as the drain region is the first photoresist pattern, that is, the first for the gate processing.
And the distance between the second gate patterns 4a and 4b and the gate length of the second gate patterns 4a and 4b. Therefore, it is possible to obtain a field effect transistor having an offset structure with very good reproducibility without being affected by the alignment accuracy as in the conventional method.

2 (a) to 2 (d) are sectional views showing a second embodiment of the present invention in the order of manufacturing steps. The first and second gate electrodes 3 are shown in FIG.
The process up to formation of a and 3b is the same as in the first embodiment. The same parts as those in FIG. 1 are designated by the same reference numerals.

After the formation of the first and second gate electrodes 3a and 3b, the SiO ₂ film 8 is formed by the CVD method as shown in FIG.
Grow to a thickness of.

Next, dry etching is performed using a mixed gas of CF ₄ + H ₂ to leave the SiO ₂ film 8 only on the side walls of the gate electrodes 3a and 3b as shown in FIG. 2 (b).

Then, as shown in FIG. 2 (c), by ion implantation,
An N ⁺ layer 6 to be the source / drain region is formed. However, when the distance between the first and second gate electrodes corresponding to the required offset amount is wider than the film thickness of the side wall SiO ₂ film 8, the SiO ₂ film 8 completely masks the space between both gate electrodes. Instead, the underlying active layer 2 is exposed. In this case, as shown in FIG. 1D of the first embodiment, a step of masking between the both gate electrodes with a photoresist is required.

Next, the first gate electrode 3a is masked by the photoresist 9 and the second gate electrode 3b and the side wall SiO ₂ film 8 are etched to obtain the offset gate structure shown in FIG. 2 (d).

Also in this embodiment, the same effect as in the first embodiment can be obtained.

EFFECTS OF THE INVENTION As described above, according to the present invention, after the first gate electrode and the second gate electrode are formed at intervals according to the offset amount, the first gate electrode and the second gate electrode are covered with the ions. Since the step of forming the source / drain regions by implantation and then masking only the first gate electrode to remove the second gate electrode by etching is performed, the distance between the gate electrode and the drain region is set to It will be determined by the distance between the two gate electrodes and the gate length of the second gate electrode,
A field effect transistor having an offset gate structure can be manufactured with excellent reproducibility without being affected by alignment accuracy as in the conventional case.

[Brief description of drawings]

1A to 1F are side views showing the first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2A to 2D are sectional views showing the second embodiment in the order of manufacturing steps. . 1 ... semi-insulating substrate, 2 ... active layer, 3a ... first gate electrode, 3b ... second gate electrode, 4a ... first gate pattern, 4b ... second gate pattern, 5 ... Photoresist, 6 ... Source / drain regions, 7 ... Photoresist, 8 ... SiO ₂ film, 9 ... Photoresist.

Claims (3)

[Claims] 1. A gate metal is formed on an active layer formed on a semi-insulating substrate, and the gate metal is separated by an interval corresponding to an offset amount of a source / drain region of a field effect transistor to be selectively etched. Forming a first gate electrode and a second gate electrode, and covering at least a gap region between the first gate electrode and the second gate electrode with a film, and then forming the film and the first gate electrode. 1st and 2nd
Forming a high-concentration impurity region as a source / drain region in the semi-insulating substrate by ion implantation using the gate electrode as a mask, and removing the second gate electrode by masking the first gate electrode A method of manufacturing a field effect transistor, comprising: 2. The method for manufacturing a field effect transistor according to claim 1, wherein a space between the first and second gate electrodes is covered with a photoresist. 3. The method for manufacturing a field effect transistor according to claim 1, wherein a space between the first and second gate electrodes is covered with an insulating film.