JP2518402B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly, to a gate / recess structure having two recess steps and a gate electrode having a T-shaped cross section. In particular, the present invention relates to a method of manufacturing a field effect transistor in which the distance between the head of the T-shaped gate electrode and the upper recessed step is increased.

[Conventional technology]

FIG. 4 shows a conventional two-step recess structure and a semiconductor device provided with a gate electrode having a T-shaped cross section, specifically, a cross sectional structure of a main part of a field effect transistor, and FIG. The manufacturing process of a field effect transistor is shown. Fourth
In the figure, an active layer 4 is formed on the GaAs substrate 2 by ion implantation or another method, and a width W _GS is formed on the upper surface of the active layer 4.
Upper gate / source recess stage 6, width W _GD upper gate / drain recess stage 8, and width W _G lower recess stage
10 are formed. The tip portion 14 of the T-shaped gate electrode 12 is in contact with the lower recess step 10. The width of the tip portion 14, that is, the gate length is l _g , and the width of the entire recess 16 is W. In general, the lower recess stage 10 provided with the T-shaped gate electrode 12 to improve the characteristics of the transistor is offset toward the source electrode side, and is formed in a positional relationship of W _GS <W _GD .

Next, a method of manufacturing the field effect transistor of FIG. 4 will be described with reference to FIG.

As shown in FIG. 3A, an active layer 4 is formed on the GaAs substrate 2 by ion implantation or another method, and a first SiN film 18 for forming a dummy gate is deposited on the active layer 4. Further, a positive resist 20 for forming an upper recess step is patterned on the first SiN film 18 for forming a dummy gate.

Next, as shown in FIG. 3B, the first SiN film 1 for forming a dummy gate is formed using the pattern of the positive type resist 20.
After removing a part of 8 by chemical etching, the active layer 4 is also subjected to recess etching by chemical etching to obtain a width W ′.
_G dummy gate portion 22, upper gate of source width W ′ _GS , source recess step forming opening 24, upper gate of width W ′ _GD ,
A drain recess step forming opening (26) is formed. In this case, W _'GS <W' _GD become so that the position of each upper recess stage formation openings, the dimensions are determined.

Next, as shown in FIG. 3 (c), the positive resist
After removing 20 and the first SiN film 18 for forming a dummy gate, the dummy gate portion 22, the upper gate / source recess step forming opening 24, and the upper gate / drain recess step forming opening 26 are formed on the surface. A second SiN film 28 having a different etching characteristic from the first SiN film 18 and a predetermined etchant is formed so as to cover the entire surface of the active layer 4 having the film formed therein.
Further, a resist 30 is formed on the second SiN film 28, and an opening 32 for forming the head of the T-shaped gate electrode is formed in a region of the resist 30 corresponding to the region where the gate electrode is to be formed.

Next, as shown in FIG. 3D, the opening of the resist 30 is formed.
The second SiN film 28 is etched from 32 by chemical etching or the like to expose the cue portion 34 of the dummy gate portion 22.

Next, as shown in FIG. 3E, the active layer 4 is etched by chemical etching or the like using the second SiN film 28 as a mask to form the lower recess portion 10 of the width W _G. By this etching process, the upper gate / source recess step 6 of the width W _GS and the upper gate / drain recess step 8 of the width W _GD are simultaneously formed. As a result, the width of the entire recessed stage 16 is W, the width of the lower recessed stage 10 is W _G , and due to the positional relationship of W _GS <W _GD , the offset type 2 in which the gate-source interval is narrower than the gate-drain interval is used. A step gate / recess structure is obtained.

Then, a third metal is deposited in the opening 32 by a method such as metal deposition.
A T-shaped gate electrode 12 is formed as shown in FIG.
At the same time, gate metals 38a and 38b are formed on the resist 30. Then, using a method such as lift-off, gate metal 38
a, 38b, and resist 30 are removed, and finally the second SiN
By removing the film 28 by chemical etching, as shown in FIG. 4, a field effect transistor having an offset type two-step recess T-shaped gate electrode structure in which the length of the gate electrode tip portion 14 is l _g is obtained.

[Problems to be Solved by the Invention]

Since the conventional field effect transistor is configured as described above, the space between the head portion 40 of the T-shaped gate electrode 12 and the upper recess steps 6 and 8 formed in the active layer 4 is inevitable. Since the size of the field effect transistor becomes narrower, foreign matter remains during this process, the breakdown voltage is significantly reduced, and the parasitic capacitance is increased, resulting in a decrease in reliability and performance of the field effect transistor.

The present invention manufactures a field effect transistor which eliminates the above-mentioned drawbacks of the conventional field effect transistor by increasing the distance between the head of the T-shaped gate electrode and the upper recess of the active layer. Aim to get a way.

[Means for solving the problem]

In the method for manufacturing a field effect transistor according to the present invention, a first SiN film for forming a dummy gate is thinly formed on an active layer, and the first SiN film has a different etching target characteristic with respect to a predetermined etchant. The gate length when the first SiN film and the second SiN film are removed by depositing the second SiN film to increase the total thickness of the first SiN film and the second SiN film It is possible to form a field effect transistor having a short length and an increased distance between the head of the T-shaped gate electrode and each upper recess of the active layer.

[Work]

According to the method of manufacturing the field effect transistor of the present invention, the distance between the gate electrode and the upper recess of the active layer is set to be smaller than that of the conventional field effect transistor by the first Si.
Since the thickness can be increased by the amount corresponding to the thickness of the N film, the breakdown voltage is improved and a field effect transistor with a small parasitic capacitance can be obtained.

〔Example〕

Hereinafter, the structure of the field effect transistor manufactured by the present invention and the manufacturing method thereof will be described with reference to FIGS. 1 (a) to 1 (f) and FIG.

1 (a) and 1 (b) are shown in FIGS. 3 (a) and 3 (b).
As in the conventional process, the dummy gate portion 22 having the width W ′ _G , the upper gate / source recess step forming opening 24 having the width W ′ _GS , and the upper gate / drain recess step having the width W ′ _GD are formed in the same process as the above. A forming opening 26 is formed. The relationship between W _'GS and W' _GD is set to be the same manner as heretofore W _'GS <W' _GD.

Next, as shown in FIG. 1C, after removing the positive type resist 20, the upper recess step forming openings 24 and 26 and the dummy gate forming first SiN film 18 are covered, and The first SiN film 18 for forming a dummy gate has a different etching target characteristic with respect to a predetermined etchant,
Deposit a second SiN film 42 that is etched with an etchant that does not attack film 18. Then, the second SiN film 42
After forming a resist 44 on the entire surface of the resist 44, a head forming opening for forming a gate electrode head having a T-shaped cross section at a position corresponding to a region where the gate electrode of the resist 44 is formed. Form 46.

Next, the second SiN film 42 is chemically etched through the opening 46 of the resist 44 to expose the cue 48 of the first SiN film 18 for forming a dummy gate, as shown in FIG. 1D. .

Next, the first dummy gate formation shown in FIG.
The head portion 48 of the SiN film 18 is etched by chemical etching using an etchant that does not attack the second SiN film 42, and then the active layer 4 is etched by chemical etching, as shown in FIG. 1 (e). A lower recess step 10 having a uniform width W _G is formed.
Simultaneously with the formation of this lower recess step 10, an upper gate / source recess step 6 of width W _GS and an upper gate / drain recess step 8 of width W _GD are formed.

Through the above steps, the width of the entire recess 16 is W, the width of the lower recess 10 is W _G , and the gate-source interval is made narrower than the gate-drain interval due to the positional relationship of W _GS <W _GD . An offset type two-stage gate recess structure is obtained.

Next, a T-shaped gate electrode 50 is formed in the opening 46 by a method such as metal deposition, as shown in FIG. At the same time, gate metals 52a and 52b are formed on the resist 44. Then, the gate metals 52a and 52b and the resist 44 are removed by lift-off or the like, and finally the second SiN film 42 and the first SiN film 18 for forming a dummy gate are sequentially removed to obtain the gate length shown in FIG. Is a T-shaped gate electrode 50 with a tip 14 of l _g
A field effect transistor having an offset type two-stage recess T-shaped gate electrode structure having the above structure is obtained.

〔The invention's effect〕

According to this invention, the head 52 of the T-shaped gate electrode 50 is
As compared with the field effect transistor manufactured by the conventional method shown in FIG. 4, the upper recesses 6 and 8 of the active layer 4 are separated from each other by an amount corresponding to the thickness of the first SiN film 18. Even if foreign matter remains between 52 and the upper recess stages 6 and 8, the leak current does not increase or the breakdown voltage does not decrease, and a highly reliable field effect transistor can be obtained. it can. Further, as described above, the head portion 52 of the T-shaped gate electrode 50 has the upper recess steps 6 and 8 of the active layer 4 respectively.
Since it is far away from the device, the parasitic capacitance is remarkably reduced, and a field effect transistor having excellent high frequency characteristics can be obtained. The thickness of the SiN layer 42 is the T-shaped gate electrode 5
It goes without saying that it can be set arbitrarily according to the distance that needs to be provided between the head portion 52 of 0 and the upper recess steps 6 and 8 of the active layer 4.

[Brief description of drawings]

1 (a) to 1 (f) are cross-sectional views at each manufacturing stage for explaining a method of manufacturing a semiconductor device according to the present invention,
FIG. 2 is a sectional view showing the structure of the main part of a semiconductor device manufactured through the manufacturing steps of FIG. 1, and FIGS. 3 (a) to 3 (f).
4A and 4B are cross-sectional views in each manufacturing step for explaining a conventional method for manufacturing a semiconductor device, and FIG. 4 is a cross-sectional view showing a configuration of a main part of a conventional semiconductor device manufactured through the manufacturing steps in FIG. . 4 ... Active layer, 6 ... Upper gate / source recess stage, 8
...... Upper gate / drain recess, 10 …… Lower recess, 14 …… Tip, 18 …… First dummy gate formation
SiN film, 24 ... Opening for upper gate / source recess step formation, 26 ... Opening for upper gate / drain recess step formation, 42 ... Second SiN film, 44 ... Resist, 46 ... T-shaped Opening for forming the gate electrode head, 50 ... T-shaped gate electrode.

Claims (1)

(57) [Claims] 1. A wide upper gate / source recess step forming opening and an upper gate / drain recess step forming are left on the active layer, leaving a first SiN film for forming a dummy gate having a predetermined pattern. A step of forming an opening for use, the opening for forming the upper gate / source recess step, the opening for forming the upper gate / drain recess step, and the first SiN film for forming the dummy gate, and the first SiN film And a second Si with different etching characteristics for a given etchant
A step of depositing an N film, and forming a head for forming a head of a gate electrode having a T-shaped cross section on the second SiN film on a region where a gate electrode is to be formed. A step of forming a resist having an opening, and using the resist as a mask to etch the second SiN film exposed in the head forming opening to form a first SiN film for forming the dummy gate. The step of exposing the crest portion and the etching of the exposed crest portion of the first SiN film using an etchant that does not attack the second SiN film are performed to remove the exposed portion of the gate electrode. A step of exposing the active layer, and etching the exposed active layer to form a narrow lower recess step offset to approach the source side, and to form a wide upper gate, source recess step and upper gate step. Drain Forming respective recessed steps, and forming a gate electrode having a T-shaped cross section with a tip contacting the narrower recessed step in the head forming opening by a method such as metal deposition. A step of sequentially removing the resist, the second SiN film, and the first SiN film for forming a dummy gate; and the enlarged head portion of the gate electrode having a T-shaped cross section and the active layer. A method of manufacturing a semiconductor device in which an interval between an upper gate / source recess stage and an upper gate / drain recess stage is widened.