JPH03239337A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03239337A
JPH03239337A JP3666790A JP3666790A JPH03239337A JP H03239337 A JPH03239337 A JP H03239337A JP 3666790 A JP3666790 A JP 3666790A JP 3666790 A JP3666790 A JP 3666790A JP H03239337 A JPH03239337 A JP H03239337A
Authority
JP
Japan
Prior art keywords
recess
substrate
insulating film
forming
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3666790A
Other languages
Japanese (ja)
Inventor
Takeshi Kuragaki
丈志 倉垣
Mitsunori Nakatani
光徳 中谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3666790A priority Critical patent/JPH03239337A/en
Publication of JPH03239337A publication Critical patent/JPH03239337A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To maintain the offset amount between a first recess and a second recess constant at all times by a method wherein a lozenge insulating film is formed on a substrate and a specific side-end edge part of the insulating film is removed sequentially to form the first recess and the second recess. CONSTITUTION:An insulating film 2 of a lozenge pattern is formed; a second photoresist layer 4 having a pattern in a desired shape is formed on a substrate 1. One part of the insulating film 2 is left on the sidewall on one side of the second photoresist layer 2; the GaAs substrate 1 is etched by using the pattern as a mask; a first recess 6 is formed. Then, the insulating film 2 is etched and removed; the GaAs substrate 1 is etched again to form a second recess 7. The recess is an offset two-stage recess in which individual central positions of an upper-stage recess part and a lower-stage recess part are dislocated. Thereby, a minute gate can be formed; a self-alignment operation can be executed; an offset amount can be maintained always constant.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、二段リセス構造を有する半導体装置の製造
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device having a two-stage recess structure.

〔従来の技術〕[Conventional technology]

第3図は従来の二段リセス構造を有する半導体装置の製
造方法の工程を示す断面図である。同図において、(1
)はGaAs基板、(3)、(4)はフォトレジスト層
、(5)はゲート金属層である。以下、図について説明
する。
FIG. 3 is a cross-sectional view showing steps in a conventional method for manufacturing a semiconductor device having a two-stage recess structure. In the same figure, (1
) is a GaAs substrate, (3) and (4) are photoresist layers, and (5) is a gate metal layer. The figures will be explained below.

先ず、GaAs基板(1)上に第1のフォトレジスト層
(3)を形成し、その層にフォトリソクラフィにより第
3図(a)に示すように所望のパターンを形成する。次
に、上記フォトレジスト層(3)をマスクとして酒石酸
でGaAs基板(1)をエツチングし、第3図(b)に
示すように第1のリセス(6)を形成する。次に、上記
フォトレジスト層(3)を除去した後、第2のフォトレ
タスl−屑(4)を形成し、その層のうち第1のリセス
(6)を覆う部分の一部にフォトリソクラライにより第
3図(C)のように所望のパターンを形成する。次に、
酒石酸により第3図(d)に示すように第1のリセス(
5)よりも幅か狭い第2のリセス(7)を形成する。次
に第3図(e)に示すように、蒸着法によりゲート金属
層(5)を形成した後、リフトオフを行って第2のフォ
トレジスト層(4)及びその居士のゲート金属層(5)
を除表し、第3図(f)に示すように、リセス内のゲー
ト金属層(5)のみを残す。
First, a first photoresist layer (3) is formed on a GaAs substrate (1), and a desired pattern is formed on the layer by photolithography as shown in FIG. 3(a). Next, using the photoresist layer (3) as a mask, the GaAs substrate (1) is etched with tartaric acid to form a first recess (6) as shown in FIG. 3(b). Next, after removing the photoresist layer (3), a second photolettuce scrap (4) is formed, and a part of the layer covering the first recess (6) is coated with photolithography. A desired pattern is formed as shown in FIG. next,
Tartaric acid creates the first recess (
Form a second recess (7) narrower than 5). Next, as shown in FIG. 3(e), after forming a gate metal layer (5) by vapor deposition, lift-off is performed to form a second photoresist layer (4) and a gate metal layer (5) thereon.
As shown in FIG. 3(f), only the gate metal layer (5) in the recess is left.

〔発明か解決しようとする課題〕[Invention or problem to be solved]

従来の製造方法では、第2のリセス(7)を形成する場
合、フォトリンクラライの工程において第1のリセス(
6)との間にアライメントか必要であるため、第1及び
第2のリセス間のオフセット量(第1及び第2のリセス
の中心位置のずれ量)を常に一定に維持することか困難
てあった。
In the conventional manufacturing method, when forming the second recess (7), the first recess (7) is formed in the photo linking process.
6), it is difficult to maintain the offset amount between the first and second recesses (the amount of deviation in the center position of the first and second recesses) constant. Ta.

この発明は、L記のような問題点を解消するためになさ
れたものて、第2のリセス形成時における第1のリセス
との間のアライメントを不要にして、つまりセルフアラ
イメントを可能にして、常に一定のオフセット酸を有す
る二段リセス構造の半導体装置を製造することかてきる
方法を得ることを目的とする。
This invention was made in order to solve the problem as described in L, and eliminates the need for alignment between the second recess and the first recess when forming the second recess, that is, enables self-alignment, The object of the present invention is to obtain a method for manufacturing a semiconductor device having a two-stage recess structure that always has a constant offset acid.

(課題を解決するための手段) この発明に係る゛[導体装置の製造方法は、半導体基板
]二に菱形形状の絶縁膜を形成し、次に、その絶縁膜の
一方の側端縁部分を残してその他の絶縁膜部分を除去し
て半導体基板(第1のリセスを形成し、次に、絶縁膜の
一方の側端縁部分を除去して半導体基板に第2のリセス
を形成して、半導体基板に二段リセス構造を形成するよ
うにしたものである。
(Means for Solving the Problems) A method for manufacturing a conductor device according to the present invention includes forming a diamond-shaped insulating film on a semiconductor substrate, and then forming a diamond-shaped insulating film on one side edge of the insulating film. The remaining insulating film portion is removed to form a first recess in the semiconductor substrate, and then one side edge portion of the insulating film is removed to form a second recess in the semiconductor substrate. A two-stage recess structure is formed in a semiconductor substrate.

〔作用〕[Effect]

この発明における半導体装置の製造方法では、菱形形状
の絶縁膜を形成することにより、第2のリセス形成時に
アライメントか不要となり、第1及び第2のリセス間の
オフセット量か常に一定に維持される。
In the method for manufacturing a semiconductor device according to the present invention, by forming a diamond-shaped insulating film, alignment is not required when forming the second recess, and the amount of offset between the first and second recesses is always maintained constant. .

〔実施例) 以F、この発明の一実施例を第1図について説明する。〔Example) Hereinafter, one embodiment of the present invention will be described with reference to FIG.

第1図(a)〜(j)は製造方法の主要工程を示す断面
図てあって、同図において、(2)は酸化シリコンまた
は窒化シリコン等の絶縁膜である。なお、第3図と同一
・符号はその園と同一または相当部分を示す。
FIGS. 1(a) to 1(j) are cross-sectional views showing the main steps of the manufacturing method, in which (2) is an insulating film made of silicon oxide, silicon nitride, or the like. Note that the same reference numerals as in Figure 3 indicate the same or corresponding parts as those in the garden.

先ず、第1図(a)に示すように、例えば約6004m
の厚さを持ったにaAs基板(1)−、)、に厚さか約
lp、mの絶縁膜(2)を形成し、更にその上に、約0
.8 grn程度の厚さの第1のフォトレジスト層(3
)を形成し、通常の露光技術を用いてその層に所望形状
のマスクを形成する。次に、弗化硫黄(SF、、)を用
いた反応性イオンど−ムエッチング(RIRE)を、垂
直方向に対して角度θの斜め方向から行い、第1図(b
)に示すように絶縁膜(2)が菱形形状となるパターン
を形成する。なお、イオンビーム黒用角度θは例えば約
30°〜45°に選ぶ。
First, as shown in Figure 1(a), for example, about 6004 m
An insulating film (2) with a thickness of about lp, m is formed on an aAs substrate (1)-, ) with a thickness of about 0.
.. The first photoresist layer (3
), and a mask of the desired shape is formed on that layer using conventional exposure techniques. Next, reactive ion etching (RIRE) using sulfur fluoride (SF) was performed from an oblique direction at an angle θ with respect to the vertical direction.
), the insulating film (2) is formed into a diamond-shaped pattern. Note that the ion beam black angle θ is selected to be approximately 30° to 45°, for example.

また、マスク長さM、絶縁膜(2)の膜J’7dとすれ
ば、M−d tan Oか後工程で形成される第1のリ
セスの幅、すなわち第1図(f)に示すリセス幅W、を
決定する。
Also, if the mask length is M and the film J'7d of the insulating film (2), M-d tan O is the width of the first recess formed in the subsequent process, that is, the recess shown in FIG. 1(f). Determine the width W.

次に、第Iのフォトレジス1〜層(3)を除去した後、
第2のフォトレジストを全面にaCt、、マスク合わせ
、露光、及び現像により、第1図(c)に示すような所
望形状のパターンを右する第2のフォトレジスト層(4
)を基板(1,)上に形成する。次に、140°C以上
に加熱して、第1図(d)に示すように第2のフォトレ
ジスト層(4)を熱変形させてそのフォトレジスト層を
絶縁v(2)の周辺に密着させ、その後、SF、を用い
て反応性イオンビームエツチングを行い、第1図(e)
に示すように、第2のフォトレジスト層(4)の片側の
側壁に絶縁膜(2)の一部が残るようにする。そして、
このパターンをマスクにして、酒石酸でGaAs基板(
1)をエチングし、第1図(f)に示すように第1のリ
セス(6)を形成する。なお、例えば、基板(1)内に
不純物濃度的1017/C[11’て生成された厚さ約
5000Åのエピタキシャル府内に第1のリセス(6)
を形成する場合は、そのリセスの深さ約2000λであ
る。
Next, after removing the I-th photoresist 1 to layer (3),
Apply a second photoresist to the entire surface by aCt, mask alignment, exposure, and development to form a pattern of the desired shape as shown in FIG. 1(c).
) is formed on the substrate (1,). Next, the second photoresist layer (4) is heated to 140°C or higher to thermally deform it as shown in FIG. After that, reactive ion beam etching was performed using SF, as shown in Fig. 1(e).
As shown in FIG. 2, a portion of the insulating film (2) is left on one side wall of the second photoresist layer (4). and,
Using this pattern as a mask, tartaric acid was applied to the GaAs substrate (
1) to form a first recess (6) as shown in FIG. 1(f). Note that, for example, a first recess (6) is formed in the epitaxial region with a thickness of about 5000 Å, which is generated in the substrate (1) at an impurity concentration of 1017/C[11'.
When forming a recess, the depth of the recess is about 2000λ.

第1のリセス形成後、第11′XI(g)に示すように
、第2のフオトレシス1へ層(4)の片側の側壁にある
絶縁膜(2)を弗酸てエッチンク除去し、その後、再び
酒石酸でGaAs基板(1)をエッチンクし、第1図(
11)に示すように、第2のリセス(7)を形成する。
After forming the first recess, as shown in No. 11' Etch the GaAs substrate (1) again with tartaric acid, as shown in Figure 1 (
11), a second recess (7) is formed.

このリセスはL段すセス部と下段リセス部の各中心位置
がずれたオフセット二段リセスである。なお、このリセ
スの深さは第1のリセスよりも更に2000λ程度深い
This recess is an offset two-stage recess in which the centers of the L-stage recess portion and the lower-stage recess portion are shifted from each other. Note that the depth of this recess is about 2000λ deeper than the first recess.

次に、第1図(i)に示すように、蒸着法でゲート金属
層(5)を形成した後、第1図(j)に示すように、リ
フトオフを行って、第2のフォトレジスト層(4)とそ
の層」二のゲート金属層(5)を除去し、第2のリセス
(7)内に形成されたゲート金属層(5)のみを残す。
Next, as shown in FIG. 1(i), after forming a gate metal layer (5) by vapor deposition, as shown in FIG. 1(j), lift-off is performed to form a second photoresist layer. The second gate metal layer (5) is removed, leaving only the gate metal layer (5) formed within the second recess (7).

次に、この発明の他の実施例を第2図を用いて説明する
。同図において、ff11図と同一符号はその図と同一
または相当部分を示す。
Next, another embodiment of the present invention will be described using FIG. 2. In the figure, the same reference numerals as in figure ff11 indicate the same or corresponding parts as in that figure.

先ず、第2図(a)に示すように、GaAs基板(1)
Lに窒化シリコンから成る絶縁膜(2)を形成し、その
膜の一部を除いて、集束イオンビーム(FIB)法によ
り斜め方向から3 i + +を300KcV、注入深
さ0.25gmて5 X ]Q+4/C113の濃度ま
で注入する。
First, as shown in FIG. 2(a), a GaAs substrate (1) is
An insulating film (2) made of silicon nitride is formed on L, and with the exception of a part of the film, 3 i + + is implanted from an oblique direction at 300 KcV and an implantation depth of 0.25 gm using a focused ion beam (FIB) method. X] Inject to a concentration of Q+4/C113.

次に、第2図(b)に示すように、10%II(、Qて
イオン注入領域のみ除去する。その後の工程は第1図(
c)〜(j)の各工程と同様であるので、説明は省略す
る。
Next, as shown in FIG. 2(b), only the ion implantation region is removed using 10%II(,Q).The subsequent steps are as shown in FIG.
Since the steps are the same as those in c) to (j), the explanation will be omitted.

上述の各実施例では、菱形形状の絶縁膜(2)を形成す
ることにより二段リセス構造を形成するのて、従来法よ
りも微細なゲートを形成することがてきる。また、第1
図(j)及び第2図(j)において、例えばトレイン電
極をゲート金属層(5)に対して左側に設ければトレイ
ン耐圧の高い電界効果トランジスタが得られる。
In each of the above-described embodiments, a two-stage recess structure is formed by forming a diamond-shaped insulating film (2), thereby making it possible to form a finer gate than in the conventional method. Also, the first
In FIG. 2(j) and FIG. 2(j), for example, if the train electrode is provided on the left side with respect to the gate metal layer (5), a field effect transistor with high train breakdown voltage can be obtained.

(発明の効果) 以上のように、この発明によれば、セルフアライメント
か可能てあり、オフセット量が常に一定に維持された二
段リセス構造の半導体装置を製造することができる。
(Effects of the Invention) As described above, according to the present invention, it is possible to manufacture a semiconductor device having a two-stage recess structure in which self-alignment is possible and the amount of offset is always maintained constant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による半導体装置の製造方
法の主要工程を示す断面図、第2図はこの発明の他の実
施例による半導体装置の製造方法の主要工程を示す断面
図、第3図は従来の半導体装置の製造方法の各工程を示
す断面図である。 図において、(1)は半導体基板、(2)は絶縁膜、(
4)はレジスト層、(5)、は電極、(6)は第1のリ
セス、(7)は第2のリセスである。 なお、各図面中、同一符号は同−又は相当部分を示す。 代  理  人     大  岩  増  雄猶 1 図 (1) 特開平3 239337 (4) 第 図 (2) ワ 拓 2 図 (1) 弔 (2)(2)
FIG. 1 is a sectional view showing the main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the main steps of a method for manufacturing a semiconductor device according to another embodiment of the invention. FIG. 3 is a cross-sectional view showing each step of a conventional method for manufacturing a semiconductor device. In the figure, (1) is a semiconductor substrate, (2) is an insulating film, (
4) is a resist layer, (5) is an electrode, (6) is a first recess, and (7) is a second recess. In each drawing, the same reference numerals indicate the same or corresponding parts. Agent Masu Oiwa Yuyu 1 Figure (1) JP-A-3 239337 (4) Figure (2) Wataku 2 Figure (1) Condolences (2) (2)

Claims (1)

【特許請求の範囲】[Claims] (1)対向する両側端縁が半導体基板の垂直方向に対し
て所望の角度をなす方向に伸延する菱形形状の絶縁膜を
その基板の一部分上に形成する第1の工程と、 上記絶縁膜と密着するようにしてその周囲の上記基板上
にレジスト層を形成する第2の工程と、上記レジスト層
の一方の側壁に上記絶縁膜の一方の側端縁側の一部が残
るようにして上記絶縁膜を除去し、そのレジスト層に第
1の開口部を形成する第3の工程と、 上記第1の開口部を介して上記基板に第1のリセスを形
成する第4の工程と、 上記絶縁膜の一部を除去して上記レジスト層に第2の開
口部を形成する第5の工程と、 上記第2の開口部を介して上記基板に第2のリセスを形
成する第6の工程と、 上記第2のリセス中 に電極を形成する第7の工程と、 を具備した半導体装置の製造方法。
(1) A first step of forming, on a portion of the substrate, a diamond-shaped insulating film whose opposite side edges extend in a direction forming a desired angle with respect to the vertical direction of the semiconductor substrate; a second step of forming a resist layer on the substrate around the substrate in close contact with the substrate; a third step of removing the film and forming a first opening in the resist layer; a fourth step of forming a first recess in the substrate through the first opening; and a fourth step of forming a first recess in the substrate through the first opening. a fifth step of forming a second opening in the resist layer by removing a portion of the film; and a sixth step of forming a second recess in the substrate through the second opening. , a seventh step of forming an electrode in the second recess, and a method for manufacturing a semiconductor device.
JP3666790A 1990-02-16 1990-02-16 Manufacture of semiconductor device Pending JPH03239337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3666790A JPH03239337A (en) 1990-02-16 1990-02-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3666790A JPH03239337A (en) 1990-02-16 1990-02-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03239337A true JPH03239337A (en) 1991-10-24

Family

ID=12476211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3666790A Pending JPH03239337A (en) 1990-02-16 1990-02-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03239337A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0594978A2 (en) * 1992-10-26 1994-05-04 Mitsubishi Denki Kabushiki Kaisha Method for producing a field effect transistor
EP0614230A2 (en) * 1993-03-05 1994-09-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with recessed gate and production method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0594978A2 (en) * 1992-10-26 1994-05-04 Mitsubishi Denki Kabushiki Kaisha Method for producing a field effect transistor
US5338703A (en) * 1992-10-26 1994-08-16 Mitsubishi Denki Kabushiki Kaisha Method for producing a recessed gate field effect transistor
EP0594978A3 (en) * 1992-10-26 1995-02-01 Mitsubishi Electric Corp Method for producing a field effect transistor.
EP0614230A2 (en) * 1993-03-05 1994-09-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with recessed gate and production method thereof
EP0614230A3 (en) * 1993-03-05 1995-11-02 Mitsubishi Electric Corp Semiconductor device with recessed gate and production method thereof.
US5548144A (en) * 1993-03-05 1996-08-20 Mitsubishi Denki Kabushiki Kaisha Recessed gate field effect transistor

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