JPH03235335A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To enable formation of a structure having a gate electrode on a low-concentration-dope drain region in a simple manner and with excellent controllability by a method wherein a resist on the gate electrode is developed with the amount of exposure varied, and the main body part of a gate and the outer peripheral part thereof are made different in thickness from each other and are used as a mask. CONSTITUTION:After a gate oxide film 22 is formed on the surface of a silicon substrate 21, a polysilicon layer 23 is deposited and a resist 24 is applied thereon. Then, a gate electrode pattern (a) and then a main body part (b) are exposed by an electron beam and developed, so that a stepped resist 24' be formed. Next, the layer 23 is etched with the resist 24' used as a mask and thereby a polysilicon gate electrode 23' is formed. Next, ion implantation is executed with the electrode 23' used as a mask and thereby high-concentration source.drain regions 26 and 27 and low-concentration source.drain regions 28 and 29 are formed. According to this constitution, a low-concentration-dope drain(LDD) structure can be formed in a simple manner and with excellent controllability and a resistance to hot carriers is also improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing an LDD structure FET, the resist on the gate electrode is exposed to light for the purpose of forming a structure having a gate electrode on the LDD region with good controllability through a simple process. Develop with different amounts to make the main body part of the gate and the part above the LDD region have different thicknesses, and then implant ions from above the gate electrode to form a high concentration source/drain region and a low concentration region of the gate electrode. Configure as a process.

[Industrial application field]

The present invention relates to a method for manufacturing a field-effect transistor (FET), and more particularly, to a method for manufacturing a field-effect transistor (FET), and more particularly, to a method for manufacturing a field-effect transistor (FET), and more particularly, to
F with a ghtly doped drain) structure
The present invention relates to a method for manufacturing ET.

[Conventional technology]

In order to increase the hot carrier resistance of a MOS transistor, it is effective to employ an LDD structure. Figure 4 shows a typical LDD structure MO3) transistor, in which the low concentration region 1
・2 is formed using the polysilicon gate 3 as a mask,
- Blade high concentration area 45 is 5102 left on the side wall of gate 3
It is formed using the spacer 6 as a mask. In this structure, since the fog of the gate electrode 3 with respect to the low concentration region 1.2 is small, the electric field due to the gate does not reach the low concentration region 1.2. 5i02 is also easily trapped in the gate oxide film 7, resulting in a deterioration mode unique to LDDs.

Therefore, as shown in FIG. 5, after stopping the etching of the polysilicon gate 13 midway and leaving a thin layer of polysilicon 13' on both ends of the gate, first ion implantation 11.
12L, then CV[3Sin. CVD 51 is formed on the sidewalls of the polysilicon gate 13 by anisotropic etching.
02 as a spacer 16 (FIG. 4(a)), and polysilicon 13 using this and the polysilicon gate as a mask.
A method has been proposed in which the heavily doped source/drain regions 14 and 15 are formed by etching the etching layer 1 and then implanting ions again.

[Problem to be solved by the invention]

In the structure shown in Fig. 5, the gate electrode extends over the low concentration region, so the deterioration mode shown in Fig. 4 is solved, but the manufacturing process is complicated or the process controllability is poor. bad. When etching polysilicon, both ends of the polysilicon gate are left unetched by stopping the etching midway through, but the controllability of the etching is poor because the end point detector that monitors the completion of etching and sowing cannot be used. .

Furthermore, after etching the polysilicon, Si[) is formed. In order to stack the 5in2 polysilicon and etch the 5in2 polysilicon,
It is necessary to go through a complicated process of etching by changing the soching gas. In addition, ion implantation is performed twice to separate the low concentration region and the high concentration region.

Therefore, the present invention simplifies the process and has good controllability.
The purpose is to manufacture an LDD structure with a gate electrode also on a high concentration region by one ion implantation.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a step of forming a gate electrode layer on a semiconductor substrate, forming a resist layer on the gate electrode layer, and controlling the exposure amount to at least the core resist layer in the gate forming region. A process of exposing to light with in-plane distribution and developing to form a resist pattern for forming a gate electrode that is thick on the gate electrode body and thin at least at the end on the drain electrode side, and using the resist pattern as a mask to form a resist pattern for forming the gate electrode. etching the layer to form a gate electrode that is thicker in the body and thinner at least at the end on the drain electrode side;
implanting ions into the semiconductor substrate using the gate electrode as a mask, forming a highly doped region in the source/drain region of the semiconductor substrate and a lightly doped region under at least the drain side end of the gate electrode. A method of manufacturing a field effect transistor having an LDD structure is provided.

The exposure method is not limited, and may be any of light exposure, electron beam exposure, X-ray exposure, etc., and the method of changing the exposure amount is also not limited.

[For production]

In this method, the gate electrode remains thin only at both ends of the gate electrode, so the area where the gate electrode remains is overwhelmingly smaller than the area lost by etching. For this purpose it is possible to use an endpoint detector. Furthermore, the process of depositing an oxide film for a spacer and the process of changing the etching gas during etching and soching of SiO□ polysilicon, as in the conventional example, are no longer necessary. Furthermore, if EB or X-rays are used for exposure, the size of the spacer can be controlled finely and accurately.

〔Example〕 This will be explained with reference to the drawings.

After oxidizing the surface of the silicon substrate 21 to form a gate oxide film 22 with a thickness of 200 mm, a polysilicon layer 23 is formed with a thickness of 4 mm.
000 A, and further coated thereon with a CMS (chloromethylated polystyrene) resist 24 to a thickness of 1.2 cm. After this, (1) the electron beam is 2.4 x 10” C/crj
At the dose amount, first, the length in the channel direction is o, 6oI! m
The gate electrode pattern (portion a in Figure 1 (a)) is exposed to light, and then the length of the gate electrode in the channel direction is 0.35-
The main body portion of = (portion b in Fig. 1 (a)) is exposed.

When this twice-exposed CMS resist is developed, as shown in Figure 1 (a), the thickness of part a is 670 mm, and the thickness of part b is 1.2 mm.
■Resist remains on.

(2) Or, 2.4 5 Xl0-5C/c in region b.
When this is exposed at a dose of rl and developed, there is 6 in part a.
A 1.2p CMS resist remains in the 7OASb portion.

FIG. 2 shows the relationship between the electron beam exposure amount and the remaining film thickness of the CMS resist for the same CMS resist (thickness 1.2 marks). As seen in this graph, the resist remaining film thickness can be controlled by controlling the exposure amount. Controlling the exposure amount is easy with an electron beam.

Next, using the stepped resist 24' as a mask, the polysilicon layer 23 is etched with HBr.

The etching speed of HBr polysilicon is 4000 people/
Etching selectivity with min SCMS resist is 4.
It is 5. Therefore, when over-etching the polysilicon layer 23 by 50%, the etching time is 90 seconds, but at this time, part a of the resist with a thickness of 670 mm is etched in about 45 seconds, and the remaining 45 mm The underlying polysilicon layer 23 is etched by 300 OA in seconds, leaving a polysilicon layer 23a with a thickness of 1000 Å. On the other hand, in the b part of the polysilicon layer 23, the upper resist is approximately 1
0.700 mm remains, and the polysilicon is not etched at all and remains at a thickness of 4000 Å. (Figure 1) Then, using the polysilicon gate electrode 23' in this state as a mask, As+ was applied 4X at an energy of 80 keV.
When ions are implanted at a dose of IO''/cffl, 4X1(]''/cffl are implanted under the outer side of the gate electrode 23' in the silicon substrate 21, forming high concentration source/drain regions 26,27, and forming the gate electrode 23'. Electrode 23'
4X1 which is 1% under part a of thickness 100OA
013/cIIl As+ is implanted to form lightly doped source/drain regions 28 and 29. Since the LDD structure provides a low concentration region in the drain region, the low concentration region does not need to be present in both the source region and the drain region, but is provided in both in practice.

Thereafter, an LDD structure MOS transistor is manufactured by a conventional method.

The LDD structure MOS transistor manufactured in this way, the LDD structure MOS transistor shown in FIG.
A stress test was conducted on three MOS (MOS) transistors with a single drain structure that does not have a DD structure, and the hot carrier resistance was compared. In addition, the effective gate length is 1.0
For stress, avalanche hot carriers are generated at a drain voltage of 6.5 V and a gate voltage of 3 V, and the ratio of the amount of change in channel conductance Δgm to the initial value gm of channel conductance is calculated as follows: It has hot carrier resistance. The results are shown in FIG. 3, and the LD of the present invention
It can be seen that the D structure has excellent hot carrier resistance.

〔Effect of the invention〕

As explained above, according to the present invention, an LDD structure having a gate electrode even on a low concentration layer can be formed with good controllability through simple steps. Furthermore, the LDD transistor of the present invention has improved hot carrier resistance.

[Brief explanation of drawings]

FIG. 1(A)-(1) is a schematic diagram showing the manufacturing process of an LDD transistor according to an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the remaining film thickness of the resist and the exposure amount, and FIG. Figures 4 and 5, which show the hot carrier resistance of various transistor structures, are schematic diagrams illustrating the manufacture of conventional LDD structure transistors. 21... Silicon substrate, 22... Gate oxide film, 23... Polysilicon layer, 23'... Gate electrode, 24... CMS resist, 26, 27... High concentration source/drain region ,28,
29...Low concentration source/drain region.

Claims (1)

[Claims] 1. Steps of forming a gate electrode layer on a semiconductor substrate and forming a resist layer on the gate electrode layer, and in-plane distribution of exposure amount for the resist layer at least in the gate formation region. It is exposed to light and developed to form a thick layer on the gate electrode body.
forming a thin resist pattern for forming a gate electrode at least at the end on the drain electrode side; etching the gate electrode layer using the resist pattern as a mask to form a gate electrode that is thick on the main body and thin at least at the end on the drain electrode side; ion implantation into the semiconductor substrate using the gate electrode as a mask to form heavily doped regions in the source/drain regions of the semiconductor substrate and lightly doped regions at least below the drain side end of the gate electrode; A method for manufacturing a field effect transistor, comprising the steps of: