JPS62143470A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a gate structure without damaging a substrate, by covering the ends of a projected channel region with a side wall layer before etching a layer of a gate electrode material in the plasma isotropic etching mode. CONSTITUTION:A p<->-type single crystal Si substrate 11 is treated to provide a projection in a region destinated to be a gate region. An n<->-layer 12 is then formed to cover the flat sections of the substrate and the ends of the gate region, while a side wall SiO2 film 14 is formed only on the ends of the gate region. After that, a gate SiO2 film 14 is formed on a channel region. Then, an Si layer 15 as a material for a gate electrode is formed. During this process, conditions are provided such that the step coverage of the ends of the projected gate region is T/2 or over and that the thickness T of the layer 15 is, at maxi mum, 1.5 times as large as the height of the projection. Subsequently, the layer 15 is highly doped with P and then patterned. As ions are implanted so that an n<+>-layer 17 is formed in the flat sections except the layer 13, for providing source and drain.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a MIS field effect transistor used in the manufacture of semiconductor devices, particularly MO8LSI memories.

[Background of the invention]

Megabit class highly integrated MO8LSI memory generally has a submicron gate electrode and a thin SI of ~100A, S degree.
MO8 field effect transistor (F
ET).

Traditionally, reactive ion etching (which has anisotropic etching characteristics) has been used to manufacture this type of MO8LSI.
Plasma etching called RIE is used. That is, a metal thin film such as tungsten or its silicide formed on the gate 5102 film is subjected to submicron photolithography and etched by RIE to form a submicron long gate region.

In this case, etching is performed by irradiating the wafer surface with positive ions in an etching gas plasma between the wafer of the negative electrode and the metal of the positive electrode. Between the wafer and the positive electrode,
A high frequency electric field is applied so that a high electric field is generated near the wafer. A high electric field near the wafer sweeps positive ions in the plasma onto the wafer surface, physically irradiating the electrode thin film on the wafer in a vertical direction.

By irradiating the wafer with ions in the vertical direction, etching is performed faithfully to the resist pattern, and the shift i. of the etching dimension from the resist dimension can be kept to 0.1 .mu.m or less. This indicates that the RIE etching mode is optimal for submicron microfabrication.

However, since RIE is a vertical ion irradiation mode, on the other hand, the ions are thin at the gate S10. It has the major drawback of passing through the film and causing crystal damage to the underlying silicon substrate. That is, in the early stage of etching, ions are irradiated to the electrode thin film, and the underlying gate 5io is irradiated with ions.
Although the Z film is not damaged, in the final stage of etching, the gate 810g film in the region to be etched is directly damaged by ion irradiation. In this case, gate 5
If the thickness of the ioz film is about 150 to 200 cA or more, the damage can be absorbed into the sin film.
Below ~150 Å, damage by ions penetrates through the film and extends to the surface of the underlying silicon substrate. Furthermore, this RIE damaged region is subjected to additional damage due to impurity ion doping in a post-process in order to be used as a source or drain region, and the thinner the 5int film is, the more susceptible it is to this effect. As a result, NPs formed on both ends of the gate 5iO7 film
This significantly deteriorates the characteristics of the junction and impairs its function as a memory.

Therefore, in a MOSFET having a thin Ga-Sift film of ~tooX, it is extremely inappropriate to etch a submicron-width gate electrode in the RIE mode because it is easily damaged by ion irradiation.

On the other hand, isotropic etching is performed by a chemical reaction between ions and the gate electrode material, and since no ion species are irradiated perpendicularly to the Sin1 film, the bulk S1 is not damaged by radiation.

However, isotropic ion etching is not suitable for submicron processing because of the so-called side etch effect in which the etching wavefront forms an arc centered on the edge of the mask, as is well known. Furthermore, since the source and drain regions of a MOS FET are formed by self-aligned ion implantation using the gate electrode as a mask, it is difficult to reduce the distance between the source and drain, or the so-called channel length, to submicron dimensions.

Note that as a technology related to the embodiments of the present invention described later,
Lightly doped drain (LDD)
international Electron Devi
ceaMeeting) Technical Digest pages 59-62.

[Purpose of the invention]

One object of the present invention is to provide a method for manufacturing a semiconductor device in which submicron processing for forming a gate electrode is realized by an isotropic etching mode instead of an RIE mode, and damage caused by RIE can be avoided. It is in.

[Summary of the invention]

According to one embodiment of the present invention, a semiconductor substrate in which a channel region is formed in a convex shape in advance is used, and after the end of the channel region is covered with a sidewall layer, a gate insulating film is formed on this substrate via a gate insulating film. Submicron length gate structures are formed by etching the gate electrode material layer in a plasma isotropic etch mode using a mask formed over the channel region.

According to another embodiment of the present invention, the end of the channel region formed in a convex shape is covered with a sidewall layer, and the surface of the substrate from the flat part to the end of the convex channel region is covered with a conductivity type opposite to that of the substrate. After forming the semiconductor region, the gate electrode material layer formed on the substrate with the gate insulating film interposed therebetween is etched in a plasma isotropic etching mode using a mask formed on the channel region to form a submicron-length etching layer. At the same time as the gate electrode is formed, ions are implanted into the flat part using the gate electrode as a mask to form a semiconductor region with a higher impurity concentration than the semiconductor region, thereby forming an LDD (Lightly Doped L) rain.
) structure source/drain regions are formed.

[Embodiments of the invention]

1 to 5 are process cross-sectional views schematically showing an embodiment of the present invention. First, a region of the P-type single crystal silicon substrate 11 that is to become a gate region (channel region) is processed into a convex shape by etching using a mask, although it is not shown in the figure. At this time, the width of the upper flat part gives the channel length, and accurate submicron photoetching is required. Next, from the flat part (lower part) of this substrate 11 to the end of the convex gate region, an N'''' layer 1
2, and a sidewall 810.2 is formed only at the end portion. Form layer 13. Thereafter, a gate 5iot film 14 is formed on the channel region. A similar SiO thin film is also formed on the flat part (lower part) (FIG. 1).

Here, the N layer 12 at the end of the gate region is a lightly doped drain (LLghtly) having an LDD structure.
The height H1 of the convex portion, the width W of the sidewall 5101 layer, and the slope of the end surface of the convex portion give the width of this N layer 12, and these values must be strictly controlled. There is. Here, in order to control isotropic etching which will be described later, it is formed to have a thickness of HzW (70.3 μm).

Next, the Po1Jsi layer 15 is applied as a gate electrode material by LPCV.
D (low pressure CVD) (as shown in Figure 2, at this time, the step coverage at the end of the convex gate region is T/2).
(50 staff) or above, and also Bo'JS.
The thickness T of the s-layer 15 is at most 1.5 times the height H of the convex portion.
Usually it is a smaller value.

Next, after doping the poly 81 layer 15 with a high concentration of υ by phosphorus treatment, a photoresist film 16 is formed on the convex portion IJss layer 15 by photolithography, and using this as a mask, the poly Si layer 15 is isotropically Patterning is done by etching. The etching wavefront advances from the position O in the figure to 1.2.3 and finally stops on the Sin region (FIG. 3).

In this case, the final etched wavefront of the poly 81 layer 15 needs to be above the sidewall 5IO1I 13, and the prerequisites for this are as described above,
The thickness T of the layer 15 is at most 1.5 times the height H of the convex portion, and its step coverage is 50 inches or more. In addition, T1
．． The final stage in the case of 5H is shown in FIG.

It is most desirable that the final etching wavefront of the poly-Si layer 15 is located just at the edge of the sidewall 8102 layer 13 as shown in FIG. Even if the overlap capacitance C0v is in the middle), the overlap capacitance C0v can be made sufficiently small by increasing the height H of the sidewall S102 layer 13, and does not significantly affect the high frequency characteristics.

Next, after removing the photoresist film 16, A8 ion implantation is performed to form an N layer 17 on the flat portion other than the sidewall 5101 layer 13 to serve as a source/drain.

At this time, A3 ions are also implanted into the upper part of the poly 5i 15 to form an N layer 15A, and a gate electrode of low resistance is further formed (FIG. 5).

As a result, an LDD structure with an N NP junction is obtained. Note that it is also possible to selectively deposit silicide of W or the like on the board 1Js1 layer 15 or the 8th layer 1T to reduce the resistance of the source/drain/and gate.

Furthermore, the above refractory metal silicide may be used instead of the poly 81 layer 150.

In this way, the convex gate region of height H is formed with a thickness T~1.
By depositing a 5H poly S1 layer and aligning the photoresist film formed thereon within 1.5H, it is possible to create an LDD structure MOS FET with a submicron channel length without creating an overlamp capacitance. and the NP junction is free from ion damage. In addition, the N layer 12 is formed in the vertical direction.
By arranging the N layer 17, the N layer 12, and the P channel region three-dimensionally, the area occupied by the device can be reduced compared to when they are arranged two-dimensionally.

Next, other embodiments of the present invention will be described in detail using FIGS. 6 to 14.

100% by thermal oxidation on the P-type single crystal Si substrate 21.
forming a film with a thickness T1 of ~200 mm;
500-800X depending on LPCvD
After forming a 5isN4 film with a thickness T2 of T2, submicron photoresist processing is performed on the region to become the gate channel region, and a pad 5102 with a submicron length of 1 is formed.
A film 22 and a 5lsNa film 23 are formed (FIG. 6).

Next, by LOCO8 thermal oxidation, a SiO2 film 24 having a thickness T3 of about 0.2 μm is entirely formed on the exposed surface of the substrate 21 (FIG. 7). This 5-inch film 24 is formed with approximately the same thickness T4 (~0.1 μm) above and inside the original substrate 21 centering on its surface. -tb, the total thickness of the SIO film 24 produced by Locus thermal oxidation is approximately twice the area of the substrate 21 ((), so the edge of the Sj s N4 film 23 is upward as shown in the figure). Bend.

Next, the 5IOt film 24 is removed by acid etching to create a submicron length (Ll) convex region with a height Hl of ~0.1 μm (~74). In this case, the height Hl can be controlled within five layers by adjusting the oxidation time for forming the LOCO85iCh film 24. Further, the slope θ of the end portion can be controlled with accuracy within 10 inches by adjusting the thickness T1 of the pad 5lOt film 22. In other words, these 5
If the tOt film 22 is thin, it is difficult for oxygen in the atmosphere to enter, and the above-mentioned end portions become sloped. Here, θ≧4
5°, and W1 to H1.

Next, phosphorus ions were used for 10~
10 pieces/(i implantation, one layer 25 of N is formed on the surface of the substrate 11 including the end face of the convex portion (FIG. 8).

Next, p s having a thickness comparable to the height of the convex portion on the entire surface
By depositing G In and then subjecting it to RIE, the sidewall PSG layer 2 buried between the curved SI3N4 film 23 and the inclined convex end face region is formed.
6 (Figure 9). At this time, the width W2 of the sidewall PSG layer 26 protruding from the S i s N4 film 23
can be controlled by the thickness of the PSG layer formed first. Here, it is assumed that W2≦0.05 μm.

Next, the Si, N4 film 23 is removed using hot phosphoric acid.
(Fig. A flat structure with approximately the same height as the flat region of the convex portion is formed (FIG. 11).

Next, gate oxide film 2T of ~100X is formed by gate oxidation.
, and further, a channel bee 12 layer 27 is formed by boron ion implantation (FIG. 12).

This ion implantation is performed at a concentration of about 1011♂vCnt. In other words, the phosphorus concentration is sufficiently low compared to the phosphorus concentration in the N layer 25, so you can use it without using a mask.
The N layer 25 never becomes P-type.

Next, a poly-Si layer with a thickness equal to or 1.5 times the convex height Hl is deposited on the entire surface by LPGVD, and after lowering the resistance by phosphorus treatment, this poly-Si layer is
Layer 29'' A multilayer resist film with a flattened upper surface was formed by a three-layer resist method in which an organic photoresist layer was placed on top of the spin-on glass layer and an organic photoresist layer was placed on top of the spin-on glass layer. Submicron photolithography is performed with alignment margin, and the multilayer resist film 30 is left on the convex portion.

Next, using this resist film 30 as a mask, the phosphorus-doped poly-Si layer 29 is etched in an isotropic etching mode. The etching wavefront at this time is shown by a broken line in the figure, and etching ultimately stops at point A in the figure in a self-aligned manner, suppressed by the wall of the sidewall 280 layer 26. On the other hand, in the BC region, it is regulated by the relationship between the film thickness and phosphorus concentration of the resist film 30 and the IJSi layer 29, and by appropriately setting these,
The isotropic etching surface can be stopped within the BC region (FIG. 13).

After removing the resist film 30 and the gate SiO2 film 27 on the source/drain regions, the poly S1 remaining on the source/drain regions and the gate region is removed by selective CVO.
By depositing a W layer 31 on top of the layer 29 and implanting As ions at a high concentration thereon, eight layers 32 are formed as low-resistance source/drain regions, and eight layers 32 are formed in the gate region. An N+W- silicide layer 33 is formed (FIG. 14).

〔Effect of the invention〕

As explained above, according to the present invention, after covering the end portion of the channel region formed in a convex shape with a sidewall layer, a gate electrode material layer formed on this substrate via a gate insulating film is applied to the channel region. By etching in plasma isotropic etching mode using the mask formed above, submicron long gate structures can be formed without damaging the substrate.

Furthermore, in the above process, the end of the channel region is covered with a sidewall layer, and a semiconductor region of the opposite conductivity type to that of the substrate is formed on the substrate surface from the flat part to the end of the channel region. A source/drain region having an LDD structure is obtained by implanting ions of the opposite conductivity type into the flat portion at a high concentration using the electrode as a mask. Moreover, in this case, since the lightly doped drain region is arranged in the vertical direction, the area occupied by the device can be reduced.

[Brief explanation of drawings]

1 to 5 are process cross-sectional views showing one embodiment of the present invention, and FIGS. 6 to 14 are process cross-sectional views showing other embodiments of the present invention. 11.21...P-type single crystal silicon substrate, 12.2
5...N single layer (first semiconductor region), 13...
Sidewall 5iOl return, 14, 27... game)
SiO1 film, 15, 29...poly-Si layer, 16.3
0...Resist film (mask), 17.32...
N layer, 2V...280 layers of sidewall. Agent: Patent Attorney Katsuo Ogawa! “ Figure 7 Figure 8 Figure 11

Claims (1)

[Claims] 1. A step of covering the end portion of the channel region of a semiconductor substrate in which a channel region is previously formed in a convex shape with a sidewall layer;
A step of forming a gate electrode material layer that can be selectively etched with respect to the sidewall layer and the gate insulating film on this semiconductor substrate via a gate insulating film, and a mask formed on the gate electrode material layer on the channel region. forming a gate electrode by etching the gate electrode material layer in a plasma isotropic etching mode. 2. Covering the end of the channel region of the semiconductor substrate of the first conductivity type in which the channel region has been formed in a convex shape in advance with a sidewall layer, and forming a second layer on the surface of the semiconductor substrate from the flat part to the end of the convex channel region. a step of forming a first conductive type semiconductor region; and a step of forming a gate electrode material layer on the semiconductor substrate via a gate insulating film, which can be selectively etched with respect to the sidewall layer and the gate insulating film. , forming a gate electrode by etching the gate electrode material layer in a plasma isotropic etching mode using a mask formed on the gate electrode material layer on the channel region, and by ion implantation using the gate electrode as a mask. A method of manufacturing a semiconductor device including at least the step of forming a second semiconductor region of a second conductivity type having a higher impurity concentration than the first semiconductor region on a flat surface of the semiconductor substrate.