JPH04171828A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE:To erect a GOLD structure in excellent film thickness controllability by a method wherein the second polysilicon film to be the overlapped part of a gate electrode is formed by CVD process. CONSTITUTION:Firstly, a gate oxide film 12 is formed on a substrate 1 and then the first polysilicon film 13 is formed on the film 12. Later, a resist pattern 14 is formed on the gate electrode position on the first polysilicon film 13 and then etched away taking an inverse mesa shape so as to form another polysilicon film 13a. Next, after the removal of the resist pattern 14, an N<-> source.drain layer 15 are formed using the polysilicon film 13a as a mask taking the shape as if creeping in the polysilicon film 13a to the side ends B beneath the inverse mesa type polysilicon film 13a. Next, after the formation of the second polysilicon film 16 500Angstrom thick by LPCVD process on the whole surface of the substrate 11, an oxide film 17 4000Angstrom thick is formed also by CVD process on the whole surface of the second polysilicon film 16. Later, the oxide film 17 and the second polysilicon film 16 are etched away using RIE process.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to MoS transistors, particularly GOL D (Gate-
Drain 0verlapped LDD) structure M
The present invention relates to a method for manufacturing an OS transistor.

(Prior Art) In a MOS transistor, when the device is downsized and the gate length becomes 1.5n or less, characteristics deteriorate due to hot carriers. Therefore, in order to prevent this characteristic deterioration, a method has been proposed in which a low concentration N- offset layer is provided between the high concentration N drain and the P layer below the gate. D (Lightly
This is called a doped drain structure.

However, the device was further reduced in size and the gate length was reduced to 0.8n.
Below this, characteristic deterioration due to hot carriers is observed even in this LDD structure.

Therefore, GOLD (Gate-
Drain 0verlapped LDD) structure is a structure that can avoid the above problems.
38 to P41, and good results have been obtained.

A conventional manufacturing method (disclosed in the above-mentioned document) of the GOLD structure MOS) run lister is shown in FIG. 2 and will be described below.

First, as shown in FIG. 2(a), a P-type (100) substrate 1
After growing a gate oxide layer 112 with a thickness of 150λ on the surface of
Make people grow. After exposing the first polysilicon 3 to the air to grow 5 to 10 natural oxide films 4 on the surface, a second polysilicon 5 and a CV D 3iOz film 6 are sequentially grown on the top to form a CV D 3iOz film. 6 is the well-known photolithography
It is patterned using etching technology and left only at the gate electrode position.

Next, the second polysilicon 5 is etched by dry etching with a high selectivity using the CVD 3iOz film 6 as a mask, as shown in FIG. 2(b). At this time, the natural oxide film 4 acts as an etching stopper, and the first
Polysilicon 3 remains without being etched. After that, using the CV DSiO□ film 6 as a mask, a voltage of 80 keV was applied.
Phosphorus is ion-implanted with an energy of
A source/drain layer 7 is formed.

Next, by growing a CV DSiO film over the entire surface and etching it by RIE, a side wall 8 of a 5lOt film is formed around the CV DSiO film 6 and the second polysilicon 5 as shown in FIG. 2(C). obtain.

After that, CV D 5iOz film 6 and sidewall 8
Using this as a mask, the first polysilicon 3 is patterned as shown in FIG. 2(C).

After that, S E L OCOS (5elective
Oxicle coating of 5ilicon
gate), the side edges of the first polysilicon 3 are converted into an oxide film 9 as shown in FIG. 2(d) under wet oxidation conditions of 800°C. By concretizing this oxidation, the overlap length of the gate electrode (first polysilicon 3) to the drain layer is controlled.

Finally, CV D 5ins film 6 and sidewall 8
Using the mask as a mask, As is ion-implanted to form a N source/drain layer 10 in the substrate 1 as shown in FIG. 2(b).

In this way, the GOLD structure MO5) run lister is completed.

(Problem B to be solved by the invention) However, the conventional manufacturing method as described above has the following problems.

(1) When etching the second polysilicon 5 shown in FIG. 2(b), it is difficult to rtim the stopper oxide film 4 of 5 to 10 layers so that the first polysilicon 3 is not etched. , the said document contains the second
Although the film thickness of the polysilicon 5 is not disclosed, the polysilicon film thickness of the gate electrode is usually 3000 to 4000.
Since a person is used, the film thickness of the second polysilicon 5 is 250 by subtracting the film thickness of the first polysilicon 3, which is 500.
It is estimated that there are 0 to 3,500 people. On the other hand, the oxide film 4 of the stopper is said to have a thickness of 5 to 10. Therefore, during the second polysilicon etching, the selection ratio of polysilicon/oxide film is 2,500/10 to 3,500, that is, 25
A value of 0 to 700 times is required. It is difficult to obtain a dry etching device with such a selectivity ratio, and as a result, the residual film thickness of the first polysilicon 3 varies within the wafer, making it difficult to obtain a predetermined gate overlap dimension and film thickness uniformly within the wafer. The problem arises that it is not possible to If wet etching with a high selectivity is used, since wet etching is generally isotropic etching, 25
In order to etch the second polysilicon 5 with a thickness of 0.00 mm, the side etching amount (lateral etching amount) is also 2.5 mm.
00 people and this side etching is shown in Figure 2 (C of BL).
Since the same amount is generated from both sides of the V D 5iOz film 6, the total number is 5,000, making it impossible to leave the desired second polysilicon width. Now, CV D 5
If iOill 6 is formed with a photolithography minimum resolution dimension of 0.51 nA, and the second polysilicon 5 is etched using it as a mask, and the side etching amount at that time is 2500, the remaining second polysilicon width is 0.5 - (0,2
5×2)=On, and the second polysilicon 5 no longer remains.

(2) If the stopper oxide film 4 is made thicker in order to facilitate the control of the above (]), the first
Polysilicon 3 and second polysilicon 5 will be insulated, and even if they are not insulated, the resistance value of the gate electrode will increase.

(3) In FIG. 2(d), the N-source/drain layer 7 is C
Although the VD5iO□ film 6 is penetrated into the inside, normally the edge of this CV DSiO□ film and the N- source/drain layer 7
The inner ends of the CVDSing film 6 are located at the same position, and the N- source/drain layer 7 is formed outside the end of the CVDSing film 6. Therefore, now CV DSiO □ film 6) +J
If the gate electrode is formed with the minimum photolithographic resolution dimension and is formed so as to overlap the N-source/drain layer 7 located outside the gate electrode, the gate electrode will be considerably larger than the photolithographic resolution dimension, making it difficult to integrate the device. This results in hindering the improvement of performance.

This invention was made in view of the above points, and it is possible to reduce the gate electrode width, reduce the resistance value of the gate electrode, and improve film thickness controllability.
An object of the present invention is to provide a method for manufacturing a MOS (MOS) run lister that can obtain a structure.

(Means for Solving the Problems) The present invention provides a method for manufacturing a run lister (OLD structure MO5) in which a first polysilicon film serving as a gate electrode is formed in an inverted trapezoidal shape, and the gate electrode extends to the lower side edge of the first polysilicon film. A low concentration source/drain layer is formed inside the layer, and a second polysilicon film which becomes an overlapping portion of the gate electrode is formed thereon by CVD.

(Function) In the above-mentioned invention, when forming a thin polysilicon film that will become the overlap part of the gate electrode, a uniform thin polysilicon film (second polysilicon film) is formed using the CVD method instead of the conventional thin etching method. Since the method of forming a silicon film is used, the gate electrode overlap portion can be formed with good film thickness controllability.

Further, since the gate electrode is formed without including an oxide film for an etching stopper, the resistance value of the gate electrode is small and there is no variation.

In addition, the first polysilicon film serving as the gate electrode is formed in an inverted trapezoidal shape, and the low concentration source/drain layer is formed by penetrating inside the gate electrode up to the lower side edge of the first polysilicon film.
The width of the gate electrode including the overlap portion becomes smaller than that of the conventional method by the amount of intrusion.

(Example) An example of the present invention will be described below with reference to FIGS. 1(a) to (e).

First, as shown in Figure 1(a), the specific resistance is 1~2Ω・1
A 200-layer thick gate oxide film 12 is formed on a P-type (100) substrate 11 by oxidation for about 30 minutes in a wet atmosphere at 850°C.
A first polysilicon film 13 having a thickness of 0.00 mm is formed. Thereafter, phosphorus is diffused into the first polysilicon film 13 at 900[deg.] C. to a phosphorus concentration of 6.times.10"C11-" to I.times.10"CI-".

Next, using a known photolithography technique, the gate electrode position on the first polysilicon film 13 is deposited with a minimum photolithographic resolution of 0.5n.
Using the resist pattern 14 as a mask, a pressure crab 12 (1+
Torr, power: 10OW, gas: sulfur hexafluoride (SF4) + Freon 114 (CtCfzF-), the first polysilicon film 13 is etched into an inverted trapezoidal shape as shown in FIG. 1(b). do.

After this etching, the inverted trapezoidal first polysilicon film 13 remaining under the resist pattern 14 as a gate electrode is referred to as a polysilicon film 13a.

Next, after removing the resistor pattern 14, the polysilicon film 1
Arsenic is implanted into the substrate 11 at an accelerating voltage of 30 keV and a dose of 2×10 "CI-" using known ion implantation technology using 3a as a mask, so that arsenic is implanted into the substrate 11 as shown in FIG. 1(C). An N- source/drain layer 15 is formed thereon. At this time, by tilting the substrate 11 by 8 degrees to 10 degrees from the vertical direction and implanting ions while rotating the substrate 11, polysilicon is formed up to the lower side edge B of the inverted trapezoidal polysilicon film 13a. An N- source/drain layer 15 is formed so as to penetrate inside II 13a. In this embodiment, the difference C between the lengths of the upper side edge A and the lower side edge B of the polysilicon film 13a serving as the gate electrode is 0. Since it is formed to be In, the N- source/drain layer 1
5 is 0.5 from the upper side edge A of the polysilicon film 13a. In
It will enter inside the polysilicon l1113a (gate electrode).

Next, the entire surface of the substrate 11 is covered with LP as shown in FIG.
A second polysilicon film 16 having a thickness of 500 mm is formed using the CVD method. At this time, according to the inventor's experiment, the variation in the second polysilicon film thickness was controlled with high accuracy to less than ±5% (±3% to ±5%), that is, less than 125 Å. Phosphorus in the silicon film 16 at 900°C with a phosphorus concentration of 6×10
It is diffused so that it becomes ``CI-'' ~ 1×10 ``CI-''. After that, CVD is applied to the entire surface of the second polysilicon film 16.
Oxide #17 is formed to a thickness of 4,000 by the method.

Thereafter, by etching the oxide film 17 and the second polysilicon film 16 using the R2H method, the overlamp portion 16a of the gate electrode made of the remaining second polysilicon film is etched as shown in FIG. 1(e). A sidewall 17a formed on the surface of the N- source/drain layer 15 and made of the remaining oxide film 17 is formed on the sidewall portion of the polysilicon film 13a.

After that, although not shown, the side edges of the overlamp portion 16a are oxidized in the 5ELOCO5 step in the same manner as in the conventional method.
Furthermore, N゛ source/drain layer is placed on the sidewall 17.
a GOLD by forming it in the outer substrate 11 by ion implantation method
Completed the structure Mos transistor.

(Effects of the Invention) As described in detail above, according to the present invention, when forming a thin polysilicon film that will become the overlap part of a gate electrode, it is possible to use a thin polysilicon film that has variations of 5% to 10% within a wafer. Because we used a CVD method with a variation of less than 5% (3% to 5%) instead of an etching removal method,
Gate electrode overlap portions can be formed with good film thickness side gate properties, making it possible to form elements with high precision.

Furthermore, since the gate electrode is formed without including an oxide film for etching stopper, the resistance value of the gate electrode can be reduced and there is no variation.

In addition, the first polysilicon film serving as the gate electrode was formed in an inverted trapezoidal shape, and the low concentration source/drain layer was formed by penetrating inside the gate electrode up to the lower side edge, so the overlap was increased by the amount of penetration. The width of the gate electrode, including the width of the gate electrode, can be made smaller than that of the conventional method. Now, assuming that the gate electrode is formed with a photolithography minimum resolution dimension of 0.5μ,
In the conventional technology, the gate electrode width including the overlap part is 1.3n, but in this invention, the width of the gate electrode is 1.3n.
Since the drain layer extends 0.1n inside the gate electrode (first polysilicon film), the width of the gate electrode including the overlap portion is 1.1n, and the electrode width can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing an embodiment of the method for manufacturing a MOS transistor according to the present invention, and FIG.
FIG. 3 is a process cross-sectional view showing a method of manufacturing a D411 MOS transistor. DESCRIPTION OF SYMBOLS 11... P type (100) substrate, 12... Gate oxide film, 13... First polysilicon film, 13a... Inverted trapezoidal polysilicon film, 14... Resist pattern, 1
5... N- source/drain layer, 16... second polysilicon film, 16a... gate electrode overlap portion, 17... oxide film, 17a... side wall. 13. First silicon film TTP type (+00) substrate An embodiment of the present invention I? σ Sidewall An embodiment of the present invention FIG. 1

Claims (1)

[Claims] A gate oxide film is formed on a semiconductor substrate, and a first
a step of forming a polysilicon film; a step of patterning the first polysilicon film into an inverted trapezoid shape as a gate electrode; After that, a second polysilicon film is formed on the entire surface of the substrate by the CVD method, and an oxide film is formed on top of it. By etching using a directional etching method, an overlapping portion of the gate electrode is formed using the remaining second polysilicon film on the surface of the low concentration source/drain layer, and an overlapping portion of the gate electrode is formed on the sidewall portion of the inverted trapezoidal first polysilicon film. A method of manufacturing a MOS transistor comprising the steps of forming a sidewall with a residual oxide film, and forming a highly doped source/drain layer in a substrate outside the sidewall.