JPH0311626A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable accurate control of the film thickness of a lateral-wall spacer by a method wherein an ion-impermeable film to be the spacer is deposited only on one side to be the drain side of a gate electrode by a Langmuir-Blodgett(LB) method and ion implantation is conducted with this film used as a mask. CONSTITUTION:A polymethyl methacrylate (PMMA) monomolecular film 7 is formed by developing PMMA dissolved in benzene on the surface of pure water 6, and this film is transferred onto the surface of the drain side of a polycrystalline silicon layer 3 and a photoresist layer 4 of an MOS gate pattern of a semiconductor substrate 1 by the LB method. On the occasion, the transition surface of the semiconductor substrate 1 is moved vertically with an angle of 85 deg. to 90 deg. maintained to the water surface, and thereby the PMMA monomolecular film 7 is deposited, so that a PMMA film 8 having a film thickness of about 700 A be formed. The film thickness of the PMMA film 8 can be controlled for angstrom (A) by the number of times of deposition of the PMMA monomolecular film 7. According to this method, the film thickness of an ion impermeable film formed on one side of a gate electrode is controlled very accurately.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor substrate, and more specifically, a method for manufacturing a semiconductor device including a method of implanting impurities into selective regions by ion implantation. This relates to a manufacturing method.

(Prior Art) In semiconductor devices, especially MOS transistors whose minimum dimensions have become sub-micron standard due to progress in miniaturization, hot carriers generated in the high electric field region near the drain region can cause damage to the semiconductor device. This has become a cause of increased instability, often causing fluctuations in the threshold voltage of MOS transistors and reductions in mutual conductance. A typical measure for relaxing the drain electric field is a so-called low concentration diffusion drain (hereinafter referred to as LDD) structure. In this LDD structure, the low concentration (n-) diffusion region lowers the effective drain voltage.

The conventional manufacturing method for a MOS transistor having this type of LDD structure is to first form a gate electrode on a silicon substrate, and then use this as a mask to implant arsenic (As) ions to form a low concentration (n-) diffusion region. Then, spacers made of silicon dioxide (SxOz) were formed on the side walls of the gate electrode using chemical vapor deposition (hereinafter referred to as CVD) and reactive ion etching (hereinafter referred to as RIE). After that, the gate electrode was formed using phosphorus (P) using the spacer as a mask.
) was ion-implanted to form a high concentration (n9) diffusion region.

(Problems to be Solved by the Invention) However, in the conventional manufacturing method, the CVD method, which is essential for forming the sidewall spacer of the gate electrode, has a problem in that it is difficult to accurately control the film thickness.

The present invention solves the above-mentioned problems and provides a method for manufacturing a semiconductor device in which the thickness of a sidewall spacer can be accurately controlled.

(Means for Solving the Problems) In order to solve the above problems, the present invention uses the Langmuir-Prodgett (hereinafter referred to as LB) method on only one side of the gate electrode, which is the drain side, to form ions that will become spacers. After depositing an impermeable film and performing ion implantation using this as a mask, the ion-impermeable film is removed.

(Function) With the above configuration, the thickness of the ion-impermeable film formed on one side of the gate electrode can be controlled extremely accurately, so a MOS transistor can be obtained that has the characteristics as designed in the mask process using the self-line method. It will be done.

(Example) An example of the present invention will be described with reference to FIGS. 1(a) to d) and FIG.

FIGS. 1(a) to d) are enlarged cross-sectional views of main parts showing the manufacturing method of a semiconductor device according to the present invention in the order of steps, and FIG. 2 is an L
FIG. 3 is a cross-sectional view of the step of depositing an ion-impermeable film using Method B.

First, on the surface of a p-type semiconductor substrate 1, a silicon dioxide film 2 with a thickness of about 4000 thick, which will serve as a gate insulating film, and a polycrystalline silicon layer 3, with a thickness of about 4000 thick, which will serve as a gate electrode, are formed in a laminated manner. On top of that, the film thickness is approximately 1.2μ by spin coating method.
After forming a positive photoresist layer 4 of m, a desired MOS gate electrode pattern is formed using photolithography technology, and the polycrystalline silicon layer 3 is etched using this as a mask to form a desired MOS gate electrode pattern 34. A polycrystalline silicon layer 3 with turns is formed. Subsequently, arsenic (As) is implanted by an ion implantation method to form an arsenic ion implantation region 5 (FIG. 1(a)). At this time, the amount of arsenic ions implanted is about 1014 to 10"/1ffl, and the arsenic ion implanted region 5 is at a low concentration (
n-) Set to become a diffusion layer.

Next, as shown in FIG. 2, polymethyl methacrylate (hereinafter referred to as PMMA) dissolved in benzene is spread on the surface of the pure water 6 to form a PMMA monomolecular film 7, and this is LB.
The MOS gate pattern of the semiconductor substrate 1 is transferred to the drain-side surfaces of the polycrystalline silicon layer 3 and the photoresist layer 4 by a method. In this case, the transition surface of the semiconductor substrate 1 is raised and lowered at an angle of 85° to 90° with respect to the water surface, and the
MMA monomolecular film 7 is accumulated, and the PMMA film thickness is approximately 700.
A film 8 is formed (FIG. 1(b)). In addition, the above PMM
The thickness of the A-film 8 can be controlled in angstrom units by the cumulative number of times the PMMA monomolecular film 7 is applied.

Next, anisotropic etching is performed using the RIE method, leaving the PMMA film 8 only on the sidewalls of the polycrystalline silicon layer 3 and the photoresist layer 4 on the drain side. Using 8 as a mask, phosphorus (P) is implanted by an ion implantation method to form a phosphorus ion implantation region 9 (FIG. 1(C)).

At this time, the amount of phosphorus ions implanted is 1015 to 1016
/d, and the phosphorus ion implantation region 9 is set to become a high concentration (n+) diffusion layer after the diffusion heat treatment.

Next, after removing the photoresist layer 4 and the PMMA film 8 by ashing, a diffusion heat treatment is performed at a temperature of 900°C for about 30 minutes, and as shown in FIG. 1(d), a self-line mask process is completed. High concentration (n+) diffusion region 1
An n-type diffusion region 10 is formed having a low concentration (n-) diffusion region 10a and a low concentration (n-) diffusion region 10b.

In this example, the silicon dioxide film 2 was used as the gate insulating film, but a silicon nitride film may also be used.
The material for the gate electrode is not limited to polycrystalline silicon, but any electrode material that can be used in the self-line method, such as high melting point metals or their silicides, can be used. In addition, although PMMA was used as the material for the ion-impermeable membrane formed by the LB method, it was also possible to obtain a monomolecular membrane by developing it on pure water with a methacrylic acid-based or acrylic acid-based material that does not contain metal ions. Any polymer that can be used as an ion-impermeable membrane can be used.

(Effects of the Invention) As explained above, according to the present invention, an ion-impermeable film with precisely controlled film thickness can be formed on the side wall of the gate electrode on the drain side by using LB@. A method for manufacturing a semiconductor device that can stably obtain a MOS transistor with the set characteristics using the mask process according to the method becomes possible.

[Brief explanation of the drawing]

1(a) to 1(d) are enlarged cross-sectional views of essential parts showing the method of manufacturing a semiconductor device according to the present invention in order of steps, and FIG. 2 is a cross-sectional view showing a step of forming an ion-impermeable film using the LB method. 1...p-type semiconductor substrate, 2... silicon dioxide film,
3... Polycrystalline silicon layer, 4... Photoresist layer, 5... Arsenic ion implantation region, 6... Pure water,
7... PMMA monomolecular film, 8... PMMA membrane (ion-impermeable membrane), 9... phosphorus ion implantation region, 1
o: n-type diffusion region, 10a: high concentration (n+) diffusion region, 10b: low concentration (n-) diffusion region.

Claims (2)

[Claims] (1) A step of forming a gate electrode on a semiconductor substrate, and a step of forming a gate electrode on a semiconductor substrate;
A process of ion-implanting impurities, a process of depositing an ion-impermeable film using the Langmuir-Prodgett method except for one side of the gate electrode, and a process of depositing an ion-impermeable film on the side wall of the gate electrode using a reactive ion etching method. A method for manufacturing a semiconductor device, comprising: leaving an ion-impermeable film; ion-implanting a second impurity into the semiconductor substrate; and removing the ion-impermeable film. (2) The method for manufacturing a semiconductor device according to claim (1), wherein in the step of depositing the ion-impermeable film by the Langmuir-Prodgett method, the angle between the semiconductor substrate surface and the water surface is 90° or less.