436903 五、發明說明（1) 發明之背景： (1 )發明之技術領域 本發明係有關於積體φΜ ,^ 士狀冰 接田於接搞Φ 電路元件的製造’且更特別地疋 有關於一種用於積體電路劁 ^ . 我造中形成平滑閘極多晶矽侧壁 之万法 β (2 )習知技藝之說明 〇 微影成像術及蝕刻法通常用於 區域性氧化矽（LOCOS)、淺溝槽隔 在積體電路的製造中 形成諸如多晶矽閘極 絕層（STI)及其它相似等—結^怔氣化矽（LOCOS)、淺溝檟閛 將來是被蝕刻掉，光阻穿、構，光阻材料係被塗覆一廣’ 顯影而形成光阻幕罩，過'"幕罩而曝露在光化光’然後 多晶矽通常做為金 $钱刻基礎層或其它層。 ，具有圖案的多晶石夕之$氣化物電晶體（M0S)的閘極電極 ，該圖案係由光阻幕罩離子钱刻（RIE)製造出閘極電極 經過蝕刻之後，吝曰定義出來的。使用現今的技術， 係由在蝕刻時多晶矽社曰側壁係呈粗糙不平的’該粗糙度 变幾何裝[晶粒尺：：體的晶粒尺寸而決定，針對超小 後，此可能導致不良吝要與裝置線寬相配合’在蝕 ^ m ^ ^ 不良多晶矽臨界尺寸（CD)配置，且依序地 了由於缺+曰制’如啟始電壓（V t)及漏極飽和電流（1 dast) '、'晶粒’用於閘極材質而取代多晶矽的非晶矽， 會，成，平滑的侧壁，然、而此方法會產生—非預期多晶 碎二泛效應的增加’且會造成較高閘極氧化物電容及較高 閾電壓。436903 V. Description of the invention (1) Background of the invention: (1) Technical field of the invention The present invention relates to the integration of φM, ^ ice-shaped ice field to the manufacture of Φ circuit elements, and more particularly to the A kind of integrated circuit used in integrated circuits 劁 ^. A description of the know-how β (2) of conventional techniques for forming smooth gate polysilicon sidewalls. Lithography and etching are commonly used for localized silicon oxide (LOCOS), Shallow trenches are formed in the fabrication of integrated circuits, such as polycrystalline silicon gate insulators (STIs) and other similar ones—junction silicon dioxide (LOCOS), shallow trenches will be etched away in the future, light blocking, The photoresist material is coated and developed to form a photoresist curtain cover. After the curtain cover is exposed to actinic light, polycrystalline silicon is usually used as the base layer or other layer of gold. The gate electrode of polycrystalline stone gas oxide transistor (M0S) with a pattern. The pattern is made of a photoresist screen ion ion engraving (RIE). After etching, the gate electrode is defined as follows: . Using today's technology, it is determined that the sidewalls of polycrystalline silicon are rough at the time of etching. The roughness becomes geometrical [grain rule :: the grain size of the body. For ultra-small, this may lead to bad results. Must match the device line width 'in the etch ^ m ^ ^ bad polycrystalline silicon critical dimension (CD) configuration, and sequentially due to lack of + system, such as the initial voltage (V t) and drain saturation current (1 dast ) ',' Crystal 'is used for the gate material instead of polycrystalline silicon, which will result in smooth sidewalls. However, this method will produce-an unexpected increase in polycrystalline fragmentation's two panning effect' and will Causes higher gate oxide capacitance and higher threshold voltage.
Llu於美國專利第5, 393, 682號揭露出一種破壞多晶矽Llu in U.S. Patent No. 5,393,682 reveals a type of polycrystalline silicon
第5頁 436908^ 五、發明說明^ ----- 本發明之製程可用於最小空泛效應的各種應用上，而 可預，達到平滑閘極懸及小特徵尺寸肖製程可用於形 成位，予線、多晶矽閘極電極、及其相似物。第1圖至 第5圈係顯示本發明製程以製造一具有平滑側壁之閘極電 極，如本技藝所熟知，本發明製程可用於形成結構的光刻 及蝕f的各種應用上，及所需小特徵尺寸的應用上。 請參閱第1囷，係顯示—半導體基板1() ’ 一閘極氧 化石夕1 2係被形成在基板的表面上，該閘極氧化矽1 2係 由一厚度10至1 5 0埃的氧化矽所組合而成，在介於約7 〇 〇到 9 0 0°C的溫度，藉由乾式或部份濕式氧化及NH4/n2〇回火而 長成閘極氧化矽1 2 ’或在介於約4 0 0到1 〇 0 0°C的溫度， 藉由RT0 (快速氧化）沉積或長成，沉積厚度約為2〇〇至5000 埃的閘極電極14可由多晶矽或多晶矽鍺所組合而成。 氧化，碎1 6的罩幕層係被沉積覆蓋多晶矽或多晶矽鍺 層至一厚度介於5 0 0到3 0 0 0埃。 光阻層1 8係被塗抹在氧化矽1 6上，光刻掩膜（未 顯示）係被設置於晶圓上，且使用光化光而暴露光阻材料 、例如使用〗線微影成像，光阻係被顯影而留下一光阻罩 幕20 ，如第2圖所示。 請參閱第3圖，未受光阻罩幕保護的部份罩幕層被蚀 刻移去，且光阻罩幕係藉由習用的方法而被移除。 請參閱第4圖，離子2 4被植入到未被罩幕層1 6覆 蓋的多晶矽層14，被植入的離子可包含矽、鍺、砷、亞 磷、硼、或四氟化硼（BF 4)，此會產生受非晶化多晶矽2Page 5 436908 ^ V. Description of the invention ^ ----- The process of the present invention can be used in various applications with minimal flooding effects, and it is predictable that smooth gate suspension and small feature sizes can be achieved. Wire, polycrystalline silicon gate electrode, and the like. Figures 1 to 5 show the process of the present invention to fabricate a gate electrode with smooth sidewalls. As is well known in the art, the process of the present invention can be used for various applications of photolithography and etching to form structures, and the required For small feature sizes. Please refer to the first display. The semiconductor substrate 1 () ′ A gate oxide stone 12 is formed on the surface of the substrate, and the gate silicon oxide 12 is composed of a thickness of 10 to 150 angstroms. It is a combination of silicon oxide, and grows into gate silicon oxide 1 2 'or by dry or partial wet oxidation and NH4 / n2 tempering at a temperature between about 7000 to 900 ° C. At a temperature of about 400 to 1000 ° C, the gate electrode 14 is deposited or grown by RT0 (rapid oxidation) to a thickness of about 200 to 5000 angstroms, and can be made of polycrystalline silicon or polycrystalline silicon germanium. Combined. The oxidized and broken 16 mask layer is deposited to cover the polycrystalline silicon or polycrystalline silicon germanium layer to a thickness of 500 to 300 angstroms. The photoresist layer 18 is coated on the silicon oxide 16 and a photolithographic mask (not shown) is placed on the wafer and exposed to the photoresist material using actinic light, such as imaging using line lithography, The photoresist is developed to leave a photoresist mask 20, as shown in FIG. Referring to Figure 3, the part of the mask layer that is not protected by the photoresist mask is etched and removed, and the photoresist mask is removed by conventional methods. Referring to FIG. 4, ions 24 are implanted into the polycrystalline silicon layer 14 that is not covered by the mask layer 16. The implanted ions may include silicon, germanium, arsenic, phosphorous, boron, or boron tetrafluoride (BF 4), which will be affected by amorphous polycrystalline silicon 2
第8頁 4§ΒΒ^Ϊ9 ^ 五、發明說明（3) 係被覆蓋在光阻層上，使用微影成像製程而將光阻圖案化 ，而提供一用於閘極電極的形成之光阻罩幕，光阻罩幕及 罩幕氧化層垂直地被蝕刻而形成一用於閘極電極的罩幕， 一矽或鍺的離子植入將未被罩幕氧化層覆蓋的多晶矽區而 非晶化，由於離子植入的橫向擴散，且將在罩幕氧化層邊 緣下方的多晶矽的一部份非晶化，此後，受非晶化矽藉由 一習用的各向異性乾式蝕刻法而被移除，而留下一受非晶 化矽的狹窄區於閘極電極的側壁上，且在罩幕氧化層邊緣 下方。 在形成本專利說明書之材料部分的附圖中，其係表示 〆 圖 號之簡 要 說 明 1 0 半 導 體 基 板 1 2 閘 極 氧 化 矽 1 4 閘 極 電 極 1 6 氧 化 矽 罩 幕 層 1 8 光 阻 層 2 0 光 阻 罩 幕 2 4 離 子 2 6 受 非 晶 化 多 晶 矽 3 0 受 非 晶 化 多 晶 矽 3 2 源 極 及 汲 極 區 3 4 内 介 電 層 較 佳實施 例 之 細 節 說 明 ΙΗΗ 第7頁 4 3㈣g f 圊式簡單說明 第1圖至第5圖係為本發明一較佳實施例之橫剖面示意圖 〇 第6圖係為利用本發明製程而完成積體電路元件之橫剖面 示意圖。 43 69 08 i 五、發明說明（5) 6的一區。例如，在厚度為2 0 0 0埃的多晶矽層1 4上，在 能量3 0到5 0千電子伏特（K e V )且具有劑量8 E1 4到 5E15atoms/cm的一第一矽植入可被完成，接著完成60到 80KeV且具有劑量8E14到5E15atoms/cm的一第二妙植入， 然後90到1 20KeV且具有劑量8e 1 4到5E15atoms/cin的一第 三矽植入會被完成。若鍺離子被植入，所有植入的植入劑 量為5E14到5E15atoms/cm2，且具有能階範圍50到80KeV、 100到17 0KeV、及100到270KeV，分別為第一、第二、及第 三植入。上述的例子僅用於做說明，且植入能量的次序並 非關鍵的’用於植入序列的能階可被調整，以便受保護深 度可覆蓋於多晶矽層的整個厚度，最好，應使用至少兩個 能量分佈，此製程會非晶化閘極的整個側壁，由一短距離 而穿過橫向擴散至多晶矽層14且在軍幕層16邊緣下方 ’此會在已完成閘極上形成平滑側邊，當避免出現非預期 的空泛效應。 請參閱第5圓，未被罩幕層1 6覆蓋的受非晶化多晶 矽區2 6可藉由各向異性乾式姓刻而被移除，而留下受非 晶化多晶矽3 0的小區域，且沿著閘極邊緣旁，此蝕刻會 與終點偵測而被完成，該終點偵測之後，接著為約1 〇到 1505¾間的過度蝕刻，罩幕層1 6可藉由習用的方法而被移 除。 請參閱第6圖，連續製程如習用技藝，若如圖示所述 ’閘極電極可由本發明的製程而被製造出來，源極及汲極 區3 2可被形成，而沉精内介電層3 4且完成電接觸窗（Page 8 4§ ΒΒ ^ Ϊ9 ^ V. Description of the invention (3) The photoresist is covered on the photoresist layer, and the photoresist is patterned using a lithography imaging process, and a photoresist for forming the gate electrode is provided. The mask, the photoresist mask, and the mask oxide layer are etched vertically to form a mask for the gate electrode. A silicon or germanium ion implantation amorphizes the polycrystalline silicon region that is not covered by the mask oxide layer. Due to the lateral diffusion of ion implantation, and a part of the polycrystalline silicon is amorphized under the edge of the oxide layer of the mask, the amorphous silicon was removed by a conventional anisotropic dry etching method. However, a narrow area affected by the amorphous silicon is left on the side wall of the gate electrode and below the edge of the mask oxide layer. In the drawings forming the material part of this patent specification, it is a brief description of the drawing number 1 0 semiconductor substrate 1 2 gate silicon oxide 1 4 gate electrode 1 6 silicon oxide mask layer 1 8 photoresist layer 2 0 Photoresist mask 2 4 Ions 2 6 Amorphized polycrystalline silicon 3 0 Amorphized polycrystalline silicon 3 2 Source and drain regions 3 4 Detailed description of the preferred embodiment of the inner dielectric layer ΙΗΗ Page 7 4 3㈣g f Brief description of the formulas Figures 1 to 5 are schematic cross-sectional diagrams of a preferred embodiment of the present invention. Figure 6 is a schematic cross-sectional diagram of the integrated circuit component using the process of the present invention. 43 69 08 i V. Description of the invention (5) One area of 6. For example, on a polycrystalline silicon layer 14 having a thickness of 2000 angstroms, a first silicon implant with an energy of 30 to 50 kiloelectron volts (K e V) and a dose of 8 E1 4 to 5E15 atoms / cm may be Is completed, followed by a second implantation of 60 to 80 KeV with a dose of 8E14 to 5E15atoms / cm, and then a third silicon implant of 90 to 120KeV with a dose of 8e1 4 to 5E15atoms / cin. If germanium ions are implanted, all implants are implanted at a dose of 5E14 to 5E15atoms / cm2 and have energy levels ranging from 50 to 80 KeV, 100 to 170 KeV, and 100 to 270 KeV, which are the first, second, and first Three implants. The above examples are for illustration only, and the order of implantation energy is not critical. The energy level for the implantation sequence can be adjusted so that the protected depth can cover the entire thickness of the polycrystalline silicon layer. It is best to use at least Two energy distributions. This process will amorphize the entire sidewall of the gate, diffuse across a short distance to the polycrystalline silicon layer 14 and below the edge of the military curtain layer 16 'This will form a smooth side on the completed gate When avoiding unexpected vague effects. Please refer to the fifth circle. The amorphous polycrystalline silicon region 26 not covered by the mask layer 16 can be removed by an anisotropic dry etching, leaving a small area of amorphous polycrystalline silicon 30. And along the edge of the gate, this etching will be completed with the end point detection. After the end point detection, there will be an over etch between about 10 and 1505¾. The mask layer 16 can be used by conventional methods. Removed. Please refer to FIG. 6, the continuous process is a conventional technique. If the gate electrode can be manufactured by the process of the present invention as shown in the figure, the source and drain regions 32 can be formed, and the inner dielectric can be formed. Layer 3 4 and complete electrical contact window (
436908 "__ 五、發明說明（6) 未顯示）係如習用技藝。 本發明係提供一種用於石版印刷術、離子植入、及蝕 刻之製程，而可有助於閘極電極具有平滑側壁的形成，未 被閘極電極罩幕覆蓋的閘極層可被非晶化，由於橫向擴散 作用，受非晶化區部份擴大至閘極罩幕下，如此，受非晶 化多晶矽可被蝕刻而產生平滑側壁，然而，大部份的閘極 包括有無空泛效應的晶化多晶矽。 雖然本發明已被特別地表示，並參考其較佳實施例做 說明，惟應為熟習本技藝之人士所瞭解地是，各種在形式 上及細節上的改變可於不違背本發明之精神與範疇下為之 〆436908 " __ 5. The description of the invention (6) (not shown) is a conventional technique. The invention provides a process for lithography, ion implantation, and etching, which can help the formation of gate electrodes with smooth sidewalls. The gate layer not covered by the gate electrode cover can be amorphous Due to the lateral diffusion effect, the portion affected by the amorphization is enlarged under the gate cover. In this way, the polycrystalline silicon that is affected by the amorphization can be etched to produce a smooth sidewall. However, most of the gates include crystals with or without the flooding effect. Polycrystalline silicon. Although the present invention has been particularly shown and described with reference to its preferred embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Under the category
第10頁 4 、-芝 圖式簡單說明 第1圖至第5圖係為本發明一較佳實施例之橫剖面示意圖 〇 第6圖係為利用本發明製程而完成積體電路元件之橫剖面 示意圖。Page 10 4-Brief description of Schematic diagrams. Figures 1 to 5 are schematic cross-sectional views of a preferred embodiment of the present invention. Figure 6 is a cross-section of the integrated circuit component to complete the process of the present invention. schematic diagram.