JPH04360540A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the irregularity of film thickness, by forming high impurity concentration source/drain regions by using photo resist as a mask, making the photo resist narrow and small, and forming low impurity concentration source/drain regions by using the narrow small photo resist as a mask. CONSTITUTION:Polycrystalline silicon 5 is selectively etched by patterning hydrophobic photo resist 4 for working a gate electrode. High concentration source/drain regions 7, 8 are formed by implanting arsenic ions 6 in silicon substrate by using the photo resist 4 as a mask. The surface of photo resist 41 is ashed and eliminated by exposing a P-type silicon substrate 1 to exygen plasma. In this process, the width of photo resist is made narrow and small. Left photo resist is used as a mask, and phosphorus ions 9 are impanted, thereby forming low concentration source/drain regions 10, 11.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a D-structure MIS field effect transistor.

0002

[Prior Art] A MIS type semiconductor device with an inverted T-shaped gate structure has a structure in which a lightly doped drain region overlaps a gate electrode, so it has high current driving ability and has little characteristic variation with respect to hot carriers. It has the following characteristics. However, it is difficult to process gate electrodes with complex shapes with good controllability, and transistor characteristics vary and hot carrier reliability tends to decrease.

As a method for manufacturing a MIS type semiconductor device having an inverted T-shaped gate structure, a method is known in which etching of the gate electrode material is stopped midway. This manufacturing method will be explained using process cross-sectional views shown in FIG.

First, a gate insulating film 2 is formed on a semiconductor substrate 1.
and a gate electrode material, and a gate electrode 3 is formed thereon.
Form a photoresist 4 for processing (Fig. 3(
a)). Next, using the photoresist 4 as a mask, the gate electrode 3 is etched, and the etching is finished before reaching the gate insulating film 2, leaving a thin gate electrode material. The photoresist 4 is peeled off, and ions are implanted to form low concentration source/drain regions using the thick gate electrode 6 portion as a mask (FIG. 3(b)).

Next, side walls 15 made of SiO2 are formed around the gate electrode (FIG. 3(c)). Next, using this side wall 15 as a mask, a portion of the thin gate electrode 5 is etched and removed. Then, using the gate electrode and its sidewalls 15 as masks, ion implantation is performed to form highly concentrated source/drain regions (FIG. 3(d)).

[0006]

SUMMARY OF THE INVENTION The method for manufacturing an MIS type semiconductor device as described above has the following problems.

First, it is difficult to set the etching time for the gate electrode, and the thickness of the thin gate electrodes on both sides is difficult to control. Therefore, since the depth of the diffusion layer in the lightly doped source/drain region is not stable, transistor characteristics such as threshold voltage and mutual conductance vary and hot carrier reliability tends to decrease.

Second, the sidewalls of the gate electrode are used to determine the length of the thin gate electrode overhang, that is, the length of the lightly doped source/drain region, but this is difficult and unstable because it is difficult to suppress the sidewall width. Similarly, transistor characteristics and hot carrier reliability are likely to deteriorate. Third, since a sidewall is formed around a thick gate electrode and a thin gate electrode is processed, the width of the gate electrode becomes wider than the processing dimension of the photoresist, which is not suitable for miniaturization of transistors. The present invention
It is an object of the present invention to provide a method for manufacturing an MIS type semiconductor device that solves such problems. [Structure of the invention]

[0009]

[Means for Solving the Problems] The present invention has been tried in view of the above circumstances, and includes a method of forming a first gate electrode layer and a photoresist on a semiconductor substrate through a gate insulating film in an area where a gate electrode is to be formed. a step of laminating the photoresist, a step of implanting ions using the photoresist as a mask to form a highly concentrated source/drain region in the semiconductor substrate, a step of reducing the width of the photoresist compared to the width of the first gate electrode, A step of implanting ions using this narrowed photoresist as a mask to form a low concentration source/drain region under the first gate electrode, a step of selectively forming an insulating film on the semiconductor substrate, and a step of forming a low concentration source/drain region under the first gate electrode. Provided is a method for manufacturing a semiconductor device, comprising the steps of: forming a groove by removing the first gate electrode; and filling the groove with an electrode material to form a second gate electrode.

0010

[Operation] As described above, according to the present invention, the thickness of the thin gate electrode can be controlled by controlling the amount of the electrode material deposited, so that variations in the film thickness are small. Therefore, the concentration distribution in the depth direction of the lightly doped source/drain region by ion implantation can be accurately controlled.

Furthermore, since the photoresist processed into the thin gate electrode is slowly thinned using low-power oxygen plasma, the length of the overhanging portion of the thin gate electrode can be accurately controlled. Therefore, the overlap length between the gate electrode and the drain region can be accurately controlled. The above two points make it possible to manufacture an inverted T-shaped MIS transistor in which transistor characteristics and hot carrier reliability are unlikely to deteriorate.

Furthermore, since the lower gate electrode to be etched may be thin, there is little possibility of over-etching the gate insulating film, making it suitable for thinning the gate insulating film. Additionally, there is no need to use special etching equipment to process the gate electrode, leading to cost reductions.

On the other hand, since the gate electrode width is the same as the processing dimensions of the photoresist initially formed, the gate electrode width can be shortened to the limit of lithography, which is suitable for miniaturization of transistors.

[0014]

Embodiments Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

In FIG. 1(d), a MOS field effect transistor (hereinafter abbreviated as MOSFET) is an n-channel type, and is formed on the main surface of a p-type Si substrate. A thin gate electrode made of a gate oxide film and n+ type polycrystalline silicon is provided on the element formation region in the p-type Si substrate, and a thick gate electrode made of tungsten is further provided thereon. A silicon oxide film grown in a liquid phase is formed on both sides thereof. FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

A gate oxide film 2 is formed to a thickness of 20 nm on the main surface of a p-type silicon substrate 1, and an n+ type polycrystalline silicon 5 is formed thereon to a thickness of 50 nm. A hydrophobic photoresist 4 of 1.3μ for gate electrode processing was created using lithography.
The polycrystalline silicon 5 (first gate electrode) is patterned to a thickness of m and selectively etched so that the gate length becomes 1.0 μm. Then, using the foresist 4 as a mask, arsenic ions 6 are implanted into the silicon substrate at an accelerating voltage of 50 kV.
, 8 (Fig. 1(a)).

Next, the p-type silicon substrate 1 is heated to an oxygen gas pressure of 50
The photoresist 41 is exposed to oxygen plasma at mTorr and power of 50 W, and the surface of the photoresist 41 is ashed to 200 nm and removed. Here, the width of the photoresist is from 1.0 μm to 0.6 μm.
Narrowed down to μm. Using the remaining photoresist as a mask, phosphorus ions 9 are implanted at an acceleration voltage of 45 keV to form low concentration source/drain regions 10 and 11 (FIG. 1(b)).

Next, LPD (Liquid Phase Depo) is applied so that no film is formed on the photoresist 41.
The silicon oxide film 12 is selectively formed using the
is grown in liquid phase. That is, the substrate 1 is immersed in a saturated H2 SiF6 solution to which H3 BO3 is added. Here, since the photoresist 41 is hydrophobic, the photoresist 41
The silicon oxide film 12 is not formed thereon (FIG. 1(c)
)). Next, the photoresist 41 is removed, and tungsten 13 (second gate electrode) is selectively grown on the gate electrode 5 of n+ type polycrystalline silicon.

FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps. Components that are the same as those in FIG. 1 are given the same numbers, and detailed explanations will be omitted. In the first embodiment, the shallow and deep regions of the source/drain diffusion layer were formed by separate ion implantations, but in the second embodiment, as shown in FIG.
The difference is that they are formed simultaneously by multiple ion implantations.

In the above embodiment, the case of an n-channel type MOSFET has been explained, but the same implementation is also possible for a p-channel type MOSFET. Furthermore, the materials for the first and second gate electrodes are not limited to n+ type polycrystalline silicon or tungsten. In particular, regarding the thick upper second gate electrode, it is also possible to form a conductive material over the entire surface of the wafer and leave it only on the gate portion using an etch-back method. Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and that various changes can be made without departing from the spirit of the invention.

[0021]

As explained above, according to the present invention, in an LDD structure MIS type semiconductor device having an inverted T-shaped gate structure, the thickness of the thin gate electrodes on both sides, the source/drain region and the gate electrode can be adjusted. The overlap length can be controlled well, and the impurity distribution in shallow source/drain regions can be manufactured stably. Therefore, it is possible to stably manufacture an MIS structure semiconductor in which transistor characteristics and hot carrier reliability are less likely to deteriorate.

Furthermore, unlike transistors with a normal inverted T-shaped gate electrode structure, the width of the thin gate electrode can be reduced to the limit of lithography technology, maintaining high current driving power and hot carrier reliability. However, transistors can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1... Semiconductor substrate 2... Gate insulating film 3, 5... N+ type polycrystalline Si 4... Photoresist 6... Arsenic ions 7, 8... N+ type source/drain diffusion layer 9... Phosphorus ions 10, 11... N+ type source/drain Diffusion layer 12...Liquid layer grown SiO2 film 13...Tungsten 15, 16...SiO2 film

Claims (2)

[Claims] 1. A step of laminating a first gate electrode layer and a photoresist in a region where a gate electrode is to be formed on a semiconductor substrate via a gate insulating film, and using the photoresist as a mask, ions are implanted into the semiconductor substrate. a step of forming a source/drain region with high impurity concentration, a step of narrowing the photoresist in comparison with the width of the first gate electrode, and performing ion implantation using the narrowed photoresist as a mask; a step of forming a low impurity concentration source/drain region under the first gate electrode; a step of selectively forming an insulating film on the semiconductor substrate; a step of removing the photoresist and forming a groove; 1. A method of manufacturing a semiconductor device, comprising the step of burying an electrode material in a groove to form a second gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a liquid phase growth method is used in the step of selectively forming an insulating film on the semiconductor substrate.