JPH08250604A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To reduce photoresist processes and thus manufacturing cost. CONSTITUTION: Using a photoresist layer 21 formed above a ntype well 3 as a mask, ions of boron are implanted to form a p<+> -type impurity diffusion layer 14. Subsequently, the photoresist layer 21 is reduced by ashing and turned into another photoresist layer 21'. Using the reduced photoresist layer 21' as a mask, ions of boron are implanted to form a p<-> -type impurity diffusion layer 9. Thus LDD structure is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
In particular, the present invention relates to a method for manufacturing, for example, a CMOS semiconductor device having an LDD (Lightly Doped Drain) structure.

[0002]

2. Description of the Related Art With high integration and miniaturization of MOS transistors, deterioration of elements due to hot carriers has become remarkable. Therefore, a MOS transistor having an LDD structure has been recently developed.

A method of manufacturing a conventional CMOS semiconductor device having an LDD structure will be described with reference to FIGS.

First, referring to FIG. 5A, a P-type well 2 and an N-type well 3 are formed on a silicon single crystal substrate 1, and a P-type MOS transistor is formed by a field oxide layer 4 using a LOCOS method. Formation area (hereinafter P
It is divided into a MOS formation region) and an N-channel type MOS transistor formation region (hereinafter, NMOS formation region). Next, a thickness of about 1 is applied to the PMOS formation region and the NMOS formation region.
A gate oxide layer 4 having a thickness of 5 nm is formed by a thermal oxidation method, and a polysilicon layer 6 having a thickness of about 200 nm is further formed thereon. Next, a pattern of the photoresist layer 7 is formed, and the polysilicon layer 6 is dry-etched using this as a mask, so that the polysilicon layer 6 becomes a gate electrode as shown in the figure. And the photoresist layer 7
Is removed.

Next, referring to FIG. 5B, after the pattern of the photoresist layer 8 is formed again to cover the NMOS formation region, boron ions are added with energy 3 for example.
Implant with 0 KeV and a dose of about 3.0 × 10 ¹³ cm ^-2 .
As a result, the low concentration P ⁻ -type impurity diffusion layer 9 is formed in the PMOS formation region. Then, the photoresist layer 8 is removed.

Next, referring to FIG. 5C, after the pattern of the photoresist layer 10 is formed again to cover the PMOS formation region, phosphorus ions, for example, with an energy of 4.
Implant with 0 KeV and a dose of about 3.0 × 10 ¹³ cm ^-2 .
As a result, the low concentration N ⁻ -type impurity diffusion layer 11 is
It is formed in the formation region. Then, the photoresist layer 8 is removed. Then, the photoresist layer 10 is removed.

Next, referring to FIG. 6A, a silicon oxide layer is formed on the entire surface and is etched back. For example, RF power of 20 in an atmosphere of CF ₄ and CHF _4.
Dry etching is performed for about 50 s under the condition of 0 W. As a result, the silicon oxide layer is formed on the gate electrode 6 as shown in the figure.
Remain as the sidewall oxide layer 12 of.

Next, referring to FIG. 6B, after the pattern of the photoresist layer 13 is formed again to cover the NMOS formation region, boron ions, for example, have an energy of 70 KeV and a dose amount of about 5.0 × 10. Inject at ¹⁵ cm ^-2 . As a result, the high concentration P ⁺ -type impurity diffusion layer 14 becomes PM.
It is formed in the OS formation region. Then, the photoresist layer 13 is removed.

Next, referring to FIG. 6C, after the pattern of the photoresist layer 15 is formed again to cover the PMOS formation region, the arsenic ions are exposed to, for example, energy 7.
Implant with 0 KeV and a dose of about 1.0 × 10 ¹⁶ cm ^-2 .
As a result, the high-concentration N ⁺ -type impurity diffusion layer 16 is
It is formed in the formation region. Then, the photoresist layer 15
Is removed.

Finally, although not shown, a BSG layer as an interlayer insulating layer is formed, an opening is formed on the gate electrode 6 and wiring of an aluminum layer is provided, whereby a desired CMOS semiconductor device can be obtained.

[0011]

However, as shown in FIG.
In the method of manufacturing the semiconductor device shown in FIG. 6, there are many photoresist steps, and as a result, there is a problem that the manufacturing cost increases. For example, in FIG. 5 and FIG. 6, the photoresist layer 7, 8, 10, 13, 15 needs to be performed five times. Further, it is necessary to form the sidewall oxide layer 12 in order to form the high-concentration impurity diffusion layers 14 and 16 of the LDD structure, and the entire surface is etched back at that time, which damages the source and drain regions, that is, the surface of the impurity diffusion layer As a result, there is also a problem that the contact resistance on the diffusion layer is high and varies. Further, there is a problem that the level difference of the interlayer insulating layer due to the gate electrode or the like is so large that it cannot be ignored as the wiring becomes finer.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device in which the photoresist process is reduced and the manufacturing cost is reduced. Another object is to reduce the damage on the surface of the diffusion layer and reduce and stabilize the contact resistance on the diffusion layer. Still another object of the present invention is to planarize the interlayer insulating layer.

[0013]

In order to solve the above problems, the present invention provides a first method in which a photoresist layer is formed on a semiconductor substrate and impurities are introduced into the semiconductor substrate using the photoresist layer as a mask. An impurity diffusion layer is formed. Next, the photoresist layer is reduced, and impurities are introduced into the semiconductor substrate using the reduced photoresist layer as a mask to form a second impurity diffusion layer. Also,
After forming the above-mentioned second impurity diffusion layer, an insulating layer is formed in the reduced opening region of the photoresist layer by the LPD method.

[0014]

In contrast to the two types of impurity diffusion layers formed by the conventional mask of the gate electrode and the mask of the gate electrode and the sidewall oxide layer, the above-described means allows the mask of the photoresist layer and the reduction of the size to be reduced. Two kinds of impurity diffusion layers are formed by the mask of the photoresist layer. Also, the height of the insulating layer formed in the reduced opening portion of the photoresist layer matches the height of the gate electrode formed in a subsequent process.

[0015]

1 to 4 are sectional views showing an embodiment of a CMOS semiconductor device according to the present invention.

First, referring to FIG. 1A, a P type well 2 and an N type well 3 are formed on a silicon single crystal substrate 1, and a PMOS formation region and an NMOS are formed by a field oxide layer 4 using a LOCOS method. It is divided into a formation area.
Next, a gate oxide layer 4 having a thickness of about 15 nm is formed in the PMOS formation region and the NMOS formation region by a thermal oxidation method.
Next, a photoresist layer 21 having a thickness of about 1 μm is formed,
The entire gate electrode region of the PMOS formation region and the entire NMOS formation region are covered. For example, if the gate electrode is 0.5 μm
The pedestal pattern is 0.4μ on one side.
m, the photoresist layer 21 in the gate electrode region of the PMOS formation region is 1.3 μm □. Next, using the photoresist layer 21 as a mask, boron ions, for example, having an energy of 70 KeV and a dose of about 5.0 × 10 ¹⁵ cm ^{-2 are used.}
Inject. As a result, the high concentration P ⁺ -type impurity diffusion layer 1
4 is formed in the PMOS formation region.

Next, referring to FIG. 1B, the photoresist layer 21 is reduced into a photoresist layer 21 'by using a reproducible oxygen plasma ashing technique (see "Deep-Submicrometer MOS"). Device Fabricatio
n Using a Photoresist-Ashing Technique ", IEEE Elec
tron Device Lett.vol.EDL-9, pp.186-188, 1988)
For example, ashing is 30 kHz and pressure is about 300 mT.
It is performed for about 3 minutes under the condition of RF power of 50 W in an oxygen plasma atmosphere of orr. As a result, the photoresist layer 21 ′ in the gate electrode region of the PMOS formation region becomes 0.7 μm □. Next, using the photoresist layer 21 'as a mask, boron ions are implanted with an energy of 30 KeV and a dose of about 3.0 × 10 ¹³ cm ^-2 , for example. As a result, the low concentration P ⁻ -type impurity diffusion layer 9 is formed in the PMOS formation region.

Next, referring to FIG. 1C, an LPD method (Liquid Phase Ox) is applied to the opening of the photoresist layer 21 '.
ide Deposition) For example, H ₂ S _i F ₆ and H ₂ O are reacted at 35 ° C. to form a silicon oxide layer 22 having a thickness of about 0.2 μm. Then, the photoresist layer 21 'is removed.

First, referring to FIG. 2A, a photoresist layer 23 having a thickness of about 1 μm is formed to cover the gate electrode region and the PMOS formation region of the NMOS formation region. In this case, if the gate electrode has a pedestal pattern of 0.5 μm and the pedestal margin is 0.4 μm on one side,
The photoresist layer 23 in the gate electrode region of the NMOS formation region is 1.3 μm □. Next, the photoresist layer 2
3 is used as a mask, and arsenic ions, for example, energy 7
Implant with 0 KeV and a dose of about 1.0 × 10 ¹⁶ cm ^-2 .
As a result, the high concentration P ⁺ -type impurity diffusion layer 16 is
It is formed in the formation region.

Next, referring to FIG. 2B, as in the case of FIG. 1B, the photoresist layer 23 is reduced to form a photoresist layer 23 'by using an ashing technique. As a result, the photoresist layer 23 'in the gate electrode region of the NMOS formation region becomes 0.7 μm □. next,
Using the photoresist layer 23 'as a mask, phosphorus ions, for example, have an energy of 40 KeV and a dose of about 3.0 × 10.
Inject at ¹³ cm ^-2 . As a result, the low concentration N ⁻ -type impurity diffusion layer 11 is formed in the NMOS formation region.

Next, referring to FIG. 2C, L is formed in the opening of the photoresist layer 21 'as in FIG. 1C.
A silicon oxide layer 24 having a thickness of about 0.2 μm is formed by the PD method. Then, the photoresist layer 23 'is removed.

Next, referring to FIG. 3A, a polysilicon layer 25 having a thickness of about 650 nm is formed on the entire surface.

Next, referring to FIG. 3B, the gate electrode 25 'is formed in the PMOS formation region and the NMOS cooling region by etching back the polysilicon layer 25.

Next, referring to FIG. 4A, a refractory metal layer such as a titanium layer 26 is formed on the entire surface.

Next, referring to FIG. 4B, heat treatment is performed to silicify the upper portion of the gate electrode (polysilicon) 25 '. After that, the non-silicided portion of the titanium layer 26 is removed. Thereby, the resistance of the gate electrode is reduced.

Finally, although not shown, a BSG layer as an interlayer insulating layer is formed, an opening is formed on the gate electrode 25 ', and wiring of an aluminum layer is provided to obtain a desired CMOS semiconductor device.

As described above, in the embodiment of the present invention,
The number of photoresist steps for forming the photoresist layers 21 and 23 is twice, which is smaller than the number of photoresist steps of 5 in the conventional semiconductor device manufacturing method shown in FIGS. Further, the sidewall oxide layer 12 shown in FIGS. 5 and 6 is not required to be formed, and therefore, there is no etching process associated therewith, so that the diffusion layer is not damaged. Furthermore, LP
The gate electrode 25 'and the silicon oxide layer 22,
The step with 24 is eliminated, and as a result, the step of the interlayer insulating layer formed thereon is also eliminated.

Although the above embodiment relates to a CMOS transistor, the present invention can be applied to a PMOS transistor or an NMOS transistor.

[0029]

As described above, according to the present invention, the photoresist process can be reduced and the manufacturing cost can be reduced.
Further, it is possible to reduce the damage on the surface of the diffusion layer and reduce and stabilize the contact resistance on the diffusion layer. Further, the interlayer insulating layer can be flattened.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing an example of a method of manufacturing a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device.

FIG. 6 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

1 ... Silicon single crystal substrate 2 ... P-type well 3 ... N-type well 4 ... Field oxide layer 5 ... Gate oxide layer 6 ... Gate electrode 7, 8, 10 ... Photoresist layer 9 ... P ⁻ type impurity diffusion layer 11 ... N ^- -type impurity diffusion layer 12 ... sidewall oxide layers 13 and 15 ... photo-resist layer 14 ... P ⁺ -type procedure Buddha diffusion layer 16 ... N ⁺ -type impurity diffusion layer 21, 21 ', 23, 23' ... photoresist layer 22, 24 ... Silicon oxide layer 25 ... Polysilicon layer 25 '... Gate electrode 26 ... Titanium layer 26' ... Titanium silicide layer

Claims (7)

[Claims] 1. A step of forming a photoresist layer (21, 23) on a semiconductor substrate (1), and an impurity is introduced into the semiconductor substrate by using the photoresist layer as a mask to form a first impurity diffusion layer (14). , 16), a step of reducing the photoresist layer, and a step of introducing impurities into the semiconductor substrate using the reduced photoresist layers (21 ′, 23 ′) as a mask to diffuse a second impurity. And a step of forming a layer (9.11). 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of reducing the photoresist layer reduces the photoresist layer by ashing. 3. A step of forming an insulating layer (22, 24) in the opening region of the reduced photoresist layer by an LPD method after forming the second impurity diffusion layer, and forming the insulating layer. After that, the step of removing the photoresist layer, the step of forming the metal layer (25) on the entire surface after removing the photoresist layer, and the step of etching back the metal layer are performed.
A method of manufacturing a semiconductor device according to item 1. 4. The method according to claim 1, wherein the metal layer is a silicon layer, and the method further comprises forming a refractory metal layer (26) on the silicon layer after the etching back and performing a heat treatment to form a part of the silicon layer. The method for manufacturing a semiconductor device according to claim 3, further comprising: a step of forming a non-metal silicide layer in the refractory metal layer; 5. A semiconductor substrate (1) having a first conductivity type first
Forming a transistor forming region and a second transistor forming region of a second conductivity type opposite to the first conductivity type; a channel region of the first transistor forming region and the second conductivity type region. As a first photoresist layer (21)
And a step of forming a first high-concentration impurity diffusion layer (14) by introducing impurities of the second conductivity type into the first transistor formation region using the first photoresist layer as a mask. Reducing the first photoresist layer by ashing, and introducing a second conductivity type impurity into the first transistor formation region using the reduced first photoresist layer as a mask, The step of forming the low-concentration impurity diffusion layer (14), the step of removing the first photoresist layer, and the step of forming the channel region of the second transistor formation region and the first conductivity type region in the second region. Photoresist layer (23)
And a step of forming a second high-concentration impurity diffusion layer (16) by introducing impurities of the first conductivity type into the second transistor formation region using the second photoresist layer as a mask. A step of reducing the second photoresist layer by ashing, and a step of introducing a first conductivity type impurity into the second transistor formation region using the reduced second photoresist layer as a mask, Forming a low-concentration impurity diffusion layer (11), and removing the second photoresist layer. 6. A step of forming a first insulating layer (22) by an LPD method in the opening region of the reduced first photoresist layer after forming the first low-concentration impurity diffusion layer. Forming a second insulating layer (24) by an LPD method in the opening region of the reduced second photoresist layer after forming the second low-concentration impurity diffusion layer; and After removing the resist layer, the metal layer (2
6. A step of forming 5) on the entire surface, and a step of etching back the metal layer.
A method of manufacturing a semiconductor device according to item 1. 7. The method according to claim 1, wherein the metal layer is a silicon layer, and the method further comprises forming a refractory metal layer (26) on the silicon layer after the etching back and performing a heat treatment to form a part of the silicon layer. The method for manufacturing a semiconductor device according to claim 6, further comprising: a step of forming a non-metal silicide layer in the refractory metal layer;