JP3228200B2 - LDD structure transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a method of manufacturing a transistor and its the LDD structure constituting the CMOS semiconductor device or the like, in particular reducing the number of photoresist steps LD
A method of manufacturing a transistor and its having a D configuration.

[0002]

2. Description of the Related Art FIGS. 2A to 2C are sectional views showing a method of manufacturing a conventional MOS transistor having an LDD structure in the order of steps. First, as shown in FIG.
After forming a P-well or N-well 1 on the surface of the mold substrate, respectively, an element isolation region 2 is formed on the surface of the substrate, then a gate oxide film 3 is formed, and a polysilicon layer 4 is formed. A stacked gate electrode 6 composed of a tungsten silicide (WSi) layer 5 is patterned. Thereafter, using this gate electrode 6 as a mask, photolithography (P
R), the substrate surface (the surface of well 1) is N-type or P-type.
A low concentration active region (LDD region) 8 composed of an N layer or a P layer is formed by implanting a type impurity.

[0003] Next, as shown in FIG. 2 (b), an oxide film having good coverage is grown on the entire surface, and the oxide film is left on the side wall of the gate electrode 6 by anisotropic etching to form a sidewall 7. Form.

Thereafter, as shown in FIG. 2C, the PR is again formed using the gate electrode 6 and the side wall 7 as a mask.
By the process, N-type or P-type impurities are implanted into the substrate surface,
High concentration active region (SD region) 9 composed of N ⁺ layer or P ⁺ layer
To form In the conventional method, usually, up to this stage, 8 to 10 PR steps are required.

[0005]

However, recently,
The reduction of the time related to the diffusion step has become an important issue, and the demand for reducing the number of PRs has been increasing. Also, improving productivity is always an issue, and approaches to improving yield are always a problem.

The present invention was made in view of the above problems, it is possible to reduce the PR number, to provide a method for producing a transistor and its LDD structure which can improve productivity and yield Aim.

[0007]

An LDD structure according to the present invention
Transistor is placed at a predetermined distance from the surface of the semiconductor substrate.
The two formed low concentration active regions (LDD regions)
The semiconductor between these two low concentration active regions (LDD regions)
Formed on the surface of the substrate via a gate insulating film
In a transistor having an LDD structure having an electrode,
The lower electrode is composed of a lower layer made of the first material and a second material.
At least two of the upper layers are laminated, and
A third material is formed on the entire exposed surface of the upper layer.
It is characterized by having an overhang layer. L according to the present invention
A method for manufacturing a transistor having a DD structure is described on a semiconductor substrate.
Forming a lower layer and a multilayer gate electrode comprising at least two layers of an upper layer made of the second material pattern made of the first material, the tension <br/> out layer of a third material around the upper and forming, by ion implantation in a direction inclined against the surface of the semiconductor substrate and the gate electrode and the overhanging layer as a mask, forming a low concentration active region in the semiconductor substrate surface, the gate by ion implantation from the direction perpendicular against the surface of the semiconductor substrate and the electrode and the overhanging layer as a mask, and forming a high-concentration active region of higher concentration than the low concentration active region in the semiconductor substrate surface It is characterized by having.

In this method of manufacturing a transistor having an LDD structure, the upper layer is, for example, a WSi layer, the lower layer is a polysilicon layer, and the overhanging layer is a WSi layer.
It can be a layer.

The low-concentration active region can be formed by ion-implanting the semiconductor substrate surface in an inclined direction while rotating the semiconductor substrate. Further, the W layer constituting the overhang layer can be formed by selective growth using WF ₆ gas.

As described above, in the present invention, the CMOS
In a transistor having an LDD structure such as a semiconductor device, a mushroom-type electrode is formed by selectively growing tungsten (W) around a WSi layer, for example, above a stacked gate electrode. Thereafter, an LDD region is formed by oblique rotation implantation, and an SD region is formed by 0 ° implantation. Thereby, conventionally, in order to form a semiconductor device having an LDD structure,
While three or four PR steps are required, the present invention can reduce the number of PR steps to two. Also,
Since the etch-back process at the time of forming the sidewall is reduced, damage to the substrate is reduced, and a favorable crystal structure can be maintained.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 (a),
(B) is sectional drawing which shows the example method of this invention in order of a process. As shown in FIG. 1A, a stacked gate electrode 6 is formed in the same process as in the related art. The gate electrode 6 has a polysilicon layer 4 as a lower layer and a WSi layer 5 as an upper layer.

Thereafter, selective growth using WF ₆ gas is performed, and W is selectively grown only around the WSi layer 5, that is, only on the upper surface and side surfaces of the WSi layer 5, thereby forming the W layer 10 as an overhanging layer. To form Thus, a mushroom type gate electrode shape is formed.

Next, as shown in FIG. 1B, while rotating the substrate, an N-type or P-type
A low-concentration active region (LDD region) 8 is formed in a portion of the substrate surface that is not covered by the lower polysilicon layer 4 by a rotational oblique implantation method of implanting a type impurity. Then, high-concentration active regions (S
D region) 9 is formed. The high-concentration active region 9 is formed by so-called 0 ° implantation using a W layer 10 as an overhanging layer extending horizontally from the upper WSi layer 5 of the gate electrode 6 as a mask.
It is formed in the substrate surface area except immediately below the layer 10. After the ion implantation, the ion implantation region is activated by the same heat treatment as in the related art. Thus, a transistor having an LDD structure is formed.

In the present invention, in order to form a semiconductor device having an LDD structure, two PR steps are sufficient, and the number of PR steps can be remarkably reduced as compared with the conventional three or four times. Further, since an etch back step in forming the sidewall is reduced, damage to the substrate is reduced, and a favorable crystal structure can be maintained.

[0015]

As described above, the present invention provides, for example,
By the selective growth of W, a mushroom type gate electrode having an overhanging layer on the upper layer is formed, and using this as a mask,
Since low concentration regions and high concentration regions are formed by oblique ion implantation into the substrate and ion implantation in the vertical direction into the substrate, the conventional 3-4 PR required area can be formed by 2PR, and the diffusion process is shortened. it can. Further, by reducing the number of etch-back steps used when forming the sidewall, damage to the substrate can be reduced, thereby reducing the number of defective modes due to leakage by several percent.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method for manufacturing a transistor having an LDD structure according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a conventional method of manufacturing a transistor having an LDD structure in the order of steps.

[Explanation of symbols]

 1: Well 2: Device isolation region 3: Gate oxide film 4: Polysilicon layer 5: WSi layer 6: Gate electrode 7: Side wall 8: Low concentration active region 9: High concentration active region 10: W layer

Claims (7)

(57) [Claims] 1. A semiconductor substrate is formed at a predetermined distance on a surface of a semiconductor substrate.
Two low-concentration active regions (LDD regions)
The semiconductor substrate between two low concentration active regions (LDD regions)
Gate electrode formed on the surface of the board via a gate insulating film
The gate of the transistor having the LDD structure having
The electrode comprises a lower layer of the first material and a lower layer of the second material.
At least two of the upper layers are laminated, and
Tension made of a third material over the entire exposed surface of the upper layer
Transistor having LDD structure characterized by having an extension layer
Star. 2. A step of patterning a stacked gate electrode comprising at least two layers, a lower layer made of a first material and an upper layer made of a second material, on a semiconductor substrate, and forming a stacked gate electrode around the upper layer using a third material. forming an overhang layer made by ion implantation in a direction inclined against the surface of the semiconductor substrate and the gate electrode and the overhanging layer as a mask, forming a low concentration active region in the semiconductor substrate surface When the by the gate electrode and the overhanging layer as a mask to ion implantation from a vertical towards <br/> direction against the surface of the semiconductor substrate, the low-density active high concentrations of higher than the area on the semiconductor substrate surface Forming a concentration active region. 3. The method according to claim 2 , wherein the upper layer is a WSi layer. Wherein said lower layer, method for producing a transistor of the LDD structure according to claim 2 or 3, characterized in that a polysilicon layer. 5. The method according to claim 3 , wherein the overhanging layer is a W layer. Wherein said low concentration active region, any one of claims 2 to 5, characterized in that formed by ion implantation in a direction inclined to the surface of the semiconductor substrate while rotating the semiconductor substrate 4. The method for manufacturing a transistor having an LDD structure according to item 1. 7. The W layer constituting the overhang layer is WF
_{6. The} method for manufacturing a transistor having an LDD structure according to claim 5 , wherein the transistor is formed by selective growth using _six gases.