KR100305402B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100305402B1 KR100305402B1 KR1019980062014A KR19980062014A KR100305402B1 KR 100305402 B1 KR100305402 B1 KR 100305402B1 KR 1019980062014 A KR1019980062014 A KR 1019980062014A KR 19980062014 A KR19980062014 A KR 19980062014A KR 100305402 B1 KR100305402 B1 KR 100305402B1
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- mosfet
- forming
- contact
- silicon substrate
- polysilicon layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 2
- 238000001953 recrystallisation Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 반도체의 집적도가 높아짐에 따라 CMOS 인버터 제조시에 높은 에스펙트비를 갖는 플러그 형성공정의 어려움을 해결하고자 반도체기판상에 기판의 수직되게 N-MOS와 P-MOS가 적층된 TFT 구조의 인버터를 제조하므로써 종래기술에 있어서의 높은 에스펙트비로 인한 공정의 어려움을 줄일 수 있을 뿐만아니라 반도체소자의 인버터가 차지하는 면적을 줄일 수 있어 고집적 소자제조에 적합한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and as the degree of integration of semiconductors increases, in order to solve the difficulty of a plug forming process having a high aspect ratio when manufacturing a CMOS inverter, an N-MOS and a substrate are vertically aligned on a semiconductor substrate. By manufacturing an inverter having a stacked TFT structure with P-MOS, the process difficulty due to the high aspect ratio in the prior art can be reduced, and the area occupied by the inverter of the semiconductor device can be reduced, which is suitable for manufacturing a highly integrated device.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 적층 구조인 TFT 구조를 이용하여 인버터를 제조하여 고집적소자제조시에 적합하도록한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which an inverter is manufactured using a TFT structure, which is a laminated structure, to be suitable for manufacturing a highly integrated device.
종래 기술에 따른 반도체소자의 인버터회로 형성방법을 도 1 및 도 2 를 참조하여 설명하면 다음과 같다.A method of forming an inverter circuit of a semiconductor device according to the prior art will be described with reference to FIGS. 1 and 2 as follows.
도 1 은 종래 기술에 따른 반도체소자의 인버터회로의 제조공정을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a manufacturing process of an inverter circuit of a semiconductor device according to the prior art.
도 2 는 일반적인 종래의 반도체소자의 인버터 회로의 회로구성도이다.2 is a circuit configuration diagram of an inverter circuit of a conventional conventional semiconductor device.
종래 기술에 따른 반도체소자의 인버터회로 제조공정은, 도 1 에 도시된 바와같이, 실리콘기판(1)상에 P-MOSFET와 N-MOSFET를 형성하기 위한 N웰(2)과 P웰(3)을 형성하고, 상기 실리콘기판(1)상에 활성영역과 필드영역을 정의해 주는 소자분리막(4)을 형성한다.The inverter circuit manufacturing process of the semiconductor device according to the prior art, as shown in Figure 1, the N well (2) and P well (3) for forming the P-MOSFET and N-MOSFET on the silicon substrate (1) And a device isolation film 4 defining an active region and a field region on the silicon substrate 1.
그다음, 상기 P-MOSFET와 N-MOSFET가 형성될 실리콘기판(1)의 활성영역상에 게이트산화막(5)과 워드라인(6)을 적층하고, 이들 측면에 워드라인스페이서(7)를 형성한다.Next, a gate oxide film 5 and a word line 6 are laminated on the active region of the silicon substrate 1 on which the P-MOSFET and the N-MOSFET are to be formed, and word liner spacers 7 are formed on these side surfaces. .
이어서, 노출된 상기 실리콘기판(1)의 N웰(3)에는 P형 불순물을 주입하여 P형불순물영역(미도시)을 형성하고, P웰(4)에는 N형불순물을 주입하여 N형 불순물영역(미도시)을 형성하여 P-MOSFET와 N-MOSFET를 형성한다.Subsequently, a P-type impurity region (not shown) is implanted into the N well 3 of the exposed silicon substrate 1 to form a P-type impurity, and an N-type impurity is implanted into the P well 4. A region (not shown) is formed to form a P-MOSFET and an N-MOSFET.
그다음, 전체 구조의 상부에 제1층간절연막(8)을 증착하고, 상기 제1층간절연막(8)을 선택적으로 제거하여 상기 P-MOSFET의 소오스와 드레인용으로 사용하는 P형불순물영역(미도시)을 노출시키는 제1콘택홀(미도시)을 형성한다.Then, a P-type impurity region (not shown) is used for the source and drain of the P-MOSFET by depositing a first interlayer insulating film 8 over the entire structure and selectively removing the first interlayer insulating film 8. ) To form a first contact hole (not shown).
이어서, 상기 P-MOSFET 상에 위치한 제1콘택홀내에 도선성물질을 매립하여 콘택플러그(9)을 형성한다.Subsequently, the contact plug 9 is formed by filling the conductive material in the first contact hole on the P-MOSFET.
그다음, 전체 구조의 상부에 제2 층간절연막(10)을 증착하고, 상기 P-MOSFET상에 위치하는 제2층간절연막(10) 부분을 선택적으로 제거하여 제2콘택홀(10a)을 형성한다.Next, a second interlayer insulating film 10 is deposited on the entire structure, and a portion of the second interlayer insulating film 10 positioned on the P-MOSFET is selectively removed to form a second contact hole 10a.
또한, 상기 N-MOSFET상에 위치하는 제2층간절연막(10)부분과 그 아래에 있는 제1층간절연막(8)을 동시에 선택적으로 제거하여 상기 N-MOSFET의 불순물영역을 노출시키는 제3콘택홀(10b)을 각각 형성한다.In addition, a third contact hole exposing the impurity region of the N-MOSFET by selectively removing the portion of the second interlayer insulating film 10 positioned on the N-MOSFET and the first interlayer insulating film 8 below it simultaneously. 10b is formed respectively.
이어서, 상기 제2콘택홀(10a)과 제3콘택홀(10b)을 포함한 전체 구조의 상부에 도전성물질을 증착하고 이를 선택적으로 패터닝하여 배선(11)을 형성하므로써 도 2 와 같은 반도체소자의 인버터회로를 구성한다.Subsequently, the conductive material is deposited on the upper part of the entire structure including the second contact hole 10a and the third contact hole 10b and selectively patterned to form the wiring 11 to form the wiring 11. Configure the circuit.
상기한 바와같이, 종래 기술에 따른 반도체소자의 인버터 회로의 제조방법에 있어서는 다음과 같은 문제점이 있다.As described above, the manufacturing method of the inverter circuit of the semiconductor device according to the prior art has the following problems.
종래 기술에 있어서는, 반도체소자의 제조에 있어서 반도체소자의 크기가 줄어듬에 따라 인버터 회로 제조시에 들어가는 플러그의 콘택 마진이 없어, 즉 높은 에스펙트비에 따른 공정상의 어려움이 있고, 이로인해 제품의 생산수율이 떨어져 원가 상승의 요인이 된다.In the prior art, as the size of a semiconductor device decreases in the manufacture of the semiconductor device, there is no contact margin of the plug which enters during the manufacture of the inverter circuit, that is, there is a difficulty in the process due to the high aspect ratio, thereby producing a product. Yield drops, which contributes to cost hikes.
또한, 종래기술에 있어서는, 인버터회로를 기판상에 수평방향으로 형성하기 때문에 반도체소자가 차지하는 면적이 증가되므로 소자의 고집적화에 적합하지가 않다.Further, in the prior art, since the inverter circuit is formed in the horizontal direction on the substrate, the area occupied by the semiconductor element is increased, which is not suitable for high integration of the element.
이에, 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 반도체소자의 인버터회로 형성시의 높은 에스펙트비의 플러그 형성공정의 어려움을 해결하고자한 반도체소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, to provide a method for manufacturing a semiconductor device to solve the difficulty of forming a high aspect ratio plug when forming an inverter circuit of the semiconductor device. There is a purpose.
또한, 본 발명의 다른 목적은, 반도체소자의 인버터회로 형성시에 인버터가 차지하는 면적을 줄여 소자의 고집적화에 적합하도록한 반도체소자의 제조방법을 제공함에 있다.In addition, another object of the present invention is to provide a method for manufacturing a semiconductor device in which the area occupied by the inverter when forming the inverter circuit of the semiconductor device is suitable for high integration of the device.
상기 목적을 달성하기 위한 본 발명은, N형 실리콘기판상에 활성영역과 필드영역을 정의해 주는 소자분리막을 형성하는 공정과;The present invention for achieving the above object is a process for forming a device isolation film defining an active region and a field region on the N-type silicon substrate;
상기 N형 실리콘기판의 활성영역상에 게이트산화막과 그 위에 워드라인을 형성하는 공정과;Forming a gate oxide film and a word line thereon on an active region of the N-type silicon substrate;
상기 게이트산화막과 워드라인의 측면에 워드라인스페이서를 형성하는 공정과;Forming a word line spacer on side surfaces of the gate oxide film and the word line;
상기 실리콘기판의 노출된 부분에 P형 불순물을 임플란트하여 소오스와 드레인영역을 형성하여 P-MOSFET를 형성하는 공정과;Implanting a P-type impurity in the exposed portion of the silicon substrate to form a source and a drain region to form a P-MOSFET;
상기 전체 구조의 상부에 제1층간절연막을 증착하고, 이를 선택적으로 제거하여 상기 소오스와 드레인영역을 노출시키는 콘택홀을 형성하는 공정과;Depositing a first interlayer insulating film over the entire structure and selectively removing the interlayer insulating film to form a contact hole exposing the source and drain regions;
상기 제1콘택홀을 포함한 전체 구조의 상부에 P형 폴리실리콘층을 증착하고, 이를 에치백(etch back)하여 평탄화시켜 상기 콘택홀내에 콘택플러그를 형성하는 공정과;Depositing a P-type polysilicon layer on top of the entire structure including the first contact hole, and etching back to form a contact plug in the contact hole;
상기 전체 구조의 상부에 절연막을 증착한후, 이를 패터닝하여 폴리실리콘층패턴을 형성하는 공정과;Depositing an insulating film on top of the entire structure, and then patterning the insulating film to form a polysilicon layer pattern;
상기 폴리실리콘층패턴상에 게이트산화막과 워드라인을 형성하는 공정과;Forming a gate oxide film and a word line on the polysilicon layer pattern;
상기 게이트산화막과 워드라인의 측면에 워드라인스페이서를 형성하는 공정과;Forming a word line spacer on side surfaces of the gate oxide film and the word line;
상기 폴리실리콘층패턴의 노출된 부분에 N형 불순물을 인플란트하여 소오스와 드레인영역을 형성하여 N-MOSFET를 형성하는 공정;Implanting an N-type impurity in the exposed portion of the polysilicon layer pattern to form a source and a drain region to form an N-MOSFET;
상기 전체구조상부에 제2층간절연막을 증착하여 평탄화시킨후 이를 선택적으로 제거하여 상기 콘택플러그를 노출시키는 배선콘택을 형성하는 공정과;Depositing and planarizing a second interlayer insulating film on the entire structure, and selectively removing the interlayer insulating film to form a wiring contact exposing the contact plug;
상기 배선콘택과 전체 구조의 상부에 도전성물질을 증착하고 이를 패터닝하여 배선을 형성하는 공정을 포함하여 구성되는 것을 특징으로한다.And forming a wiring by depositing and patterning a conductive material on the wiring contact and the entire structure.
도 1 은 종래 기술에 따른 반도체소자의 인버터회로 형성공정을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a process of forming an inverter circuit of a semiconductor device according to the prior art.
도 2 는 일반적인 반도체소자의 인버터회로 구성도를 나타낸 회로도이다.2 is a circuit diagram showing a configuration diagram of an inverter circuit of a general semiconductor device.
도 3 내지 6 는 본 발명에 따른 반도체소자의 인버터회로 형성공정을 설명하기 위한 단면도이다.3 to 6 are cross-sectional views illustrating a process of forming an inverter circuit of a semiconductor device according to the present invention.
＜도면의주요부분에대한부호의설명＞<Description of the symbols for the main parts of the drawings>
21 : 실리콘기판 22 : 소자분리막21 silicon substrate 22 device isolation film
23, 32 : 게이트산화막 24, 33 : 워드라인23, 32: gate oxide film 24, 33: word line
25, 34 : 워드라인스페이서 26, 35 : 불순물영역25, 34: word liner 26, 35: impurity region
27 : 제1층간 절연막 28 : 제1콘택홀27: first interlayer insulating film 28: first contact hole
29a, 29b : 콘택플러그 30 : 절연막29a, 29b: contact plug 30: insulating film
31 : 폴리실리콘층패턴 36 : 제2층간 절연막31 polysilicon layer pattern 36 second interlayer insulating film
37a, 37b, 37c : 제2콘택홀 38 : 배선37a, 37b, 37c: second contact hole 38: wiring
이하, 본 발명에 따른 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3 내지 6 는 본 발명에 따른 반도체소자의 인버터회로 형성공정을 설명하기 위한 공정단면도이다.3 to 6 are process cross-sectional views for explaining a process of forming an inverter circuit of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 인버터 회로 형성방법은, 도 3 에 도시된 바와같이, P-MOSFET를 형성하기 위해 먼저 N형 실리콘기판(21)상에 활성영역과 필드영역을 정의해 주는 소자분리막(22)을 형성하고, 활성영역상에 게이트산화막물질과 P형 폴리실리콘층을 증착한다.In the method of forming an inverter circuit of a semiconductor device according to the present invention, as shown in FIG. 3, a device isolation film defining an active region and a field region on an N-type silicon substrate 21 is first formed to form a P-MOSFET. 22), and deposits a gate oxide material and a P-type polysilicon layer on the active region.
그다음, 상기 게이트산화막과 P형 폴리실리콘층을 워드라인용 마스크(미도시)로 선택적으로 패터닝하여 게이트산화막(23)과 워드라인(24)을 형성한다.Next, the gate oxide film and the P-type polysilicon layer are selectively patterned with a word line mask (not shown) to form the gate oxide film 23 and the word line 24.
이어서, 상기 게이트산화막(23)과 워드라인(24)의 측면에 스페이서(25)를 형성하고, 상기 실리콘기판(21)의 노출된 부분에 P형 불순물을 임플란트하여 소오스/ 드레인용 불순물영역(26)을 형성하여 P-MOSFET를 완성한다.Subsequently, spacers 25 are formed on the side surfaces of the gate oxide layer 23 and the word line 24, and P-type impurities are implanted in the exposed portions of the silicon substrate 21 to thereby source / drain impurity regions 26. ) To complete the P-MOSFET.
이어서, 도 4 에 도시된 바와같이, 상기 전체 구조의 상부에 제1층간절연막(27)을 증착하고, 이를 선택적으로 제거하여 상기 불순물영역(26)을 노출시키는 제1콘택홀(28)을 형성한다.Subsequently, as shown in FIG. 4, the first interlayer insulating layer 27 is deposited on the entire structure and selectively removed to form the first contact hole 28 exposing the impurity region 26. do.
그다음, 상기 제1콘택홀(28)을 포함한 전체 구조의 상부에 P형 폴리실리콘층을 증착하고, 이를 에치백(etch back)하여 평탄화시켜 상기 제1콘택홀(28)내에 콘택플러그(29a)(29b)을 형성한다.Next, a P-type polysilicon layer is deposited on the entire structure including the first contact hole 28, etched back to planarize the contact plug 29a in the first contact hole 28. 29b is formed.
이어서, 도 5 에 도시된 바와같이, 상기 전체 구조의 상부에 절연막(30)을 증착한후, 그 위에 폴리실리콘층을 증착하고 재결정화 공정과 열적 공정을 진행하여 TFT 기판으로 사용될 부분을 제외한 나머지 부분을 제거하여 폴리실리콘층패턴(31)을 형성한다.Subsequently, as shown in FIG. 5, after the insulating film 30 is deposited on the entire structure, a polysilicon layer is deposited thereon, followed by recrystallization and thermal processes, except for portions to be used as TFT substrates. The portion is removed to form the polysilicon layer pattern 31.
상기 폴리실리콘층패턴(31) 상에 게이트산화물질과 N형 폴리실리콘층을 증착하고, 이를 워드라인패턴용 마스크(미도시)를 사용하여 선택적으로 제거하여 게이트산화막(32)와 워드라인(33)을 형성한다.A gate oxide material and an N-type polysilicon layer are deposited on the polysilicon layer pattern 31 and selectively removed using a mask for a word line pattern (not shown) to form the gate oxide layer 32 and the word line 33. ).
그다음, 상기 게이트산화막(32)와 워드라인(33)의 측면에 워드라인스페이서(34)를 형성하고, 상기 폴리실리콘층패턴(31)의 노출된 부분에 N형 불순물을 인플란트하여 소오스/드레인용 N형 불순물영역(35)을 형성하여 N-MOSFET를 완성한다.Next, a word liner 34 is formed on the side surfaces of the gate oxide layer 32 and the word line 33, and an N-type impurity is implanted into the exposed portion of the polysilicon layer pattern 31 for source / drain. An N-type impurity region 35 is formed to complete an N-MOSFET.
이어서, 도 6 에 도시된 바와같이, 상기 전체 구조의 상부에 제2층간절연막(36)을 증착하여 평탄화시킨다.Subsequently, as shown in FIG. 6, a second interlayer insulating film 36 is deposited and planarized on top of the entire structure.
그다음, 상기 제2층간절연막(36)을 선택적으로 제거하여 상기 콘택플러그(29a)와 상기 N형불순물영역(35)중 하나의 일부분을 노출시키는 제 1 배선콘택(37a)과, 상기 N형 불순물영역(35)의 나머지 하나를 노출시키는 제 2 배선콘택(37b)과, 상기 콘택플러그(29b)를 노출시키는 제 3 배선콘택(37c)을 각각 형성한다.Next, the first interconnection contact 37a for selectively removing the second interlayer insulating layer 36 to expose a portion of the contact plug 29a and the N-type impurity region 35 and the N-type impurity A second wiring contact 37b exposing the other one of the regions 35 and a third wiring contact 37c exposing the contact plug 29b are formed, respectively.
이어서, 상기 제1, 제2, 제3 배선콘택(37a)(37b)(37c)을 포함한 전체 구조의 상부에 배선용 도전성물질을 증착하고 이를 배선용 마스크(미도시)를 사용하여 선택적으로 제거하여 배선(38)을 형성하므로써 반도체소자의 인버터 회로 형성을 완성한다.Subsequently, a wiring conductive material is deposited on the entire structure including the first, second, and third wiring contacts 37a, 37b, 37c, and selectively removed using a wiring mask (not shown). The formation of the inverter 38 completes the inverter circuit formation of the semiconductor element.
이때, 상기 배선(38)중 하나는 상기 제1배선(37a)을 통해 N-MOSFET와 P-MOSFET를 연결하게 된다.At this time, one of the wires 38 connects the N-MOSFET and the P-MOSFET through the first wire 37a.
한편, 상기에서 적층 트랜지스터를 이용함에 있어서 N-MOS와 P-MOS 트랜지스터의 형성순서를 바꾸어 활용할 수도 있다.On the other hand, when using the stacked transistors, the formation order of the N-MOS and P-MOS transistors may be changed.
상기한 바와같이, 본 발명에 따른 반도체장치의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the manufacturing method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 반도체소자의 인버터회로 형성시에 트랜지스터(TFT) 구조를 이용하여 적층구조의 인버터회로를 형성하므로써 종래기술에 있어서의 높은 에스펙트비로 인한 공정의 어려움을 줄일 수 있을뿐만 아니라 인버터회로를 기판상에 수직방향으로 적층구조로 형성하기 때문에 종래보다 반도체소자가 차지하는 면적을 최소화시킬 수 있어 원가 절감효과도 기대할 수 있다.In the present invention, by forming a multilayer inverter circuit using a transistor (TFT) structure at the time of forming an inverter circuit of a semiconductor device, not only the difficulty of the process due to the high aspect ratio in the prior art but also the inverter circuit can be reduced. Since it is formed in a vertical stacked structure on the substrate it can be minimized the area occupied by the semiconductor device compared to the conventional cost reduction effect can also be expected.
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| KR100866711B1 (en) * | 2002-07-18 | 2008-11-03 | 주식회사 하이닉스반도체 | Manufacturing method for invertor of semiconductor device |
| KR100866734B1 (en) * | 2002-07-18 | 2008-11-03 | 주식회사 하이닉스반도체 | Manufacturing method for invertor of semiconductor device |
| WO2017213644A1 (en) * | 2016-06-08 | 2017-12-14 | Intel Corporation | Monolithic integration of back-end p-channel transistor with iii-n n-channel transistor |
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| KR100678462B1 (en) | 2004-11-16 | 2007-02-02 | 삼성전자주식회사 | Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same |
| KR100655664B1 (en) * | 2005-07-08 | 2006-12-08 | 삼성전자주식회사 | Stacked semiconductor device and method of manufacturing the same |
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| JPS6240716A (en) * | 1985-08-15 | 1987-02-21 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
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| JPS63137450A (en) * | 1986-11-28 | 1988-06-09 | Fujitsu Ltd | Laminated type cmos gate array |
| JPH01264254A (en) * | 1988-04-15 | 1989-10-20 | Agency Of Ind Science & Technol | Manufacture of laminate type semiconductor device |
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| KR100866711B1 (en) * | 2002-07-18 | 2008-11-03 | 주식회사 하이닉스반도체 | Manufacturing method for invertor of semiconductor device |
| KR100866734B1 (en) * | 2002-07-18 | 2008-11-03 | 주식회사 하이닉스반도체 | Manufacturing method for invertor of semiconductor device |
| WO2017213644A1 (en) * | 2016-06-08 | 2017-12-14 | Intel Corporation | Monolithic integration of back-end p-channel transistor with iii-n n-channel transistor |
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