KR100248811B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor device manufacturing method.

2. Technical problem to be solved by the invention

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of maintaining the maximum performance of a logic circuit unit and a DRAM cell and reducing a step in forming the logic circuit unit and the DRAM cell on one chip.

3. Summary of the Solution of the Invention

In forming a semiconductor device, an integrated circuit (a logic circuit unit and a DRAM cell) may be formed on the top and bottom of a wafer by using an SOI process to increase the degree of integration.

4. Important uses of the invention

Used in semiconductor device manufacturing process.

Description

Semiconductor device manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing process, and more particularly, to a semiconductor device manufacturing process for fabricating different types of integrated circuits on a single substrate using a silicon on insulator (SOI) substrate.

A general SOI technique is a technique on a single crystal silicon thin film having a thickness of 1 μm or less on an insulating film such as sapphire. Since the devices are formed on the insulating film, CMOS technology can improve the latchup problem, reduce parasitic capacitance, and induce high integration of the device.

1A to 1G are cross-sectional views of a semiconductor device manufacturing process having a general SOI substrate, to briefly describe a general SOI process.

First, as shown in FIG. 1A, a single crystal silicon thin film 12 doped with n-type impurities is formed on the buried insulating film 11.

Next, as shown in FIG. 1B, the silicon thin film 12 is etched to expose the insulating film 11, thereby forming n-type single crystal silicon islands that are insulated from each other.

Next, as shown in FIG. 1C, the photoresist pattern 101 is formed with a mask (not shown) for forming a p-type single crystal silicon island, and ion implantation of p-type impurities such as boron is used as an ion implantation barrier. P-type single crystal silicon islands 13 are formed.

Next, as shown in FIG. 1D, a gate oxide film and a polysilicon film are formed on the previously formed n-type and p-type single crystal silicon islands 12 and 13 to pattern the gate electrode 14.

Next, as shown in Figs. 1E and 1F, a source for n-channel formation in the p-type single crystal silicon island 13 using a mask (not shown) for forming the p-type single crystal silicon island first used is shown. A drain 15 is formed, and a source / drain 16 for p-channel formation is formed in the n-type single crystal silicon island 12.

Finally, as shown in FIG. 1G, the silicon oxide film 17 is formed as a whole, and then a metal contact is formed by an etching process, and the metal wiring 18 process is performed.

Recently, in the manufacture of integrated circuits, a technique for implementing DRAM and logic circuits in one chip is used. The advantages of the chips manufactured in this way are explained in terms of performance and functional aspects. In the former case, the width of the bus connecting the DRAM and the logic circuit portion can be widened, so that a high-performance chip having a band width exceeding 1G byte / s can be obtained. In the latter case, custom semiconductors, etc., which have been conventionally processed by hardware, can be processed by software in such a chip, thereby ensuring the versatility.

Conventionally, devices are formed only on the wafer in order to implement DRAM and logic circuits in one chip. Therefore, during the DRAM forming process and the logic circuit forming process, the process order must be specified selectively. The DRAM and logic circuit parts have advantages and disadvantages depending on the degree of integration, the design environment, and the cost. You should use the process that has the best point at the expense of the performance of any one of the logic circuits separately.

In addition, problems in the metal wiring process and the photolithography process are caused by the step difference between the DRAM and the logic circuit.

SUMMARY OF THE INVENTION The present invention devised to solve the above-mentioned problems is a semiconductor that can maintain the performance of the logic circuit portion and the DRAM cell to the maximum and reduce the process step in the process of forming the logic circuit portion and the DRAM cell on one chip. It is an object of the present invention to provide a method for manufacturing a device.

1A to 1G are cross-sectional views of a semiconductor device manufacturing process having a general SOI substrate,

2A through 2F are cross-sectional views of a semiconductor device manufacturing process, according to an embodiment of the present invention;

3A to 3G are cross-sectional views of a semiconductor device manufacturing process in accordance with another embodiment of the present invention.

* Description of symbols for the main parts of the drawings.

31, 38: silicon substrate 36: DRAM cell portion

32: buried oxide film 37: oxide film

33: single crystal silicon film 39: logic circuit portion

34: photoresist

35: polysilicon

In order to achieve the above object, the semiconductor device manufacturing method of the present invention comprises the steps of: forming a buried oxide film, a first silicon thin film on the first semiconductor substrate; Forming a first integrated circuit on the silicon thin film; Forming a second semiconductor substrate after performing a planarization process on the entire structure; Replacing the front and rear surfaces of the wafer on which the second semiconductor substrate is formed, and etching the entire surface of the first semiconductor substrate to form a second silicon thin film; And forming a second integrated circuit on the second silicon thin film.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A through 2F are cross-sectional views of a semiconductor device fabrication process according to an embodiment of the present invention. First, as shown in FIG. 2A, the buried oxide film 22 and the single crystal silicon film are sequentially formed on the first silicon substrate 21. Laminated. In the conventional SOI technique, a word line, a bit line, and a capacitor charge storage electrode are formed on a single crystal silicon film, and then a DRAM cell portion 23 insulated with an insulating film is formed.

Next, as shown in FIG. 2B, the oxide film 24 is formed to reduce the step difference between the cell region and the peripheral circuit region, and then the device is planarized by chemical mechanical polishing.

Next, as shown in FIG. 2C, the first silicon substrate is formed by forming a second silicon substrate 25 to be used as a support substrate on the entire structure, and changing the wafer which has been processed as described above up and down. (21) face up.

Next, as shown in FIG. 2D, the first silicon substrate 21 positioned at the top is etched to have a suitable thickness by chemical-mechanical polishing.

Next, as shown in Fig. 2E, the logic circuit portion 26 is formed on the single crystal silicon layer of the first silicon substrate 21, and an interlayer insulating film is formed.

3A to 3G are cross-sectional views of a semiconductor device fabrication process according to another embodiment of the present invention. First, as shown in FIG. 3A, an oxide buried film 32 and a single crystal silicon film are formed on a first silicon substrate 31. (33) is laminated one by one.

Next, as shown in FIG. 3B, a photoresist pattern 34 is formed on the single crystal silicon film 33.

Next, as shown in FIG. 3C, the single crystal silicon film 33 and the buried oxide film 32 are etched using the photoresist pattern 34 as an etching barrier, and the silicon substrate 31 is partially etched to form trenches. do. The pre-formed trench is completely filled while the polysilicon film 35 is formed over the entire structure.

Next, as shown in FIG. 3D, the polysilicon film 35 formed on the single crystal silicon film 33 is completely removed from the polysilicon film 35 on the single crystal silicon film 33 by chemical-mechanical polishing. By removing the polysilicon 35 remaining only inside the formed trench.

Next, as shown in FIG. 3E, a word line, a bit line, and a capacitor charge storage electrode are formed on the single crystal silicon film 33 by a conventional SOI technique, and then a DRAM cell portion 36 insulated with an insulating film is formed. . Next, after forming the oxide film 37 which reduces the step between the cell region and the peripheral circuit region, the device is planarized by chemical-mechanical polishing.

Next, as shown in FIG. 3F, the first silicon substrate is formed by forming a second silicon substrate 38 to be used as a support substrate over the entire structure, and changing the bottom and top of the wafer having the above-described process. (31) face up.

Next, as illustrated in FIG. 3G, the first silicon substrate 31 is etched by chemical-mechanical polishing of the first silicon substrate 31 positioned at the top thereof, where the pre-formed polysilicon 35 is exposed. The viewpoint is performed as an etch stop. A logic circuit 39 is formed on the single crystal silicon layer of the first silicon substrate 31, and an interlayer insulating film is formed.

According to the present invention made as described above, different types of integrated circuits may be formed on and under one wafer, and may be formed by a process unique to each integrated circuit. Therefore, it is not necessary to develop a new process for mixing integrated circuits, and it is possible to overcome a step problem between the DRAM and the logic circuit unit. In addition, the use of trenches embedded in polysilicon used in other embodiments facilitates thickness control of the first silicon substrate by acting as a stop layer during the chemical-mechanical polishing process in subsequent processes.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention as described above, in the process of forming the logic circuit portion and the DRAM cell on one chip, each integrated circuit (logical circuit portion and the DRAM cell) is formed on the upper and lower portions of the wafer, and each process can be performed completely separately. Therefore, the advantages of each integrated circuit can be maintained. In addition, by forming an integrated circuit in a multi-layer, thereby reducing the area of the entire chip to improve the degree of integration.

Claims (3)

Sequentially forming a buried oxide film and a first silicon thin film on the first semiconductor substrate; Forming a first integrated circuit on the silicon thin film; Forming a second semiconductor substrate after performing a planarization process on the entire structure; Replacing the front and rear surfaces of the wafer on which the second semiconductor substrate is formed, and etching the first semiconductor substrate to form a second silicon thin film; And Forming a second integrated circuit on the second silicon thin film A semiconductor device forming method comprising a. The method of claim 1, After forming the first silicon thin film Forming a photoresist pattern to etch the first silicon thin film and the buried oxide film and to form a trench in the first semiconductor substrate; And embedding polysilicon in the trench. The method according to claim 1 or 2, And the first or second silicon thin film is formed of single crystal silicon.

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