JPH1041511A - Soi wafer and semiconductor integrated circuit device using the wafer and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify and minimize a device structure of an semiconductor integrated circuit device using an SOI(silicon on insulator) wafer. SOLUTION: An n type semiconductor region 3 for wiring having a higher impurity concentration than a semiconductor substrate 1 for a base and a p type semiconductor region 5 are formed at a selected region of the semiconductor substrate 1 for a base of an SOI wafer in an integrated circuit device. And a manufacturing method for the semiconductor integrated circuit device using the SOI wafer is composed of after forming semiconductor elements on a semiconductor substrate 7 for element molding and of forming a wiring layer 22 and so on for semiconductor elements on the semiconductor substrate 7 for element molding.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI wafer, a semiconductor integrated circuit device using the same, and a method for manufacturing the same, and more particularly, to a semiconductor integrated circuit device having a multi-layer wiring structure using a SOI wafer. The present invention relates to a method for manufacturing an integrated circuit device.

[0002]

2. Description of the Related Art The present inventor has proposed SOI (Silico
n on Insulator) We studied the manufacturing technology of semiconductor integrated circuit devices using wafers. The following is a technique studied by the present inventors, and the outline is as follows.

That is, a MOSFET (Me) is formed on a semiconductor substrate for element formation, which is disposed on an insulating film of an SOI wafer.
A semiconductor integrated circuit device using an SOI wafer is manufactured by forming a semiconductor element such as a tal oxide semiconductor field effect transistor (Tx) and then forming a wiring layer on a semiconductor substrate for forming the element.

[0004] Incidentally, as a document which describes a manufacturing technique of a semiconductor integrated circuit device using an SOI wafer, for example, W. Mari published by Keigaku Shuppan Co., Ltd. "P321 to p3
25.

[0005]

However, the aforementioned S
A semiconductor integrated circuit device using an OI wafer has a structure in which a semiconductor element and its wiring layer are stacked above an insulating film of an SOI wafer. There is a problem that the structure of the element and the wiring layer is multi-layered, and the vertical structure of the semiconductor integrated circuit device is complicated.

Further, as the manufacturing technology of the semiconductor integrated circuit device becomes finer, the structure of the semiconductor element and the wiring layer is multi-layered, and the vertical structure of the semiconductor integrated circuit device becomes complicated. Scale Integrated
(Circuit) It becomes difficult to ensure the flatness of the chip, the degree of freedom of the LSI manufacturing process is reduced, and it becomes difficult to manufacture an LSI having a fine structure.

Further, as the manufacturing technology of the semiconductor integrated circuit device becomes finer, the structures of the semiconductor element and the wiring layer are multi-layered, and the vertical structure of the semiconductor integrated circuit device is complicated. The influence of the formed parasitic capacitance and the parasitic MOSFET formed between each layer and the interface of the silicon region cannot be ignored, and the device design method and the like have become complicated.

An object of the present invention is to provide a semiconductor integrated circuit device using an SOI wafer, capable of simplifying and miniaturizing a device structure, and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In other words, the SOI wafer of the present invention has a wiring semiconductor region or a capacitor element having a higher impurity concentration than the base semiconductor substrate in a selective region of the base semiconductor substrate.

According to the semiconductor integrated circuit device of the present invention, the SO
A plurality of semiconductor elements are formed on a semiconductor substrate for element formation on an I wafer.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a plurality of semiconductor elements are formed on a semiconductor substrate for element formation on the SOI wafer, and a wiring layer of the semiconductor element is formed on the semiconductor substrate for element formation. And a step of performing

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) FIGS. 1 to 9 are sectional views showing a manufacturing process of a semiconductor integrated circuit device using an SOI wafer according to an embodiment of the present invention. The SOI wafer and the method of manufacturing the same according to the present embodiment, the semiconductor integrated circuit device using the SOI wafer, and the method of manufacturing the same will be specifically described with reference to FIG.

First, for example, a p-type silicon substrate to be a base semiconductor substrate 1 of an SOI wafer is prepared, and a photoresist film 2 is applied to the surface thereof by using a spin coating apparatus, and then, by using an exposure apparatus. The photoresist film 2 is patterned. Using the patterned photoresist film 2 as a mask, an n-type impurity such as phosphorus (P) is implanted into the base semiconductor substrate 1 with a high impurity concentration by an ion implantation method. Then, after removing the unnecessary photoresist film 2, the n-type impurity ion-implanted is thermally diffused to form n
A semiconductor region 3 of a mold is formed on the base semiconductor substrate 1 (FIG. 1). Since the n-type semiconductor region 3 for wiring contains an n-type impurity having a high impurity concentration, it can be a wiring layer having low resistance and excellent electric characteristics. Further, the n-type semiconductor region 3 for wiring is formed by the CMOS (Co
This is used as a wiring layer of an n-channel MOSFET of a simple metal oxide semiconductor (simplementary metal oxide semiconductor) device.

Next, after a photoresist film 4 is applied to the surface of the base semiconductor substrate 1 by using a spin coater,
The photoresist film 4 is patterned using an exposure device. Using the patterned photoresist film 4 as a mask, for example, boron (B) is formed on the base semiconductor substrate 1.
A p-type impurity such as is ion-implanted with a high impurity concentration by an ion implantation method. Thereafter, after removing the unnecessary photoresist film 4, the p-type impurity implanted is thermally diffused to form a p-type semiconductor region 5 for wiring on the base semiconductor substrate 1 (FIG. 2). ). Since the p-type semiconductor region 5 for wiring contains a high impurity concentration of p-type impurity, it can be a wiring layer having low resistance and excellent electrical characteristics. The p-type semiconductor region 5 for wiring is used as a wiring layer of a p-channel MOSFET of the CMOS semiconductor integrated circuit device of the present embodiment.

Then, after an insulating film 6 such as a silicon oxide film is formed on the surface of the base semiconductor substrate 1, an element forming semiconductor substrate 7 such as a p-type silicon substrate is bonded to the surface of the insulating film 6. After that, if necessary, the surface of the element forming semiconductor substrate 7 is polished to obtain an element forming semiconductor substrate 7 having a predetermined thickness and being flattened (FIG. 3).

According to the above-described manufacturing process, a semiconductor substrate for element formation is formed on a base semiconductor substrate 1 having an n-type semiconductor region 3 and a p-type semiconductor region 5 as wiring layers with an insulating film 6 interposed therebetween. 7 is formed,
The SOI wafer of this embodiment can be formed.

Next, contact holes 9 for the n-type semiconductor region 3 and the p-type semiconductor region 5 as wiring layers in the SOI wafer of the present embodiment are formed (FIG. 4). Specifically, after applying a photoresist film 8 to the surface of the SOI wafer of the present embodiment using a spin coater, an n-type wiring layer is formed by using a photolithography technique and a selective etching technique. Semiconductor region 3 and p
A contact hole 9 having a deep groove structure in contact with the semiconductor region 5 of the mold is formed. Thereafter, after removing the unnecessary photoresist film 8, a conductive material is buried in the contact hole 9 to form a contact plug 10 (FIG. 5). The contact plug 10 has a pillar shape, that is, a pillar, and is formed by a sputtering method or a CV method using a material such as a refractory metal such as tungsten or titanium or conductive polycrystalline silicon.
It is formed using a D (Chemical Vapor Deposition) method.

Thereafter, a field insulating film 11 as an insulating film for element isolation is formed in a selective region of the element forming semiconductor substrate 7 by a thermal oxidation method (FIG. 6). Next, a p-type impurity such as boron is ion-implanted into the element forming semiconductor substrate 7 in a region where the p-channel MOSFET is to be formed by ion implantation to form a p-type semiconductor region 12. After that, a gate insulating film 13, a gate electrode 14, an insulating film 15 and a side wall insulating film 16 are formed in a region where an n-channel MOSFET and a p-channel MOSFET are to be formed. Semiconductor region 1
7 and a p-type semiconductor region 18 having a high impurity concentration as a source / drain of a p-channel MOSFET is formed (FIG. 7).

Next, an insulating film 19 such as a silicon oxide film is formed on the SOI wafer by using, for example, the CVD method. Thereafter, the n-type semiconductor region 17 as the source / drain of the n-channel MOSFET and the p-channel MOSFET
P-type semiconductor region 18 as source / drain of ET
After forming a contact hole, a contact plug 20 is formed by embedding a conductive material in the contact hole (FIG. 8). Specifically, a photoresist film is applied to the surface of the insulating film 19 by using a spin coating device, and then a contact hole having a deep groove structure is formed by using a photolithography technique and a selective etching technique.
Then, after removing the unnecessary photoresist film, a conductive material is buried in the contact hole, and the contact plug 20 is made of a material such as a refractory metal such as tungsten or titanium or a conductive polycrystalline silicon. And formed by a sputtering method or a CVD method. As shown in FIG.
Zeros are formed to reduce the contact resistance.
FIG. 10 is a schematic plan view showing in perspective a plane near the cross-sectional area of the semiconductor integrated circuit device shown in FIG.

Thereafter, for example, CVD is performed on the SOI wafer.
An insulating film 21 such as a silicon oxide film is formed by using a method, a through hole is formed in the insulating film 21, and a conductive material is embedded in the through hole to form a wiring layer 22 (FIG. 9). . Specifically, after applying a photoresist film to the surface of the insulating film 21 using a spin coating device,
A through hole is formed using a photolithography technique and a selective etching technique. Then, after removing the unnecessary photoresist film, a conductive material is buried in the through holes, and the wiring layer 22 is made of a material such as a high melting point metal such as tungsten or titanium or a conductive polycrystalline silicon. And the sputtering method or C
It is formed using a VD method.

As another mode of forming the insulating film 21 and the wiring layer 22, after forming the wiring layer 22 made of a conductive material on the SOI wafer, the photolithography technique and the selective etching technique are used. After patterning of the wiring layer 22, a manufacturing process in which the insulating film 21 is formed and the surface thereof is polished and planarized as necessary can be employed.

Next, after a plurality of interlayer insulating films and upper wiring layers are formed on the wiring layer 22 as required, a surface protection film (for example, a silicon nitride film) is formed on the uppermost wiring layer. Thus, the manufacturing process of the semiconductor integrated circuit device is completed.

According to the above-described SOI wafer of the present embodiment, the base semiconductor substrate 1 under the insulating film 6 includes the n-type semiconductor region 3 and the p-type semiconductor region 5 as wiring layers. When forming a semiconductor element formed on the element forming semiconductor substrate 7 and its wiring layer,
Since the wiring layer formed on the base semiconductor substrate 1 can be used, the degree of freedom in the design specification of the wiring region of the semiconductor element is improved, and the multilayer structure of the wiring layer formed on the element forming semiconductor substrate 7 is reduced. Therefore, the device structure can be simplified and miniaturized.

Further, according to the semiconductor integrated circuit device using the SOI wafer and the method of manufacturing the same according to the present embodiment, the semiconductor device includes the n-type semiconductor region 3 and the p-type semiconductor region 5 as wiring layers. By using the SOI wafer having the base semiconductor substrate 1, when forming the semiconductor elements formed on the element formation semiconductor substrate 7 and the wiring layers thereof, the wiring layers formed on the base semiconductor substrate 1 can be removed. Since it can be used, the degree of freedom in the design specification of the wiring region of the semiconductor element is improved, and the multilayer structure of the wiring layer formed on the element forming semiconductor substrate 7 can be reduced. Therefore, the area of the semiconductor element can be reduced, and the flatness of the wiring layer formed on the element forming semiconductor substrate 7 can be improved, and a high-performance semiconductor integrated circuit device can be manufactured using a simple manufacturing process. be able to.

(Embodiment 2) FIGS. 11 to 18 are sectional views showing a process of manufacturing a semiconductor integrated circuit device using an SOI wafer according to another embodiment of the present invention. The SOI wafer and the method of manufacturing the same according to the present embodiment, the semiconductor integrated circuit device using the SOI wafer, and the method of manufacturing the same will be specifically described with reference to FIG.

First, for example, a p-type silicon substrate which is to be a base semiconductor substrate 1 in an SOI wafer is prepared, and a photoresist film 2 is applied to the surface thereof by using a spin coating device, and then by using an exposure device. The photoresist film 2 is patterned. Using the patterned photoresist film 2 as a mask, a deep groove 23 is formed in the base semiconductor substrate 1 by using a selective etching method. Then, after the unnecessary photoresist film 2 is removed, the groove 23 is removed.
An insulating film 24 such as a silicon oxide film is formed on the side wall of the substrate by using, for example, a CVD method (FIG. 11). The insulating film 24 is used as an insulating film of a capacitor.

Next, the groove 23 in which the insulating film 24 is formed
A contact plug 25 is formed by burying a conductive material in the contact plug 25. The contact plug 25 has a columnar shape,
It is a pillar and is formed by a sputtering method or a CVD method using a material such as a refractory metal such as tungsten or titanium or conductive polycrystalline silicon. The contact plug 25 serves as one electrode of the capacitive element, and the region of the base semiconductor substrate 1 in contact with the insulating film 24 as the insulating film of the capacitive element is used as the other electrode of the capacitive element. I have. Further, the capacitor of this embodiment is a DRAM (Dynamic Random Accelerator).
s Memory). After that, a photoresist film 4 is applied to the surface of the base semiconductor substrate 1 by using a spin coating device, and then the photoresist film 4 is patterned by using an exposure device. Using the patterned photoresist film 4 as a mask, an n-type impurity such as phosphorus is ion-implanted with a high impurity concentration by an ion implantation method. Then, after the unnecessary photoresist film 4 is removed, the ion-implanted n-type impurity is thermally diffused to form an n-type semiconductor region 3 for wiring on the base semiconductor substrate 1 (FIG. 12). ). Since the n-type semiconductor region 3 for wiring contains an n-type impurity having a high impurity concentration, it can be a wiring layer having low resistance and excellent electric characteristics. Further, the n-type semiconductor region 3 for wiring is used as a wiring layer (bit line) of the DRAM of the present embodiment.

Next, after an insulating film 6 such as a silicon oxide film is formed on the surface of the base semiconductor substrate 1, an element forming semiconductor substrate 7 such as a p-type silicon substrate is attached to the surface of the insulating film 6. After the alignment, the surface of the element forming semiconductor substrate 7 is polished, if necessary, to obtain an element forming semiconductor substrate 7 having a predetermined thickness and being flattened (FIG. 13).

According to the above-described manufacturing process, an element forming semiconductor substrate 7 is formed on a base semiconductor substrate 1 having a capacitor and an n-type semiconductor region 3 as a wiring layer with an insulating film 6 interposed therebetween. With this structure, the SOI wafer of this embodiment can be formed.

Next, a contact hole 25 for the contact plug 25 and the n-type semiconductor region 3 in the SOI wafer of the present embodiment is formed (FIG. 14). Specifically, after applying a photoresist film 8 to the surface of the SOI wafer of the present embodiment using a spin coater, the contact plug 25 and the n-type are etched using a photolithography technique and a selective etching technique. A contact hole 9 having a deep groove structure in contact with the semiconductor region 3 is formed. Then, after removing the unnecessary photoresist film 8, a conductive material is embedded in the contact hole 9 to form a contact plug 10 (FIG. 15). The contact plug 10 has a pillar shape, that is, a pillar, and is formed by a sputtering method or a CVD method using a material such as a high melting point metal such as tungsten or titanium or conductive polycrystalline silicon.

Thereafter, a field insulating film 11 as an insulating film for element isolation is formed in a selective area of the semiconductor substrate 7 for element formation by a thermal oxidation method (FIG. 16). Next, after forming a gate insulating film 13, a gate electrode 14, an insulating film 15 and a sidewall insulating film 16 in a region where an n-channel MOSFET is to be formed, a high impurity concentration n-type semiconductor as a source / drain of the n-channel MOSFET is formed. Area 1
7 (FIG. 17).

Next, an insulating film 19 such as a silicon oxide film is formed on the SOI wafer by using, for example, the CVD method. Thereafter, the gate electrode 14 of the n-channel MOSFET
After forming a contact hole, a conductive material is buried in the contact hole to form a contact plug 20. Specifically, a photoresist film is applied to the surface of the insulating film 19 by using a spin coating device, and then a contact hole having a deep groove structure is formed by using a photolithography technique and a selective etching technique. Then, after removing the unnecessary photoresist film, a conductive material is buried in the contact hole, and the contact plug 20 is made of a material such as a refractory metal such as tungsten or titanium or a conductive polycrystalline silicon. And formed by a sputtering method or a CVD method.

Thereafter, for example, CVD is performed on the SOI wafer.
An insulating film 21 such as a silicon oxide film is formed by using a method, a through hole is formed in the insulating film 21, and a conductive material is embedded in the through hole to form a wiring layer (DR).
A wiring layer 22 used as an AM word line is formed (FIG. 18). Specifically, after applying a photoresist film to the surface of the insulating film 21 using a spin coating device, using a photolithography technique and a selective etching technique,
Form a through hole. Then, after removing the unnecessary photoresist film, a conductive material is buried in the through holes, and the wiring layer 22 is made of a material such as a high melting point metal such as tungsten or titanium or a conductive polycrystalline silicon. And sputtering or CVD
It is formed using a method.

As another mode for forming the insulating film 21 and the wiring layer 22, after forming the wiring layer 22 made of a conductive material on the SOI wafer, the photolithography technique and the selective etching technique are used. After patterning of the wiring layer 22, a manufacturing process in which the insulating film 21 is formed and the surface thereof is polished and planarized as necessary can be employed.

Next, after a plurality of interlayer insulating films and upper wiring layers are formed on the wiring layer 22 as necessary, a surface protective film such as a silicon nitride film is formed on the uppermost wiring layer. Thus, the manufacturing process of the semiconductor integrated circuit device is completed.

According to the SOI wafer of the present embodiment described above, since the base semiconductor substrate 1 under the insulating film 6 is provided with the capacitance element and the n-type semiconductor region 3 as the wiring layer, the element is formed. When the semiconductor element formed on the base semiconductor substrate 7 and its wiring layer are formed, the capacitor element and the wiring layer formed on the base semiconductor substrate 1 can be used, so that the device structure can be simplified and miniaturized.

According to the semiconductor integrated circuit device using the SOI wafer and the method of manufacturing the same according to the present embodiment, for example, the n-type semiconductor region 3 as a capacitor and a wiring layer used in a DRAM or the like is used. When the SOI wafer having the base semiconductor substrate 1 provided with the semiconductor device is used, the semiconductor element formed on the element formation semiconductor substrate 7 and the wiring layer thereof are formed on the base semiconductor substrate 1. Since the capacitor and the wiring layer which are used can be used, the formation of the capacitor in the region of the semiconductor substrate for element formation 7 and the wiring layer formed thereon can be reduced. Further, the degree of freedom in design specification of the wiring region of the semiconductor element formed on the semiconductor substrate 7 for element formation is improved, and the multilayer structure of the wiring layer formed on the semiconductor substrate 7 for element formation can be reduced. Accordingly, the area of the semiconductor element can be reduced, and the flatness of the wiring layer formed on the element forming semiconductor substrate 7 can be improved, and a high performance semiconductor integrated circuit device such as a DRAM can be manufactured by using a simple manufacturing process. Can be manufactured.

(Embodiment 3) FIGS. 19 to 23 are cross-sectional views showing steps of manufacturing an SOI wafer according to another embodiment of the present invention. Referring to FIG.
The wafer and its manufacturing method will be specifically described.

First, for example, a p-type silicon substrate serving as a base semiconductor substrate 1 in an SOI wafer is prepared, and a photoresist film 2 is coated on the surface thereof by using a spin coating device, and then by using an exposure device. The photoresist film 2 is patterned. Using the patterned photoresist film 2 as a mask, an n-type impurity such as phosphorus is ion-implanted into the base semiconductor substrate 1 with a high impurity concentration by an ion implantation method. Then, after removing the unnecessary photoresist film 2, the n-type impurity implanted is thermally diffused to form an n-type semiconductor region 3 for wiring on the base semiconductor substrate 1 (FIG. 1).
9). The n-type semiconductor region 3 for wiring is n-type with a high impurity concentration.
Since a type impurity is contained, a wiring layer having low resistance and excellent electric characteristics can be obtained.

Next, a photoresist film 4 is applied to the surface of the base semiconductor substrate 1 by using a spin coating apparatus.
The photoresist film 4 is patterned using an exposure device. Using the patterned photoresist film 4 as a mask, a p-type impurity such as boron is ion-implanted into the base semiconductor substrate 1 with a high impurity concentration by an ion implantation method. Thereafter, after removing the unnecessary photoresist film 4, the p-type impurity implanted by ions is thermally diffused to form a p-type semiconductor region 5 for the capacitor on the base semiconductor substrate 1 (FIG. 20). In this case, the capacitance element of the present embodiment uses a pn junction capacitance between the n-type semiconductor region 3 and the p-type semiconductor region 5.

Then, after an insulating film 6 such as a silicon oxide film is formed on the surface of the base semiconductor substrate 1, an element forming semiconductor substrate 7 such as a p-type silicon substrate is bonded to the surface of the insulating film 6. After that, if necessary, the surface of the element forming semiconductor substrate 7 is polished to obtain an element forming semiconductor substrate 7 having a predetermined thickness and being flattened (FIG. 2).
1).

According to the above-described manufacturing process, the capacitance element using the capacitance of the pn junction of the n-type semiconductor region 3 as a wiring layer and the p-type semiconductor region 5 forming a pn junction with the n-type semiconductor region is provided. With the structure in which the element forming semiconductor substrate 7 is formed on the base semiconductor substrate 1 with the insulating film 6 interposed therebetween, the SOI wafer of the present embodiment can be formed.

Next, a contact hole 9 for the n-type semiconductor region 3 as a wiring layer in the SOI wafer of the present embodiment is formed (FIG. 22). Specifically, after applying a photoresist film 8 to the surface of the SOI wafer of the present embodiment using a spin coater, an n-type wiring layer is formed by using a photolithography technique and a selective etching technique. A contact hole 9 having a deep groove structure in contact with the semiconductor region 3 is formed. Then, after removing the unnecessary photoresist film 8, a conductive material is buried in the contact hole 9 to form a contact plug 10 (FIG. 23). The contact plug 10 has a pillar shape, that is, a pillar, and is formed by a sputtering method or a CVD method using a material such as a high melting point metal such as tungsten or titanium or conductive polycrystalline silicon.

According to the above-described SOI wafer of this embodiment, the base semiconductor substrate 1 under the insulating film 6 is provided with the capacitance element using the pn junction capacitance and the n-type semiconductor region 3 as the wiring layer. With this configuration, when forming a semiconductor element formed on the element forming semiconductor substrate 7 and a wiring layer thereof, the capacitor element and the wiring layer formed on the base semiconductor substrate 1 can be used, thereby simplifying the device structure. And miniaturization.

According to the semiconductor integrated circuit device using the SOI wafer and the method of manufacturing the same according to the present embodiment, the base semiconductor substrate including the capacitor and the n-type semiconductor region 3 as a wiring layer By using the SOI wafer having the number 1, the capacitance element and the wiring layer can be used for a semiconductor integrated circuit device such as a DRAM. Therefore, effects similar to those of the semiconductor integrated circuit device of the second embodiment and the method of manufacturing the same can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, when a wiring layer composed of a semiconductor region is formed on a base semiconductor substrate in an SOI wafer, an SOI wafer in which an element formation semiconductor substrate is formed on a base semiconductor substrate via an insulating film. Impurities may be ion-implanted into the base semiconductor substrate below the insulating film from the surface of the element formation semiconductor substrate by an ion implantation method to form a high impurity concentration semiconductor region for wiring.

As a semiconductor element formed on a semiconductor substrate for element formation in an SOI wafer, MOSFE is used.
T, CMOSFET, bipolar transistor or M
B combining OSFET and bipolar transistor
An embodiment in which various semiconductor elements such as an iMOS or BiCMOS structure are combined can be adopted.

Further, as a semiconductor element formed on a semiconductor substrate for element formation on an SOI wafer, a DRAM,
It can be an embodiment of a semiconductor element forming a memory cell such as an FRAM (Ferroelctric RAM) or an SRAM.

[0053]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the SOI wafer of the present invention,
By providing the semiconductor region as a wiring layer on the base semiconductor substrate below the insulating film, the semiconductor element formed on the element formation semiconductor substrate and the wiring layer formed therefrom are formed on the base semiconductor substrate. Since the use of the wiring layer that is used can improve the degree of freedom in the design specification of the wiring region of the semiconductor element and reduce the multilayer structure of the wiring layer formed on the semiconductor substrate for element formation, the simplification of the device structure and Can be miniaturized.

(2). According to the SOI wafer of the present invention,
Since the base semiconductor substrate below the insulating film is provided with the capacitor and the semiconductor region as the wiring layer, the base semiconductor substrate is formed when the semiconductor element formed on the element formation semiconductor substrate and the wiring layer thereof are formed. Since the capacitive element and the wiring layer formed on the substrate can be used, the device structure can be simplified and miniaturized.

(3). According to the semiconductor integrated circuit device using the SOI wafer and the method of manufacturing the same of the present invention, by using the SOI wafer having the base semiconductor substrate provided with the semiconductor region as the wiring layer, the element forming semiconductor substrate is used. In the case of forming a semiconductor element and its wiring layer, the wiring layer formed on the base semiconductor substrate can be used, so that the degree of freedom in the design specification of the wiring region of the semiconductor element is improved and the semiconductor for element formation is formed. The multilayer structure of the wiring layer formed on the substrate can be reduced. Therefore, it is possible to reduce the area of a semiconductor element and improve the flatness of a wiring layer formed on a semiconductor substrate for element formation, and to manufacture a high-performance semiconductor integrated circuit device using a simple manufacturing process. Can be.

(4). According to the semiconductor integrated circuit device using the SOI wafer and the method of manufacturing the same according to the present invention, for example, an SOI wafer having a base semiconductor substrate including a semiconductor element as a wiring layer and a capacitor element used in a DRAM or the like is provided. The use of the capacitor and the wiring layer formed on the base semiconductor substrate enables the use of the capacitor element and the wiring layer when the semiconductor element and the wiring layer formed on the element forming semiconductor substrate are formed. And the formation of a capacitor in a region of a wiring layer formed thereover can be reduced. Further, the degree of freedom in design specification of the wiring region of the semiconductor element formed on the semiconductor substrate for element formation is improved, and the multilayer structure of the wiring layer formed on the semiconductor substrate for element formation can be reduced. Therefore, the area of the semiconductor element can be reduced, and the flatness of the wiring layer formed on the element forming semiconductor substrate can be improved, so that a high performance semiconductor integrated circuit device such as a DRAM can be manufactured using a simple manufacturing process. Can be manufactured.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device using an SOI wafer according to an embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device using the SOI wafer following FIG. 1;

FIG. 3 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device using the SOI wafer following FIG. 2;

FIG. 4 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device using the SOI wafer following FIG. 3;

5 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device using the SOI wafer following FIG. 4;

6 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device using the SOI wafer, following FIG. 5;

FIG. 7 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device using the SOI wafer, following FIG. 6;

8 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device using the SOI wafer, following FIG. 7;

9 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device using the SOI wafer, following FIG. 8;

10 is a schematic plan view perspectively showing a plane near a cross-sectional area of the semiconductor integrated circuit device shown in FIG. 8;

FIG. 11 is a fragmentary cross-sectional view showing a manufacturing step of a semiconductor integrated circuit device using an SOI wafer according to another embodiment of the present invention;

12 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device using the SOI wafer, following FIG. 11;

13 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device using the SOI wafer, following FIG. 12;

14 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device using the SOI wafer, following FIG. 13;

15 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device using the SOI wafer, following FIG. 14;

16 is a fragmentary cross-sectional view showing the manufacturing step of the semiconductor integrated circuit device using the SOI wafer, following FIG. 15;

FIG. 17 is a fragmentary cross-sectional view showing the manufacturing step of the semiconductor integrated circuit device using the SOI wafer, following FIG. 16;

18 is a fragmentary cross-sectional view showing the manufacturing step of the semiconductor integrated circuit device using the SOI wafer, following FIG. 17;

FIG. 19 is a fragmentary cross-sectional view showing a manufacturing step of an SOI wafer according to another embodiment of the present invention;

20 is a fragmentary cross-sectional view showing the manufacturing step for the SOI wafer following FIG. 19;

21 is a fragmentary cross-sectional view showing the manufacturing step of the SOI wafer following FIG. 20;

FIG. 22 is an essential part cross sectional view showing the manufacturing process of an SOI wafer following FIG. 21;

FIG. 23 is an essential part cross sectional view showing the SOI wafer manufacturing step following FIG. 22;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Base semiconductor substrate 2 Photoresist film 3 Semiconductor region 4 Photoresist film 5 Semiconductor region 6 Insulating film 7 Element forming semiconductor substrate 8 Photoresist film 9 Contact hole 10 Contact plug 11 Field insulating film 12 Semiconductor region 13 Gate insulating film 14 Gate electrode 15 Insulating film 16 Side wall insulating film 17 Semiconductor region 18 Semiconductor region 19 Insulating film 20 Contact plug 21 Insulating film 22 Wiring layer 23 Groove 24 Insulating film 25 Contact plug

Claims (9)

[Claims] 1. An SOI wafer having a semiconductor substrate for element formation provided on a base semiconductor substrate with an insulating film interposed therebetween, wherein the SOI wafer is formed in a selective region of the base semiconductor substrate below the insulating film. An SOI wafer provided with a wiring semiconductor region having a higher impurity concentration than a base semiconductor substrate. 2. The SOI wafer according to claim 1, wherein
An SOI wafer, wherein the semiconductor region for wiring and the semiconductor substrate for element formation are electrically connected by a contact plug. 3. The SOI wafer according to claim 1, wherein a semiconductor region forming a pn junction with the wiring semiconductor region is provided, and a capacitance due to the pn junction is used as a capacitance element. SOI wafer characterized by the above-mentioned. 4. An SOI wafer in which a semiconductor substrate for element formation is provided on a semiconductor substrate for base via an insulating film, and a selective region of the semiconductor substrate for base below the insulating film is provided with a capacitor. An SOI wafer comprising one electrode for an element and an insulating film for a capacitor and a contact plug as the other electrode for the capacitor in a region of the electrode. 5. The SOI wafer according to claim 4, wherein
An SOI wafer, wherein a semiconductor region for wiring having a higher impurity concentration than that of the base semiconductor substrate is provided in a selective region of the base semiconductor substrate. 6. The S according to claim 1, wherein
An OI wafer, wherein the contact plug has a pillar shape, that is, a pillar. 7. The S according to claim 1, wherein
A semiconductor integrated circuit device, wherein a plurality of semiconductor elements are formed on a semiconductor substrate for element formation on an OI wafer. 8. The S according to claim 1, wherein
A semiconductor integrated circuit device, comprising: a step of forming a plurality of semiconductor elements on a semiconductor substrate for element formation on an OI wafer; and a step of forming a wiring layer of the semiconductor element on the semiconductor substrate for element formation. Manufacturing method. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein a part of said wiring layer has a contact hole formed in an insulating film formed on said element forming semiconductor substrate. And a wiring layer in which a contact plug is buried in the contact hole.