JPS6321351B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit including a capacitive element, and particularly to a MOS integrated circuit suitable as a large-capacity IC memory.

MOS integrated circuits are suitable for high density and large scale,
Large capacity IC memory can be realized. In particular, a one-transistor type IC memory uses one transistor and one capacitor to provide a memory function, so the device occupies a small area, and is attracting attention as a high-density memory integrated circuit. Conventionally, a capacitive element and a transistor are formed separately within an active region, and four elements, the gate electrode of the transistor, two opposite conductivity type regions, and the electrode of the capacitive element, are laid out in a plane and provided on the active region. However, it is desirable to reduce these elements for higher density. Furthermore, it has become a necessary technology to reduce the size of the gate electrode of a transistor so that the gate electrode and the wiring electrode can be reliably coupled to each other in a reduced area.

An object of the present invention is to provide a higher density MOS integrated circuit.

The integrated circuit of the present invention is characterized in that a gate electrode is provided on a semiconductor substrate of one conductivity type via a gate insulating film, and regions of opposite conductivity type are provided in the substrate so that their respective ends are aligned with the gate electrode. In an integrated circuit, an electrode of a capacitive element is provided on the gate electrode via an insulating film, the electrode of the capacitive element is further covered with an insulating film, and a wiring layer of aluminum or the like is provided on top of the electrode. .

Such a semiconductor device is an integrated circuit in which, for example, the active region is protected by a silicon nitride film and a thick oxide film is grown on the surrounding semiconductor surface by using the selective oxidation property of a silicon nitride film with respect to the surface of a semiconductor of one conductivity type. , providing a gate electrode across the active region in advance, selectively covering the silicon nitride film and performing selective oxidation, and forming a capacitive element electrode on one end of the silicon nitride film used for the selective oxidation; It can be manufactured by a manufacturing method in which a region of opposite conductivity type is formed at the other end of the active region.

According to this invention, an integrated circuit having a sufficiently small planar shape can be realized without using special microfabrication techniques.

Next, in order to better understand the characteristics of the present invention, embodiments of the present invention will be described using figures.

1 to 4 are cross-sectional views showing the main manufacturing steps of an embodiment of the present invention.

The MOS integrated circuit of this example has a thickness of 300 Å on one surface of a P-type silicon single crystal substrate 1 with a specific resistance of 1 Ωcm.
A gate insulating film 2 of silicon oxide is grown by thermal oxidation, and gate electrodes 3 and 4 of phosphorous-doped polycrystalline silicon are selectively formed on its upper surface (FIG. 1).

The gate electrodes 3 and 4 are covered with silicon nitride films 7 and 8 that form an active region via silicon oxide films 5 and 6 of about 100 Å, and the substrate is thermally oxidized to form a thick film of about 1.0 μm around the active region. A silicon oxide film 9 is formed. Note that these silicon nitride films 7 and 8
Thick silicon oxide film 9 using as a mask for selective oxidation
Prior to the formation of P-type region 10, impurities for preventing parasitic effects are introduced into the surface of the inactive region using silicon nitride films 7 and 8 as masks, thereby forming highly doped P-type region 10. (Figure 2).

Next, a capacitive element electrode 11 of phosphorous-doped polycrystalline silicon is formed on the upper surface of the silicon nitride films 7 and 8 that have defined the active region, and a silicon oxide film 12 with a thickness of about 5000 Å is thermally oxidized on the electrode. do. This silicon oxide film 12 is also used as an etching mask for the silicon nitride films 7 and 8. That is, the capacitive element electrode 11 and the silicon nitride films 7 and 8 are protected at one end of each active region, and the silicon nitride film is removed from the partial surfaces of the gate electrodes 3 and 4 and the substrate surface at the other end. (Figure 3).

Phosphorus is ion-implanted into the substrate surface from which the silicon nitride film has been removed, using the polycrystalline silicon gate electrodes 3 and 4 as masks, with a junction depth of 1 μm and a surface concentration of about 10 ¹⁹ cm ^-3 , and N at the other end of the active region. mold area 1
3 and 14 are formed, and an aluminum wiring electrode 15 is conductively coupled to the exposed surfaces of the gate electrodes 3 and 4, completing the process as shown in FIG. In this completed MOS integrated circuit, a memory cell with a minimum element occupation area is formed in each active region, consisting of a gate electrode, a capacitor electrode, and an N-type region.

5 is a partial top view showing a 4-bit matrix portion of the completed MOS integrated circuit of FIG. 4. FIG. As shown in this figure, N-type region 1 of the memory cell
Since the gate electrode 3 and the capacitive element electrode 11, which connect the capacitive element and the gate electrode 3 through a conductive channel, overlap,
The area is reduced compared to a conventional one-transistor type memory cell. In addition, the conductive bond between the gate electrodes 3 and 4 and the wiring electrode 15 is obtained on the etched surface of the silicon nitride film, and since the silicon nitride film has etching selectivity with respect to the silicon oxide film, it is ensured on the minute exposed surface of about 0.5 to 2 μm. A highly conductive bond can be obtained.

Although one embodiment of the present invention has been described above, the present invention is not limited to memory integrated circuits as described above, but can also be applied to logic MOS integrated circuits.
Further, the conductivity type, electrode material, insulator, etc. used may be changed as necessary.

[Brief explanation of drawings]

1 to 4 are sectional views showing the order of steps in the main manufacturing process of an embodiment of the present invention, and FIG. 5 is a top view of the embodiment of the invention. In the figure, 1... P-type silicon single crystal substrate, 2... gate insulating film, 3, 4... gate electrode,
5, 6... Silicon oxide film, 7, 8... Silicon nitride film, 9... Silicon oxide film, 10... High concentration P type region, 11... Capacitive element electrode, 12... Silicon oxide film, 13, 14... N type region, 15... Wiring electrode.

Claims (1)

[Claims] 1. In a method for manufacturing an IC memory in which a memory cell is a series configuration of a field effect transistor and a capacitive element, there are two steps: forming a gate insulating film on the surface of a semiconductor substrate of one conductivity type, and depositing polycrystalline silicon on the gate insulating film on the active region. a step of selectively forming a gate electrode of the transistor, a step of forming an oxide film on the surface of the gate electrode, a step of selectively forming a nitride film only on the surface of the active region, and a step of forming the nitride film selectively on the surface of the active region; a step of forming a thick silicon oxide film on the surface of the semiconductor substrate other than the active region using a film as a mask; a step of partially removing the nitride film at one end of the gate electrode; and a step opposite to the one end of the gate electrode. forming an upper electrode of a capacitive element on the nitride film at the other end located at the gate electrode; and forming an opposite conductivity type region having an end located at the one end of the gate electrode. IC memory manufacturing method.