KR100515075B1 - Method of forming buried wiring of semiconductor device - Google Patents
Method of forming buried wiring of semiconductor device Download PDFInfo
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- KR100515075B1 KR100515075B1 KR1019980025266A KR19980025266A KR100515075B1 KR 100515075 B1 KR100515075 B1 KR 100515075B1 KR 1019980025266 A KR1019980025266 A KR 1019980025266A KR 19980025266 A KR19980025266 A KR 19980025266A KR 100515075 B1 KR100515075 B1 KR 100515075B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
본 발명은 반도체기판의 소정영역들을 이방성식각하여 각기 다른 다양한 폭을 갖는 트렌치들을 형성하는 단계, 상기 트렌치들이 형성된 기판 전면에 절연막을 증착하여 일부 트렌치는 절연막으로 매립하고 다른 트렌치에는 그 내면에 절연막이 형성되도록 하는 단계, 상기 질화막 상에 배선 형성용 도전층을 형성하는 단계, 및 상기 도전층 및 질화막을 제거하여 상기 트렌치내에만 남도록 하는 단계를 포함하여 구성되는 반도체소자의 매립배선 형성방법을 제공함으로써 디자인룰을 감소시키고, 후속공정의 마진을 개선하며, 접합 커패시턴스를 감소시키는 등의 효과를 얻는다. The present invention is anisotropically etched predetermined regions of a semiconductor substrate to form trenches having different widths, depositing an insulating film on the entire surface of the substrate on which the trenches are formed, and filling some trenches with an insulating film, and in another trench, an insulating film on the inner surface thereof. By forming a wiring layer forming conductive layer on the nitride film, and removing the conductive layer and the nitride film so as to remain only in the trench. Benefits include reduced design rules, improved margins in subsequent processes, reduced junction capacitance, and more.
Description
본 발명은 반도체장치의 매립배선 형성방법에 관한 것으로, 특히 트렌치 소자분리기술과 보더리스(borderless)콘택기술을 이용하여 매립배선을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a buried interconnect in a semiconductor device, and more particularly, to a method of forming a buried interconnect using a trench isolation method and a borderless contact technique.
도 1에 종래기술에 의해 제조되는 CMOS소자의 평면도 및 단면도를 나타내었다. 이를 제조하기 위하여 종래에는 LOCOS 소자분리 및 보더드(bordered) 콘택공정을 일반적으로 사용하였다. 1 is a plan view and a cross-sectional view of a CMOS device manufactured according to the prior art. In order to manufacture this, LOCOS device isolation and bordered contact processes have been generally used.
도 1을 참조하여 CMOS 소자의 제조 방법을 간략히 살펴보면, 반도체기판(11)의 소정 영역에 LOCOS 소자분리를 이용하여 소자분리막(FOX, 12)을 형성하고, 이온주입을 통해 PMOSFET가 형성될 n 웰(13)과 NMOSFET가 형성될 p 웰(14)을 각각 형성한다.Referring to FIG. 1, a method of fabricating a CMOS device will be described. An isolation film FOX 12 may be formed in a predetermined region of a semiconductor substrate 11 using LOCOS isolation, and an n well in which a PMOSFET is formed through ion implantation. (13) and p wells 14 on which NMOSFETs are to be formed are formed, respectively.
그리고, n 웰(13)과 p웰(14) 상부에 각각 게이트산화막(15)과 게이트전극(16)을 형성하고, 게이트전극(16)의 양측벽에 게이트스페이서(17)을 형성한 후, n 웰(13)과 p웰(14) 내에 이온주입을 통해 각각 p+ 소스/드레인(18)과 n+ 소스/드레인(19)을 형성한다. 그리고, n웰(13)과 p웰(14) 내에 웰 픽업을 위한 n+ 픽업층(20)과 p+ 픽업층(21)을 각각 형성한다.After the gate oxide film 15 and the gate electrode 16 are formed on the n well 13 and the p well 14, respectively, and the gate spacers 17 are formed on both side walls of the gate electrode 16. Ion implantation into n well 13 and p well 14 forms p + source / drain 18 and n + source / drain 19, respectively. Then, n + pickup layer 20 and p + pickup layer 21 for well pickup are formed in n well 13 and p well 14, respectively.
그리고, 게이트전극(16)을 포함한 전면에 층간절연막(22)을 형성한 후, 보더드콘택 공정을 진행하여 p+ 소스/드레인(18)에 연결되는 금속배선(Vcc, out)을 형성하고, n+ 소스/드레인(19)에 연결되는 금속배선(Vss, out)을 형성한다. 여기서, 금속배선Vcc은 n+ 픽업층(20)과 p+ 소스에 동시에 연결되고, 금속배선 Vss는 p+ 픽업층(21)과 n+ 소스에 동시에 연결되며, 금속배선 out는 p+ 드레인과 n+ 드레인에 동시에 연결된다.After the interlayer insulating film 22 is formed on the entire surface including the gate electrode 16, a border contact process is performed to form metal wirings (Vcc, out) connected to the p + source / drain 18. Metal wires Vss and out connected to the source / drain 19 are formed. Here, the metal wiring Vcc is simultaneously connected to the n + pickup layer 20 and the p + source, the metal wiring Vss is simultaneously connected to the p + pickup layer 21 and the n + source, and the metal wiring out is simultaneously connected to the p + drain and the n + drain. do.
도 1과 같은 종래기술의 경우, 금속배선과 소스/드레인간 연결을 위해 보더드콘택 공정을 이용하는데, 보더드콘택 공정이 층간절연막(22)을 식각하여 소스/드레인을 노출시키는 콘택홀을 형성하고 이 콘택홀에 배선 물질을 매립하는 공정을 이용함에 따라 고집적화시에 콘택홀을 디파인하는데 한계 디자인룰이 발생하는 문제가 있다. 즉, 콘택홀 형성시 하부의 소스/드레인과의 오버랩을 항상 고려해야 하며(소스/드레인을 벗어나면 않되도록 고려), 오버랩마진이 부족한 경우에는 오정렬로 인해 콘택불량이 발생한다. 특히, 보더드콘택 공정을 이용하는 경우에는 배선공정(Vcc, Vss, out)이 복잡해지고 트랜지스터 소오스 및 드레인영역의 접합커패시터(CJ)도 일정수준 이하로는 줄일 수 없게 되는 문제등이 생긴다.In the prior art as shown in FIG. 1, a border contact process is used to connect a metal wire and a source / drain, and the border contact process etches the interlayer insulating layer 22 to form a contact hole exposing a source / drain. In addition, there is a problem in that a limit design rule occurs in defining the contact hole at the time of high integration, by using a process of embedding wiring material in the contact hole. That is, when forming a contact hole, the overlap with the source / drain at the bottom should always be considered (to avoid leaving the source / drain). If the overlap margin is insufficient, contact failure occurs due to misalignment. In particular, when the border contact process is used, the wiring processes (Vcc, Vss, out) become complicated, and the junction capacitor CJ of the transistor source and drain regions cannot be reduced to a certain level or less.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 트렌치 소자분리기술과 보더리스 콘택기술을 이용하여 배선을 매립하는 형태로 형성하는 방법을 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide a method of forming a wiring in a form using a trench device isolation technique and a borderless contact technique.
상기 목적을 달성하기 위한 본 발명의 매립 배선 형성방법은 반도체기판의 소정영역들을 이방성식각하여 각기 다른 다양한 폭을 갖는 트렌치들을 형성하는 단계, 상기 트렌치들이 형성된 기판 전면에 절연막을 증착하여 일부 트렌치는 절연막으로 매립하고 일부 트렌치에는 그 내면에 절연막이 형성되도록 하는 단계, 상기 절연막 상에 배선 형성용 도전층을 형성하는 단계, 및 상기 도전층 및 질화막을 제거하여 상기 트렌치내에만 남도록 하는 단계를 포함하여 구성된다. In the buried wiring forming method of the present invention to achieve the above object is to anisotropically etch a predetermined region of the semiconductor substrate to form trenches having different widths, by depositing an insulating film on the entire surface of the substrate on which the trench is formed some trench And forming an insulating film on an inner surface of the trench, forming a conductive layer for forming a wiring on the insulating film, and removing the conductive layer and the nitride film so as to remain only in the trench. do.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2c에 본 발명에 의한 매립 배선 형성방법을 공정순서에 따라 나타내었다.2A to 2C show a buried wiring formation method according to the present invention according to the process sequence.
먼저, 도 2a에 나타낸 바와 같이 반도체기판(31) 소정영역을 이방성식각하여 트렌치(32a, 32b, 32c)를 형성한다. 이때, 소자분리영역과 배선이 형성될 부분에 동시에 트렌치를 형성하는 바, 배선을 형성할 트렌치(32a, 32b)는 그 크기를 a 이상의 크기(b, c)로 형성한다. 소자분리영역의 트렌치(32c)가 갖는 a보다 큰 폭으로 형성한다.First, as shown in FIG. 2A, the trenches 32a, 32b, and 32c are formed by anisotropically etching the predetermined region of the semiconductor substrate 31. At this time, since the trenches are simultaneously formed in the device isolation region and the portion where the wirings are to be formed, the trenches 32a and 32b for forming the wirings have a size of a or more (b, c). It is formed to have a width larger than a of the trench 32c in the device isolation region.
이어서 도 2b에 나타낸 바와 같이 상기 트렌치(32a, 32b, 32c)가 형성된 반도체기판(31) 전면에 절연막으로서 예컨대 질화막(33)을 형성한다. 이때, 배선이 형성되지 않을 소자분리영역에 해당하는 트렌치(32c)는 완전히 매립되도록 질화막(33)을 형성한다. 이어서 상기 질화막(33) 상에 배선 형성을 위한 도전층으로서 예컨대 도핑된 폴리실리콘층(34)을 형성한다.Next, as shown in FIG. 2B, a nitride film 33 is formed as an insulating film over the entire surface of the semiconductor substrate 31 on which the trenches 32a, 32b, and 32c are formed. In this case, the nitride film 33 is formed to completely fill the trench 32c corresponding to the device isolation region where the wiring is not to be formed. Subsequently, a doped polysilicon layer 34 is formed on the nitride film 33 as a conductive layer for wiring formation.
다음에 도 2c에 나타낸 바와 같이 상기 폴리실리콘층(34) 및 질화막(33)을 선택적으로 제거하여 트렌치(32a, 32b, 32c)내에만 남도록 한다. 이때, 폴리실리콘층(34) 및 질화막(33)의 제거공정은 에치백 또는 화학적 기계적 연마등과 같은 다양한 방법에 의해 행할 수 있다.Next, as shown in FIG. 2C, the polysilicon layer 34 and the nitride film 33 are selectively removed so as to remain only in the trenches 32a, 32b, and 32c. At this time, the removal process of the polysilicon layer 34 and the nitride film 33 can be performed by various methods, such as etch back or chemical mechanical polishing.
상술한 본 발명에 따른 매립배선 형성방법을 CMOS 제조공정에 적용한 예를 도 3 및 도 4에 도시하였다.3 and 4 illustrate an example in which the buried interconnection forming method according to the present invention is applied to a CMOS manufacturing process.
도 3은 CMOS의 평면도이고, 도 4는 도 3의 B-B'선에 따른 단면도이다.3 is a plan view of the CMOS, and FIG. 4 is a cross-sectional view taken along line BB ′ of FIG. 3.
도 3과 도 4를 참조하여 본 발명의 실시예에 따른 CMOS 소자의 제조 방법을 살펴보기로 한다.A method of manufacturing a CMOS device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 4.
먼저, 반도체기판(41)의 소정 영역에 전술한 도 2a 내지 도 2c의 방법을 이용하여 소자분리지역에서는 트렌치에 질화막(42a)이 매립된 소자분리막(FOX)을 형성하고, 배선층이 형성될 지역에는 트렌치에 질화막(42a)과 폴리실리콘층(42b)이 매립된 콘택구조를 형성한다.First, in the device isolation region in the device isolation region by using the method of FIGS. 2A to 2C described above, a device isolation film (FOX) in which the nitride film 42a is embedded in the trench is formed, and the wiring layer is to be formed. In the trench, a contact structure in which the nitride film 42a and the polysilicon layer 42b are embedded is formed.
그리고, 이온주입을 통해 PMOSFET가 형성될 n 웰(43)과 NMOSFET가 형성될 p웰(44)을 각각 형성한다.In addition, the n well 43 in which the PMOSFET is to be formed and the p well 44 in which the NMOSFET are to be formed through ion implantation are formed, respectively.
그리고, n 웰(43)과 p웰(44) 상부에 각각 게이트산화막(45)과 게이트전극(46)을 형성하고, 게이트전극(46)의 양측벽에 게이트스페이서(47)을 형성한 후, n 웰(43)과 p웰(44) 내에 이온주입을 통해 각각 p+ 소스/드레인(48)과 n+ 소스/드레인(49)을 형성한다. 그리고, n웰(43)과 p웰(44) 내에 웰픽업을 위한 n+ 픽업층(50)과 p+ 픽업층(51)을 각각 형성한다.After the gate oxide film 45 and the gate electrode 46 are formed on the n well 43 and the p well 44, respectively, and the gate spacer 47 is formed on both side walls of the gate electrode 46. Ion implantation into n well 43 and p well 44 forms p + source / drain 48 and n + source / drain 49, respectively. Then, n + pick-up layer 50 and p + pick-up layer 51 for well pick-up are formed in n-well 43 and p-well 44, respectively.
그리고, 게이트전극(46)을 포함한 전면에 층간절연막(52)을 형성한 후, 보더리스콘택 공정을 진행하여 p+ 소스/드레인(48)에 연결되는 금속배선(Vcc, out)을 형성하고, n+ 소스/드레인(49)에 연결되는 금속배선(Vss, out)을 형성한다. 여기서, 배선Vcc은 n+ 픽업층(50)과 p+ 소스에 동시에 연결되고, 금속배선 Vss는 p+ 픽업층(51)과 n+ 소스에 동시에 연결되며, 금속배선 out는 p+ 드레인과 n+ 드레인에 동시에 연결된다.After the interlayer insulating film 52 is formed on the entire surface including the gate electrode 46, a borderless contact process is performed to form metal wirings (Vcc, out) connected to the p + source / drain 48. Metal wires Vss and out connected to the source / drain 49 are formed. Here, the wiring Vcc is simultaneously connected to the n + pickup layer 50 and the p + source, the metal wiring Vss is simultaneously connected to the p + pickup layer 51 and the n + source, and the metal wiring out is simultaneously connected to the p + drain and the n + drain. .
도 3 및 도 4에 도시된 바와 같이 트렌치를 이용하여 금속배선과 연결되는 폴리실리콘층(42b)을 매립하여 형성함으로써 참조부호 100으로 나타낸 부분에서 알 수 있듯이 종래기술의 디자인룰의 한계를 극복할 수 있게 된다. 또한, 도시된 바와 같이 다양한 크기와 형태의 매립 배선을 사용할 수 있다. 그리고 참조부호 200으로 나타낸 부분에서와 같이 트랜지스터의 접합부분의 면적(배선 out와 콘택간 접합면적)이 감소되므로 접합커패시턴스도 감소되어 소자의 고속동작이 가능하게 된다. 또한, 참조부호 300으로 나타낸 부분에서 알 수 있듯이 산화막과 선택비를 갖는 질화막을 사용함에 따라 콘택과 웰의 측면부 단락이 방지된다. 아울러 후속의 금속배선 공정시 디자인룰을 개선시킬 수 있다. (참조부호 400 참조)As shown in FIG. 3 and FIG. 4, the polysilicon layer 42b connected to the metal wiring is embedded by using a trench to overcome the limitations of the prior art design rule, as indicated by the reference numeral 100. It becomes possible. In addition, buried wiring of various sizes and shapes may be used as shown. As shown by the reference numeral 200, the area of the junction portion of the transistor (the junction area between the wiring out and the contact) is reduced, so that the junction capacitance is also reduced, thereby enabling high-speed operation of the device. Further, as can be seen from the portion indicated by reference numeral 300, short circuiting of the side portions of the contact and the well is prevented by using a nitride film having an oxide film and a selectivity ratio. In addition, it is possible to improve design rules in subsequent metallization processes. (See 400)
상기 트렌치 공정시 트렌치 폭을 구분하여 적용함으로써 필요한 부분에만 선택적으로 매립 배선을 형성할 수 있다. 즉, 도면에서 b로 나타낸 부분은 질화막(42a)으로 완전히 매립하고 a로 나타낸 부분은 질화막(42a)을 형성하고 중심부분에 폴리실리콘층(42b)을 매립한다. 또한, 참조부호 100으로 나타낸 부분에서 알 수 있듯이 이 보더리스 콘택에서 웰 픽업과 Vcc를 동시에 스트랩할 수 있다.In the trench process, a buried wiring may be selectively formed only in a required portion by dividing and applying a trench width. That is, the portion indicated by b in the figure is completely filled with the nitride film 42a, and the portion indicated by a forms the nitride film 42a, and the polysilicon layer 42b is embedded in the central portion. In addition, as shown by the reference numeral 100, the well pick-up and the Vcc can be strapped at the same time in this borderless contact.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
본 발명에 의하면, 트렌치 공정과 보더리스 콘택공정을 이용하여 매립 배선을 형성함으로써 디자인룰을 감소시키고, 후속공정의 마진을 개선하며, 접합 커패시턴스를 감소시키는 등의 효과를 얻을 수 있다.According to the present invention, the buried wiring is formed by using the trench process and the borderless contact process, thereby reducing the design rule, improving the margin of the subsequent process, and reducing the junction capacitance.
도 1은 종래기술에 의해 제조된 CMOS의 평면도 및 단면도,1 is a plan view and a cross-sectional view of a CMOS manufactured by the prior art,
도 2a 내지 도 2c는 본 발명에 의한 반도체소자의 매립배선 형성방법을 도시한 공정순서도,2A to 2C are process flowcharts showing a method for forming buried wirings in a semiconductor device according to the present invention;
도 3은 본 발명의 매립배선 형성공정을 적용하여 제조한 CMOS의 평면도,3 is a plan view of a CMOS manufactured by applying the buried interconnection forming process of the present invention;
도 4는 본 발명의 매립배선 형성공정을 적용하여 제조한 CMOS의 단면도. 4 is a cross-sectional view of a CMOS manufactured by applying the buried interconnection formation process of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
41 : 반도체 기판 42a : 질화막41 semiconductor substrate 42a nitride film
42b : 폴리실리콘층 43 : n 웰42b: polysilicon layer 43: n well
44 : p 웰 45 : 게이트산화막44 p well 45 gate oxide film
46 : 게이트전극 47 : 게이트스페이서46: gate electrode 47: gate spacer
48 : p+ 소스/드레인 49 : n+ 소스/드레인48: p + source / drain 49: n + source / drain
50 : n+ 픽업층 51 : p+ 픽업층50: n + pickup layer 51: p + pickup layer
52 : 층간절연막52: interlayer insulating film
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980025266A KR100515075B1 (en) | 1998-06-30 | 1998-06-30 | Method of forming buried wiring of semiconductor device |
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| KR1019980025266A KR100515075B1 (en) | 1998-06-30 | 1998-06-30 | Method of forming buried wiring of semiconductor device |
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| KR20000003958A KR20000003958A (en) | 2000-01-25 |
| KR100515075B1 true KR100515075B1 (en) | 2006-01-12 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58112342A (en) * | 1981-12-25 | 1983-07-04 | Toshiba Corp | Manufacture of semiconductor device |
| JPH06334031A (en) * | 1993-05-25 | 1994-12-02 | Nec Corp | Element-isolation method for semiconductor device |
| JPH07106277A (en) * | 1993-10-05 | 1995-04-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH1092820A (en) * | 1996-09-12 | 1998-04-10 | Toshiba Corp | Method of forming metal wiring and metal wiring forming equipment |
-
1998
- 1998-06-30 KR KR1019980025266A patent/KR100515075B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58112342A (en) * | 1981-12-25 | 1983-07-04 | Toshiba Corp | Manufacture of semiconductor device |
| JPH06334031A (en) * | 1993-05-25 | 1994-12-02 | Nec Corp | Element-isolation method for semiconductor device |
| JPH07106277A (en) * | 1993-10-05 | 1995-04-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH1092820A (en) * | 1996-09-12 | 1998-04-10 | Toshiba Corp | Method of forming metal wiring and metal wiring forming equipment |
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| KR20000003958A (en) | 2000-01-25 |
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