JP2006228950A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the mobility of carriers is improved by applying stress on a semiconductor substrate while avoiding the generation of a large divot or contact connection failure, and to provide a manufacturing method thereof. <P>SOLUTION: A gate electrode 4 is formed on a semiconductor substrate 1 via a gate insulating film 3. Source/drain regions 8 are formed on both sides of the gate electrode 4 of the semiconductor substrate 1. A liner film 11 is formed continuously from the inside wall of an element isolation groove 2 over the source/drain regions 8 and the gate electrode 4. The continuously formed liner film 11 applies stress to the semiconductor substrate 1 to improve the mobility of the carriers. The liner film 11 has also a role of an etching stopper for forming a contact 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, with the demand for higher integration and higher functionality of semiconductor devices, element structures have been miniaturized. Under such circumstances, in a conventional semiconductor device (so-called MOS transistor) in which a gate electrode is provided on a semiconductor substrate via a gate insulating film, characteristics are improved by simple miniaturization, and a noticeable short circuit. It is difficult to simultaneously suppress the channel effect (for example, punch-through phenomenon).

  For this reason, attempts have been made to improve characteristics by changing the mobility of carriers. As a typical example, a technique for improving characteristics by stress is known. As one of the stress control methods, there are a contact stopper liner film and an STI liner film. The contact stopper liner film is disclosed in Non-Patent Documents 1 and 2, and the STI liner film is disclosed in Patent Documents 1 and 2.

  However, as pointed out in Patent Documents 1 and 2, the STI liner film has a drawback that the divot at the end of the element isolation insulating film tends to be large. When the divot becomes large, the gate electrode material to be formed thereafter is buried in the divot, causing problems such as a short circuit of the gate and generation of a parasitic transistor.

Further, the liner film for the contact stopper has a drawback that a connection hole formation defect (contact opening defect) is likely to occur when the liner film is thickened to apply more stress. If the connection hole reaching the source / drain region is not formed well, a connection failure of a contact formed by burying a conductive material in the connection hole occurs.
Japanese Patent Laid-Open No. 2002-12477 JP 2002-373935 A A. Shimizu et.al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, IEDM Tech, 2001 S. Thompson et.al., “A 90nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1um2 SRAM Cell”, IEDM Tech. 2002

  The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the mobility of carriers by applying stress to the semiconductor substrate while avoiding the occurrence of large divots and poor contact connections. Is to provide.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of efficiently applying stress to a semiconductor substrate while avoiding the occurrence of large divots and poor contact connections. There is to do.

  In order to achieve the above object, a semiconductor device of the present invention is formed on an element isolation insulating film formed on a semiconductor substrate, a gate electrode formed on the semiconductor substrate, and the semiconductor substrate on both sides of the gate electrode. The semiconductor substrate is formed continuously from the interface between the two semiconductor regions to be the source or drain and the element isolation insulating film and the semiconductor substrate to the semiconductor region and the gate electrode, and stresses the semiconductor substrate. And a liner film.

  In the semiconductor device of the present invention described above, the liner film is continuously formed from the interface between the element isolation insulating film and the semiconductor substrate to the semiconductor region and the gate electrode, so that the area acting on the semiconductor substrate is large. Become. For this reason, the liner film efficiently stresses the semiconductor substrate. This stress improves carrier mobility in the region (channel) of the semiconductor substrate under the gate electrode. Further, since the liner film is continuously formed, generation of a large divot is avoided.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a dummy element isolation film that partitions an active region on the semiconductor substrate, and a gate electrode is formed on the semiconductor substrate in the active region. A step of forming two semiconductor regions to be a source or a drain on the semiconductor substrate on both sides of the gate electrode, and removing the dummy element isolation film to form an element isolation groove in the semiconductor substrate. Forming a liner film on the inner wall of the element isolation trench, on the semiconductor region and on the gate electrode, and forming an insulating film on the liner film so as to fill the element isolation groove Process.

  In the method of manufacturing a semiconductor device according to the present invention, after the gate electrode and the semiconductor region are formed, the dummy element isolation film is removed to form an element isolation groove, whereby the inner wall of the element isolation groove is formed on the semiconductor region. In addition, a continuous liner film can be formed on the gate electrode. Thereby, the area which acts on the semiconductor substrate is large, and therefore a liner film which can be thinned is formed.

According to the semiconductor device of the present invention, carrier mobility can be improved by applying stress to the semiconductor substrate while avoiding the occurrence of large divots and poor contact connections.
According to the method for manufacturing a semiconductor device of the present invention, it is possible to manufacture a semiconductor device in which stress is efficiently applied to a semiconductor substrate while avoiding the occurrence of a large divot or contact connection failure.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to the first embodiment.

  For example, in a semiconductor substrate 1 made of silicon, element isolation trenches 2 that partition active regions are formed. A gate electrode 4 made of, for example, polysilicon is formed on the semiconductor substrate 1 in the active region via a gate insulating film 3 made of, for example, silicon oxide.

  A silicide layer 5 made of, for example, cobalt silicide is formed on the upper surface of the gate electrode 4, and a sidewall insulating film 6 made of, for example, silicon nitride is formed on the side wall of the gate electrode 4.

  A shallow extension region 7 is formed in the semiconductor substrate 1 on both sides of the gate electrode 4, more specifically, in the semiconductor substrate 1 immediately below the sidewall insulating film 6. In the case of a p-channel MOS transistor, a p-type extension region 7 is formed, and in the case of an n-channel MOS transistor, an n-type extension region 7 is formed.

  A source / drain region 8 deeper than the extension region 7 is formed in the semiconductor substrate 1 on both sides of the gate electrode 4 and outside the extension region 7. The source / drain region 8 is a semiconductor region to be a source or a drain. In the case of a p-channel MOS transistor, a p-type source / drain region 8 is formed. In the case of an n-channel MOS transistor, an n-type source / drain region 8 is formed.

  A silicide layer 9 made of, for example, cobalt silicide is formed on the surface of the source / drain region 8.

  A liner film 11 is formed on the entire inner wall of the element isolation trench 2, on the source / drain regions 8 and on the gate electrode 4 via a pad insulating film 10 made of, for example, silicon oxide. The film thickness of the pad insulating film 10 is, for example, 10 nm to 50 nm.

  The liner film 11 is made of, for example, a silicon nitride (SiN) film or a silicon oxynitride (SiON) film. The liner film 11 is not limited to a single layer and may be a laminated film. The film thickness of the liner film 11 is, for example, 10 nm to 100 nm. As will be described later, the liner film 11 has a function of applying stress to the semiconductor substrate 1 to improve carrier mobility.

  An insulating film 12 is formed on the liner film 11 so as to fill the element isolation trench 2 and cover the gate electrode 4. The insulating film 12 is made of, for example, silicon oxide. The insulating film 12 also serves as an element isolation insulating film 12 a that fills the element isolation trench 2 and an interlayer insulating film 12 b positioned above the main surface of the semiconductor substrate 1. In this example, the insulating film 12 may be formed of multiple layers other than a single layer.

  In the insulating film 12, contacts 13 connected to the two source / drain regions 8, more specifically, the two silicide layers 9 are formed. The contact 13 is made of tungsten, for example.

  Although not shown, a first layer wiring is formed on the contact 13, and a multilayer wiring layer is further formed on the first layer wiring.

  In the semiconductor device according to the present embodiment, the liner film 11 is continuously formed from the interface between the element isolation insulating film 12a and the semiconductor substrate 1 to the source / drain region 8 and the gate electrode 4. The liner film 11 of this embodiment has a shape in which a conventional contact stopper liner film and an STI liner film are connected. In FIG. 1, the liner film 11 is interrupted at the contact 13 portion. However, when viewed in plan, the liner film 11 is connected around the contact 13.

  The silicon nitride film or silicon oxynitride film to be the liner film 11 can easily adjust the stress in the film arbitrarily. That is, the liner film 11 is a film having a compressive stress or a film having a tensile stress. As a result, a force F1 for expanding the channel (region under the gate electrode 4) of the semiconductor substrate 1 or a force F2 for contracting the channel of the semiconductor substrate 1 acts. By controlling this force, that is, mechanical stress applied to the channel, the mobility of carriers (electrons for n-channel MOS transistors and holes for p-channel MOS transistors) can be improved. If the carrier mobility is improved, the drive current can be increased, and the same effect as miniaturization of the semiconductor device can be obtained.

  In this embodiment, since the liner film 11 is continuously formed from the interface between the element isolation insulating film 12a and the semiconductor substrate 1 to the source / drain region 8 and the gate electrode 4, the semiconductor substrate 1 can be stressed, and as a result, a strong stress can be applied to the channel of the semiconductor substrate 1.

  That is, when a predetermined stress is applied to the channel of the semiconductor substrate 1, the liner is compared with, for example, a conventional contact stopper liner film (formed only on the source / drain region 8 and the gate electrode 4). The film thickness of the film 11 can be reduced. For this reason, a contact connection hole reaching the source / drain region 8 can be reliably formed, and contact connection failure can be prevented. However, the liner film 11 needs to have a film thickness that can serve as a contact stopper (etching stopper).

  Furthermore, in this embodiment, the liner film 11 is connected from the inner wall of the element isolation trench 2 to the source / drain region 8, and the insulating film 12 is formed so as to fill the element isolation trench 2. Such a structure is made possible by forming the liner film 11 and the insulating film 12 after once removing the dummy element isolation film, as will be described later. By not using the conventional STI liner film in the formation of the dummy element isolation film, the generated divot becomes smaller than the conventional element isolation insulating film using the STI liner film.

  As described above, according to the semiconductor device of this embodiment, stress can be applied to the semiconductor substrate while avoiding the occurrence of large divots and poor contact connections, and the carrier mobility can be improved. By improving the carrier mobility, the driving current can be increased, and the same effect as miniaturization of the semiconductor device can be achieved.

  Since the occurrence of a large divot or contact opening failure can be avoided, the reliability of the semiconductor device can be improved while improving the carrier mobility.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 2 to 7 are process cross-sectional views corresponding to FIG. 2 to 7 are process cross-sectional views in the gate length direction. FIG. 8 is a process sectional view in the gate width direction (direction perpendicular to the paper surface of FIG. 1).

  First, as shown in FIG. 2A, an element isolation trench 2 is formed in a semiconductor substrate 1 by STI (Shallow Trench Isolation) technology, and a dummy element isolation film 14 is formed by embedding the element isolation trench 2. To do. Here, in the formation of the dummy element isolation film 14, a silicon oxide film is simply formed without using a conventional STI liner film made of a silicon nitride film. In this way, in the first formation of the dummy element isolation insulating film, the divot 14a generated at the end of the dummy element isolation film 14 is not formed as shown in FIG. This is smaller than the element isolation insulating film using the STI liner film.

  Next, as shown in FIG. 2B, the gate insulating film 3 made of silicon oxide is formed on the semiconductor substrate 1 in the active region, for example, by thermal oxidation.

  Next, as shown in FIG. 3A, a gate electrode 4 made of, for example, polysilicon is formed on the semiconductor substrate 1 in the active region via the gate insulating film 3. The gate electrode 4 is formed by depositing polysilicon as a gate electrode material on the entire surface of the semiconductor substrate 1 and etching the gate electrode material using a resist mask.

  FIG. 8A is a cross-sectional view in the gate width direction after the process. The gate electrode 4 extends to the dummy element isolation film 14. Here, in particular, when the width of the dummy element isolation film 14 that the gate electrode 4 crosses is wide, it is preferable to leave the pillar 1 a in the element isolation trench 2 and under the gate electrode 4. The pillar 1a may be formed by etching the semiconductor substrate 1 in a pattern that leaves the pillar 1a when the element isolation trench 2 is formed in the semiconductor substrate 1.

  Next, as shown in FIG. 3B, extension regions 7 are formed in the semiconductor substrate 1 on both sides of the gate electrode 4 by ion implantation using the gate electrode 4 as a mask. In the case of a p-channel MOS transistor, boron is ion-implanted as a p-type impurity to form a p-type extension region 7. In the case of an n-channel MOS transistor, n-type extension region 7 is formed by ion implantation of arsenic or phosphorus as an n-type impurity.

  Next, as shown in FIG. 4A, a sidewall insulating film 6 made of, for example, silicon nitride is formed on the sidewall of the gate electrode 4. In this process, after a silicon nitride film is deposited on the entire surface of the semiconductor substrate 1 so as to cover the gate electrode 4, a sidewall insulating film 6 is formed on the side wall of the gate electrode 4 by performing etch back.

  Next, as shown in FIG. 4B, an extension is applied to the semiconductor substrate 1 on both sides of the gate electrode 4 and outside the extension region 7 by ion implantation using the gate electrode 4 and the sidewall insulating film 6 as a mask. A source / drain region 8 deeper than the region 7 is formed. In the case of a p-channel MOS transistor, boron is ion-implanted as a p-type impurity to form p-type source / drain regions 8. In the case of an n-channel MOS transistor, n-type source / drain regions 8 are formed by ion implantation of arsenic or phosphorus as an n-type impurity.

  Next, as shown in FIG. 5A, a silicide layer 5 is formed on the surface of the gate electrode 4, and a silicide layer 9 is formed on the surface of the source / drain region 8. In this step, for example, a cobalt layer is deposited on the semiconductor substrate 1 so as to cover the gate electrode 4, the silicide layer 5 and the silicide layer 9 are formed by heat treatment, and then the cobalt layer is removed.

  As described above, a transistor is manufactured on the semiconductor substrate 1. In the conventional method for manufacturing a semiconductor device, the process then proceeds to an interlayer insulating film formation and contact formation process. In the present embodiment, the process proceeds to the following process.

  As shown in FIG. 5B, the dummy element isolation film 14 filling the element isolation trench 2 of the semiconductor substrate 1 is removed by wet etching. As a result, the element isolation trench 2 is exposed and formed. In this etching, an etching solution having a high etching selectivity of the dummy element isolation film 14 with respect to the sidewall insulating film 6 and the gate electrode 4 is used. Further, since the silicide layer 9 is formed, an etching solution having a high etching selectivity of the dummy element isolation film 14 with respect to the silicide layer 9 is used.

  FIG. 8B is a cross-sectional view in the gate width direction after the process. As shown in FIG. 8B, the gate electrode 4 floats in the air above the element isolation trench 2 by removing the dummy element isolation film 14. However, in this embodiment, since the gate electrode 4 is supported by the pillar 1a in the particularly wide element isolation groove 2, the gate electrode 4 can be prevented from being broken.

  Next, as shown in FIG. 6A, a pad insulating film 10 made of, for example, silicon oxide is formed on the inner wall of the element isolation trench 2, the source / drain region 8, and the gate electrode 4. For example, the pad insulating film 10 having a thickness of 10 nm to 50 nm is formed.

  Next, as shown in FIG. 6B, a liner film 11 is formed by depositing a silicon nitride film or a silicon oxynitride film on the pad insulating film 10. For example, the liner film 11 having a thickness of 10 nm to 100 nm is formed. When a silicon nitride film or a silicon oxynitride film is formed as the liner film 11, the stress in the film can be arbitrarily adjusted. For example, the liner film 11 having a compressive stress can be formed by forming a silicon nitride film by a plasma CVD method. Alternatively, the liner film 11 having tensile stress can be formed by forming a silicon nitride film by a thermal CVD method.

  Further, for example, after the liner film 11 is formed, an impurity (for example, Ge ion) is ion-implanted into the liner film 11 to adjust the stress in the film. For this reason, for example, when forming a CMOS transistor, an optimum liner film 11 is formed in accordance with an n-channel MOS transistor, and then Ge ions are ion-implanted into the liner film 11 in the region of the p-channel MOS transistor. The stress in the film may be adjusted. On the contrary, after the optimum liner film 11 is formed in accordance with the p-channel MOS transistor, Ge ions are implanted into the liner film 11 in the n-channel MOS transistor region to adjust the stress in the film. Good.

  Next, as shown in FIG. 7A, for example, a silicon oxide film is deposited on the liner film 11 so as to fill the element isolation trench 2 and the gate electrode 4 to form an insulating film 12. The insulating film 12 can be broadly divided into an element isolation insulating film 12 a that fills the element isolation trench 2 and an interlayer insulating film 12 b that covers the gate electrode 4. Here, in the case where appropriate insulating films are different between the element isolation insulating film 12a and the interlayer insulating film 12b, the insulating film 12 may be formed of two or more layers.

  Next, as shown in FIG. 7B, the insulating film 12 is etched using a resist mask to form connection holes 13a reaching the source / drain regions 8, more specifically the silicide layer 9. In this step, first, the insulating film 12 is etched using the liner film 11 as an etching stopper (contact stopper). Thereafter, the liner film 11 and the pad insulating film 10 exposed in the connection hole 13a are removed. As described above, the liner film 11 is formed with such a film thickness that does not cause defective formation of the connection hole 13a while ensuring a film thickness that can function as an etching stopper. The reaching connection hole 13a can be formed with high accuracy.

  Next, the contact 13 is formed in the connection hole 13a by embedding the connection hole 13a with a conductive material such as tungsten (see FIG. 1). Then, a semiconductor device is manufactured by performing a multilayer wiring formation process.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, after the transistor is formed on the semiconductor substrate 1, the dummy element isolation film 14 is once removed, and then the inner wall of the element isolation trench 2, the source A liner film 11 continuously formed on the drain region 8 and the gate electrode 4 is formed.

  In this embodiment, since the conventional STI liner film is not used in forming the dummy element isolation film 14, the divot 14a generated at the end of the dummy element isolation film 14 is an element isolation using the conventional STI liner film. It is smaller than the divot generated at the end of the insulating film. Moreover, since the film thickness of the liner film 11 for applying stress to the semiconductor substrate 1 can be reduced, the formation failure of the connection hole 13a can be prevented. Since the connection hole 13a reaching the silicide layer 9 can be formed with high accuracy, connection failure of the contact 13 can be prevented.

  For this reason, stress can be efficiently applied to the semiconductor substrate 1 while avoiding the occurrence of a large divot and the occurrence of poor contact connection. Therefore, a semiconductor device with improved carrier mobility can be manufactured without reducing the yield.

(Second Embodiment)
FIG. 9 is a cross-sectional view illustrating an example of a semiconductor device according to the second embodiment. In addition, the same code | symbol is attached | subjected to the component same as FIG. 1, and the description is abbreviate | omitted.

  In the present embodiment, the liner film is formed directly on the inner wall (interface between the element isolation insulating film 12a and the semiconductor substrate 1), the source / drain region 8 and the gate electrode 4 of the element isolation trench 2 of the semiconductor substrate 1. 11 is formed.

  In the first embodiment, the pad insulating film 10 is interposed between the liner film 11 and the semiconductor substrate 1 because silicon nitride or silicon oxynitride having charge retention characteristics is directly formed on the semiconductor substrate 1 as the liner film 11. This is because when formed, there is a concern that the electrical characteristics of the MOS transistor are affected. However, if there is no such influence, the pad insulating film 10 described in the first embodiment may be omitted.

  The semiconductor device described above can be manufactured by not performing the step of forming the pad insulating film 10 shown in FIG. 6A in the first embodiment. According to this embodiment, the same effect as that of the first embodiment can be obtained.

(Third embodiment)
FIG. 10 is a cross-sectional view illustrating an example of a semiconductor device according to the third embodiment. In addition, the same code | symbol is attached | subjected to the component same as FIG. 1, and the description is abbreviate | omitted.

  In this embodiment, for example, the pad insulating film 10 a made of silicon oxide is formed only on the inner wall of the element isolation trench 2.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  First, similarly to the first embodiment, the steps shown in FIGS. 2A to 4B are performed. In this embodiment, the dummy element isolation film 14 is removed as shown in FIG. 11A without forming the silicide layers 5 and 9. As a result, the element isolation trench 2 is exposed and formed.

  Next, as shown in FIG. 11B, a pad insulating film 10 made of, for example, silicon oxide is formed on the inner wall of the element isolation trench 2, the source / drain region 8, and the gate electrode 4. For example, the pad insulating film 10 having a thickness of 10 nm to 50 nm is formed.

  Next, as shown in FIG. 12A, a mask layer 15 is formed to fill only the element isolation trench 2. In the formation of the mask layer 15, for example, after a resist film is formed on the entire surface, the resist film is etched back. Thereby, the mask layer 15 made of a resist film can be formed only in the element isolation trench 2.

  Next, as shown in FIG. 12B, the pad insulating film 10 exposed from the mask layer 15 is wet-etched using the mask layer 15 as an etching mask. As a result, the pad insulating film 10 on the source / drain regions 8 and the gate electrode 4 is removed, and the pad insulating film 10 a remains only on the inner wall of the element isolation trench 2. Thereafter, the mask layer 15 is removed.

  Next, as shown in FIG. 13A, a silicide layer 5 is formed on the surface of the gate electrode 4, and a silicide layer 9 is formed on the surface of the source / drain region 8. In this step, for example, a cobalt layer is deposited on the semiconductor substrate 1 so as to cover the gate electrode 4, and the silicide layer 5 and the silicide layer 9 are formed by heat treatment. At this time, since the pad insulating film 10a remains in the element isolation trench 2, no silicide layer is formed. Thereafter, the cobalt layer is removed.

  Next, as shown in FIG. 13B, a silicon nitride film or a silicon oxynitride film is deposited on the entire surface of the pad insulating film 10a, the source / drain regions 8 and the gate electrode 4 to form the liner film 11. Form. For example, the liner film 11 having a thickness of 10 nm to 100 nm is formed. The method for forming the liner film 11 is as described in the first embodiment.

  Next, as shown in FIG. 14A, for example, a silicon oxide film is deposited on the liner film 11 to form the insulating film 12 so as to fill the element isolation trench 2 and the gate electrode 4. The insulating film 12 can be broadly divided into an element isolation insulating film 12 a that fills the element isolation trench 2 and an interlayer insulating film 12 b that covers the gate electrode 4. Here, in the case where appropriate insulating films are different between the element isolation insulating film 12a and the interlayer insulating film 12b, the insulating film 12 may be formed of two or more layers.

  Next, as shown in FIG. 14B, the insulating film 12 is etched using a resist mask to form connection holes 13a reaching the source / drain regions 8, more specifically the silicide layer 9. In this step, first, the insulating film 12 is etched using the liner film 11 as an etching stopper (contact stopper). Thereafter, the liner film 11 exposed in the connection hole 13a is removed. As described above, the liner film 11 is formed with such a film thickness that does not cause defective formation of the connection hole 13a while ensuring a film thickness that can function as an etching stopper. The reaching connection hole 13a can be formed with high accuracy.

  Next, the contact 13 is formed in the connection hole 13a by embedding the connection hole 13a with a conductive material such as tungsten (see FIG. 10). Then, a semiconductor device is manufactured by performing a multilayer wiring formation process.

  The same effects as those of the first embodiment can also be obtained by the semiconductor device manufacturing method according to the present embodiment. In the present embodiment, the dummy element isolation film 14 is removed before the silicide layers 5 and 9 are formed. This is particularly effective when the dummy element isolation film 14 cannot be selectively etched with respect to the silicide layer. Further, it is possible to prevent the silicide layers 5 and 9 from being damaged when the dummy element isolation film 14 is etched.

The present invention is not limited to the description of the above embodiment.
For example, the materials and numerical values given in the present embodiment are examples, and the present invention is not limited to these. For example, the formation process of the transistor illustrated in FIGS.
In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing which shows an example of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. FIG. 10 is a process cross-sectional view in the gate width direction during the manufacture of the semiconductor device according to the first embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 3rd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 3rd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 3rd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 3rd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... Pillar, 2 ... Element isolation groove, 3 ... Gate insulating film, 4 ... Gate electrode, 5 ... Silicide layer, 6 ... Side wall insulating film, 7 ... Extension area | region, 8 ... Source / drain area | region , 9 ... Silicide layer, 10, 10a ... Pad insulating film, 11 ... Liner film, 12 ... Insulating film, 12a ... Element isolation insulating film, 12b ... Interlayer insulating film, 13 ... Contact, 13a ... Connection hole, 14 ... Dummy element Separation membrane, 14a ... divot, 15 ... mask layer

Claims (6)

An element isolation insulating film formed on a semiconductor substrate;
A gate electrode formed on the semiconductor substrate;
Two semiconductor regions serving as a source or drain formed on the semiconductor substrate on both sides of the gate electrode;
A semiconductor device comprising: a liner film that is formed continuously from the interface between the element isolation insulating film and the semiconductor substrate to the semiconductor region and the gate electrode, and applies stress to the semiconductor substrate. The element isolation insulating film is formed by being embedded in an element isolation trench formed in the semiconductor substrate,
The semiconductor device according to claim 1, wherein the liner film is continuously formed from an inner wall of the element isolation trench to the semiconductor substrate and the gate electrode. An interlayer insulating film formed in an upper layer of the semiconductor substrate;
A contact formed through the interlayer insulating film and the liner film and connected to the two semiconductor regions;
The semiconductor device according to claim 1, further comprising: Forming a dummy element isolation film for partitioning an active region on the semiconductor substrate;
Forming a gate electrode on the semiconductor substrate in the active region;
Forming two semiconductor regions to be a source or a drain on the semiconductor substrate on both sides of the gate electrode;
Removing the dummy element isolation film and forming an element isolation groove in the semiconductor substrate;
Forming a liner film on the inner wall of the element isolation trench, on the semiconductor region and on the gate electrode;
And a step of forming an insulating film on the liner film so as to fill the element isolation trench. The semiconductor device manufacturing method according to claim 4, further comprising a step of forming a pad insulating film on at least an inner wall of the element isolation groove before the step of forming the liner film after the step of forming the element isolation groove. Method. In the step of forming the insulating film, an insulating film that fills the element isolation trench and covers the gate electrode and the semiconductor region is formed,
After the step of forming the insulating film, forming a connection hole in the insulating film and the liner film on the semiconductor region;
The method for manufacturing a semiconductor device according to claim 4, further comprising: embedding a conductive material in the connection hole and forming a contact connected to the semiconductor region.

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