JP2010165907A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent chipping from being formed in an active area and an element separation area, when forming a contact hole, in a semiconductor device different each other in a film thickness of a liner film in the first area and a film thickness of a liner film in the second area. <P>SOLUTION: An area between gate structures adjacent each other is opened in each of the liner film 22b and an interlayer insulating film 23 in the first area arranged densely with the gate structures Gb, to form the first contact hole 28r remaining with the liner film having the first film thickness in a bottom part. Then, an area between the gate structures adjacent each other is opened in each of the liner film and an interlayer insulating film in the second area arranged thinly with the gate structures Gb, to form the second contact hole 34r remaining with the liner film having the second film thickness in a bottom part. The liner film remaining in the bottom part of the first contact hole, and the liner film remaining in the bottom part of the second contact hole, are removed thereafter. The first film thickness is equal to the second film thickness. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a contact in a semiconductor device having a liner film.

  In recent years, in response to a demand for higher performance of semiconductor devices, miniaturization of transistors has progressed in order to increase the number of transistors integrated per chip, and ultra-fine transistors of 45 nm nodes are now mass-produced. However, even if the transistor size is simply reduced according to Moore's Law, the capability of the transistor cannot be ensured, and a desired device characteristic cannot be obtained due to a decrease in the driving power of the transistor due to a decrease in carrier mobility. It has become apparent.

  In order to solve this problem, a technique for applying stress to the channel region has been proposed as a technique for improving the driving force of the transistor. As a method for applying stress to the channel region, first, for example, a film having a lattice constant different from the lattice constant of the semiconductor substrate is embedded in the source / drain region, and tensile stress is applied to the channel region of the N-type MOS transistor, or A technique for applying compressive stress to the channel region of a P-type MOS transistor has been proposed. Second, for example, a technique of providing a liner film having a tensile stress on a P-type MOS transistor while providing a liner film having a tensile stress on an N-type MOS transistor ("Dual Stress Liner technique"). ) Has been proposed.

  Hereinafter, a conventional method for manufacturing a semiconductor device using the dual stress liner technique will be described with reference to FIGS. 15A to 15D and FIGS. 16A to 16C (for example, Patent Document 1). reference). FIG. 15A to FIG. 16C are cross-sectional views of relevant steps showing a conventional method of manufacturing a semiconductor device in the order of steps. Here, in FIG. 15A to FIG. 16C, the “NMOS region” is shown on the left side, and the “PMOS region” is shown on the right side. The “NMOS region” refers to a region where an N-type MOS transistor is formed. On the other hand, the “PMOS region” refers to a region where a P-type MOS transistor is formed.

  First, as shown in FIG. 15A, an element isolation region 101 is formed on the semiconductor substrate 100. Thus, the active region 100a is formed in the semiconductor substrate 100 in the NMOS region, while the active region 100b is formed in the semiconductor substrate 100 in the PMOS region.

  Next, after sequentially forming gate insulating films 102a and 102b and gate electrodes 103a and 103b on the active regions 100a and 100b, offset spacers 104a and 104b are formed on the side surfaces of the gate electrodes 103a and 103b. Thereafter, an N-type extension region 105a is formed below the side of the gate electrode 103a in the active region 100a, while a P-type extension region 105b is formed below the side of the gate electrode 103b in the active region 100b.

  Next, as shown in FIG. 15 (b), on the side surfaces of the gate electrodes 103a and 103b, the side walls including the inner side walls 106a and 106b and the outer side walls 107a and 107b are provided via the offset spacers 104a and 104b. 107A and 107B are formed. Thereafter, an N-type source / drain region 108a is formed under the side wall 107A in the active region 100a, while a P-type source / drain region 108b is formed under the side wall 107B in the active region 100b. .

  Thereafter, silicide layers 109a1 and 109b1 are formed on the source / drain regions 108a and 108b, and silicide layers 109a2 and 109b2 are formed on the gate electrodes 103a and 103b.

  In this way, the gate structure (N-type MOS transistor) Ga and the gate structure (P-type MOS transistor) Gb are formed on the semiconductor substrate 100.

  Next, as shown in FIG. 15C, a first liner film 110 having a tensile stress and an insulating film 111 are sequentially formed on the entire surface of the semiconductor substrate 100.

  Next, as shown in FIG. 15D, the insulating film 111 in the PMOS region is removed by dry etching using a resist (not shown) covering the NMOS region as a mask, and the insulating film 111a is left. Remove the resist. Thereafter, using the insulating film 111a as a mask, the first liner film 110 in the PMOS region is removed by dry etching to leave the first liner film 110a.

  Next, as shown in FIG. 16A, a second liner film 112 having a compressive stress is formed on the entire surface of the semiconductor substrate 100.

  Next, as shown in FIG. 16B, using the resist (not shown) covering the PMOS region as a mask, the second liner film 112 in the NMOS region is removed by dry etching, and the second liner film 112b is formed. To remain.

  Next, as shown in FIG. 16C, an interlayer insulating film 113 is formed on the entire surface of the semiconductor substrate 100.

  Thereafter, although not shown, a resist pattern in which contact hole forming holes are formed is formed on the interlayer insulating film 113. Thereafter, using the resist pattern as a mask, the interlayer insulating film 113, the insulating film 111a, and the first liner film 110a in the NMOS region are sequentially etched to form a contact hole that exposes the upper surface of the silicide layer 109a1. At the same time, using the resist pattern as a mask, the interlayer insulating film 113 and the second liner film 112b in the PMOS region are sequentially etched to form a contact hole that exposes the upper surface of the silicide layer 109b1. Thereafter, a contact is formed in the contact hole.

  As described above, a conventional semiconductor device is manufactured.

  Here, as shown in FIG. 17A, for example, in the PMOS region, the second liner film 112b in the “dense region” in which the interval between the gate electrodes 103b is narrow is formed so as to be embedded between the gate electrodes 103b. The gate electrode 103b is formed thicker than the second liner film 112b in the “sparse region” where the distance between the gate electrodes 103b is wide. Therefore, the etching time required to remove the second liner film 112b in the dense region is longer than the etching time required to remove the second liner film 112b in the sparse region. However, conventionally, the second liner film 112b in the dense region and the sparse region must be removed by one etching.

  Therefore, first, for example, when the etching time of the second liner film 112b is set to the etching time required to remove the second liner film 112b in the dense region, as shown in FIG. In the formation of the contact hole 114s in the sparse region, when a resist pattern (not shown) is misaligned (the contact hole forming hole of the resist pattern is located across the element isolation region 101 and the active region 100a). In some cases, excessive over-etching causes scraping in the active region 100b and the element isolation region 101, resulting in increased junction leakage. This problem occurs remarkably in the case of a contact hole in which the amount of overlap between the contact hole and the active region is small, such as so-called “borderless contact”.

  On the other hand, for example, when the etching time of the second liner film 112b is set to the etching time required to remove the second liner film 112b in the sparse region, as shown in FIG. In the formation of the contact hole 114c in the dense region, there is a problem that the second liner film 112b cannot be completely removed due to insufficient etching and an open failure of the contact hole 114c occurs.

  In FIG. 17A, the dense region and the sparse region in the PMOS region are shown, and the problem in the sparse region in the PMOS region will be described with reference to FIG. 17B, and the problem in the dense region in the PMOS region will be described. 17 (c), the problem similar to the problem in the sparse region in the PMOS region (that is, the active region 100a and the element isolation region 101 are scraped) also in the sparse region in the NMOS region. In the dense region in the NMOS region, there is a problem similar to the problem in the dense region in the PMOS region (that is, a problem that a contact hole open defect occurs).

  By the way, a non-photosensitive organic film is used as a method for preventing the active region and the element isolation region from being scraped when a resist pattern shift occurs in, for example, the formation of SAC (self-aligned contact). The technique which performs is proposed (for example, refer patent document 2).

  Here, as a method for forming an existing SAC, there is the following method. Using the first resist pattern as a mask, the liner film on the gate electrode (etching stopper film) and the liner film on the source / drain regions are removed by the first etching. Thereafter, after forming an interlayer insulating film, the second insulating pattern is used as a mask to remove the interlayer insulating film by a second etching to form a contact hole.

  However, when a resist pattern shift occurs, the active region and the element isolation region are excessively over-etched during the second etching, and a cut is formed in the active region and the element isolation region.

Therefore, in the technique described in Patent Document 2, the non-photosensitive organic film is embedded in the recesses between the gate electrodes before the first etching, so that the active region and the element isolation region are scraped. To prevent that.
JP 2007-208166 A JP 2001-217200 A

  However, in the technique described in Patent Document 2, although it is possible to prevent the active region and the element isolation region from being scraped in the semiconductor device having the same film thickness over the entire region, In a semiconductor device in which the thickness of the liner film in the first region (for example, the dense region) and the thickness of the liner film in the second region (for example, the sparse region) are different from each other, the active region and the element isolation region are scraped. It cannot be prevented.

  In view of the above, the present invention provides a semiconductor device in which the thickness of the liner film in the first region and the thickness of the liner film in the second region are different from each other in the active region and the element isolation region when the contact hole is formed. It is to prevent the shaving from being formed.

  In order to solve the above problems, a first method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a plurality of gate structures on a semiconductor substrate, and a plurality of methods on a semiconductor substrate. (B) sequentially forming a liner film and an interlayer insulating film so as to cover the gate structure, and a gate structure adjacent to the liner film and the interlayer insulating film in the first region where the gate structures are densely arranged A step (c) of forming a first contact hole in which a liner film having a first film thickness is left at the bottom by opening a region between the bodies, and a second in which the gate structures are arranged sparsely A step of opening a region between adjacent gate structures in the liner film and the interlayer insulating film in the region, and forming a second contact hole in which the liner film having the second film thickness remains at the bottom ( d) and step (c) And a step (e) of removing the liner film remaining at the bottom of the first contact hole and the liner film remaining at the bottom of the second contact hole after the step (d), The thickness and the second film thickness are equal to each other.

  According to the first method for manufacturing a semiconductor device of the present invention, the liner film having the first film thickness on the bottom before the liner film remaining on the bottom of the first and second contact holes is removed. Forming the first contact hole in which the first film is left and the step of forming the second contact hole in which the liner film having the second film thickness is left on the bottom, The film thickness and the second film thickness can be controlled independently, and the first film thickness and the second film thickness can be controlled equally. Therefore, in the step of removing the liner film remaining at the bottom of the first and second contact holes, the amount of overetching of the liner film having the first film thickness and the overetching of the liner film having the second film thickness are performed. The amount can be controlled equally.

  Therefore, in the second region (sparse region), when the contact hole is formed, it is possible to prevent the active region or the element isolation region from being scraped by excessive overetching, and to prevent an increase in junction leakage. it can. At the same time, in the first region (dense region), when the contact hole is formed, it is possible to prevent the contact hole from being opened due to insufficient etching.

  A method for manufacturing a second semiconductor device according to the present invention includes a step (a) of forming a first gate structure, a second gate structure, and a third gate structure on a semiconductor substrate; (B) sequentially forming a liner film and an interlayer insulating film on the semiconductor substrate so as to cover the first gate structure, the second gate structure, and the third gate structure; A first contact hole in which a region between the first gate structure and the second gate structure adjacent to each other is opened in the interlayer insulating film, and the liner film having the first film thickness remains at the bottom. Forming a region between the second gate structure and the third gate structure adjacent to each other in the liner film and the interlayer insulating film, and forming a second film thickness at the bottom For forming a second contact hole in which a liner film having a film remains (D) and the step of removing the liner film remaining at the bottom of the first contact hole and the liner film remaining at the bottom of the second contact hole after the steps (c) and (d) (e The planar shape of the first contact hole and the second contact hole is a rectangular shape in which the length in the gate width direction is longer than the length in the gate length direction, and the first film thickness and the second contact hole are The film thickness is equivalent.

  According to the second method of manufacturing a semiconductor device of the present invention, in the step of removing the liner film remaining at the bottoms of the first and second contact holes, the overetching amount of the liner film having the first film thickness The overetching amount of the liner film having the second film thickness can be controlled equally.

  In addition, by forming the first contact hole and the second contact hole independently, the distance between the first and second contact holes is reduced, and the contact hole density is increased. It is possible to increase the density of contacts having a rectangular planar shape. That is, since the distance between the contact holes can be reduced, the gate structure can be further miniaturized, and even if the distance between the adjacent gate structures is reduced, a problem is caused. The contact hole can be formed without any problem.

  Further, by making the planar shape of the first and second contact holes rectangular, first and second contacts having a rectangular planar shape are formed in the first and second contact holes. be able to. Therefore, even if the gate structure is further miniaturized, a sufficient contact area between the contact and the active region can be ensured, so that an increase in contact resistance can be suppressed.

  The third method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a gate structure on a semiconductor substrate, and a liner film and interlayer insulation on the semiconductor substrate so as to cover the gate structure. A step (b) of sequentially forming a film, and opening a first partial region in a region extending from the gate electrode constituting the gate structure to the source / drain region in the liner film and the interlayer insulating film; A step (c) of forming a first contact hole in which a liner film having a first film thickness remains on the bottom, and a source / drain region on the liner film and the interlayer insulating film from above the gate electrode constituting the gate structure A step (d) of forming a second contact hole in which the second partial region of the region extending upward is opened and the liner film having the second film thickness remains at the bottom, and the step (c), After step (d) Removing the liner film remaining at the bottom of the first contact hole and the liner film remaining at the bottom of the second contact hole to form a first combined contact comprising the first contact hole and the second contact hole; A step (e) of forming a hole, wherein the first contact hole and the second contact hole are adjacent to each other along the gate length direction, and a portion of the first contact hole and the second contact hole A part of the contact hole is disposed so as to overlap each other, and the planar shape of the first contact hole and the second contact hole is a circular shape or a square shape with rounded corners. The film thickness of 2 is equivalent.

  According to the third method of manufacturing a semiconductor device of the present invention, in the step of removing the liner film remaining at the bottoms of the first and second contact holes, the overetching amount of the liner film having the first film thickness The overetching amount of the liner film having the second film thickness can be controlled equally.

  In the third method for fabricating a semiconductor device according to the present invention, in the step (c), the liner film and the interlayer insulating film are formed in the first of the regions extending from the gate electrode constituting the gate structure to the source / drain region. And forming a third contact hole in which the liner film having the third film thickness remains at the bottom, and the step (d) includes forming a gate on the liner film and the interlayer insulating film. Opening a fourth partial region in the region extending from the gate electrode constituting the structure to the source / drain region, a fourth contact hole in which a liner film having a fourth film thickness remains at the bottom is formed. The step (e) includes the step of forming the third contact hole by removing the liner film remaining at the bottom of the third contact hole and the liner film remaining at the bottom of the fourth contact hole. Forming a second merged contact hole comprising a fourth contact hole, and the first merged contact hole and the second merged contact hole are adjacent to each other at a distance along the gate width direction. And the first contact hole and the third contact hole are arranged to face each other along the gate width direction, and the third contact hole and the fourth contact hole are arranged opposite to each other along the gate length direction. The holes are adjacent to each other along the gate length direction, and a part of the third contact hole and a part of the fourth contact hole are arranged so as to overlap each other, and the third contact hole and the fourth contact The planar shape of the hole is a circular shape or a square shape with rounded corners, and the third film thickness and the fourth film thickness are the first film thickness and the second film thickness. It is preferably equal to the film thickness.

  In this way, the planar shape forms a first combined contact hole made up of the first and second contact holes having a square shape with rounded corners or a circular shape, and the planar shape has a corner portion. Forming a second combined contact hole made of a third or a fourth contact hole having a rounded square shape or a circular shape, whereby the first and first adjacent ones spaced apart from each other along the gate width direction are formed. The interval between the second merged contact holes can be reduced to increase the density of the merged contact holes, thereby increasing the density of the merged contacts.

  In the first to third semiconductor device manufacturing methods according to the present invention, the step (d) is performed after the step (c) and before the step (e), and after the step (c). In addition, it is preferable to further include a step (f) of embedding an organic film in the first contact hole before the step (d).

  In the first to third semiconductor device manufacturing methods according to the present invention, the step (c) is performed after the step (d) and before the step (e), and after the step (d). In addition, it is preferable to further include a step (g) of embedding an organic film inside the second contact hole before the step (c).

  According to the semiconductor device manufacturing method of the present invention, in the semiconductor device in which the thickness of the liner film in the first region (for example, a dense region) and the thickness of the liner film in the second region (for example, a sparse region) are different from each other, When the contact hole is formed, the active region and the element isolation region can be prevented from being scraped, and an increase in junction leakage can be prevented. In addition, the distance between contact holes can be reduced, the contact hole density can be increased, and the contact density can be increased. That is, since the distance between contact holes can be reduced, the gate structure (transistor) can be further miniaturized, and the distance between adjacent gate structures can be reduced. Contact holes can be formed without incurring defects.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
In the following, the semiconductor device manufacturing method according to the first embodiment of the present invention will be described with reference to FIGS. 1 (a) to (d), FIGS. 2 (a) to (c), and FIGS. 3 (a) to (d). ) And FIGS. 4 (a) to 4 (c). FIG. 1A to FIG. 4C are principal part process cross-sectional views illustrating the method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of processes. Here, in FIGS. 1A to 2C, the “NMOS region” is shown on the left side and the “PMOS region” is shown on the right side. The “NMOS region” refers to a region where an N-type MOS transistor is formed. On the other hand, the “PMOS region” refers to a region where a P-type MOS transistor is formed.

  First, as shown in FIG. 1A, an element isolation region 11 in which a silicon oxide film is buried in a trench having a depth of, for example, 300 nm is formed on a semiconductor substrate 10 by STI (Shallow Trench Isolation). As a result, an active region 10a surrounded by the element isolation region 11 is formed in the semiconductor substrate 10 in the NMOS region, and an active region 10b surrounded by the element isolation region 11 is formed in the semiconductor substrate 10 in the PMOS region. The

  Next, a gate insulating film forming film having a thickness of 2 nm and a gate electrode forming film made of a polysilicon film having a thickness of 100 nm, for example, are sequentially formed on the semiconductor substrate 10. Thereafter, the gate electrode forming film and the gate insulating film forming film are sequentially patterned by etching to form the gate insulating film 12a and the gate electrode 13a sequentially on the active region 10a, and the gate insulating film on the active region 10b. A film 12b and a gate electrode 13b are sequentially formed.

Next, a silicon oxide film having a thickness of, for example, 10 nm is formed on the entire surface of the semiconductor substrate 10. Thereafter, the entire surface of the silicon oxide film is etched by etch back until the surface of the semiconductor substrate 10 is exposed, thereby forming offset spacers 14a and 14b on the side surfaces of the gate electrodes 13a and 13b. Thereafter, using the gate electrode 13a and the offset spacer 14a as a mask, the active region 10a is ion-implanted with, for example, As ⁺ , an acceleration voltage of, for example, 1.5 keV, and a dose of, for example, 1 × 10 ¹⁵ cm ^−2. An N-type extension region 15a is formed in a self-aligned manner in a region located on the lower side of the gate electrode 12a in 10a. On the other hand, using the gate electrode 13b and the offset spacer 14b as a mask, for example, BF ²⁺ is ion-implanted into the active region 10b with an acceleration voltage of, for example, 3 keV and a dose of, for example, 5 × 10 ¹⁴ cm ^−2. A P-type extension region 15b is formed in a self-aligned manner in a region located on the lower side of the gate electrode 12b.

Next, as shown in FIG. 1B, after a silicon oxide film having a film thickness of, for example, 10 nm is formed on the semiconductor substrate 10 so as to cover the gate electrodes 13a and 13b and the offset spacers 14a and 14b, For example, a silicon nitride film having a thickness of 30 nm is formed on the silicon oxide film. Thereafter, the silicon nitride film and the silicon oxide film are sequentially etched by the entire surface etch back until the surface of the semiconductor substrate 10 is exposed, and the inner side walls 16a and 16b and the outer side are formed on the side surfaces of the offset spacers 14a and 14b. Sidewalls 17A and 17B composed of the side walls 17a and 17b are formed. Thereafter, using the gate electrode 13a, the offset spacer 14a, and the sidewall 17A as a mask, ions of, for example, As ⁺ are implanted into the active region 10a with an acceleration voltage of, for example, 15 keV and a dose of, for example, 7 × 10 ¹⁴ cm ⁻² . N-type source / drain regions 18a are formed in a self-aligned manner in a region located on the lower side of the sidewall 17A in the active region 10a. On the other hand, using the gate electrode 13b, the offset spacer 14b, and the sidewall 17B as a mask, for example, BF ²⁺ is ionized into the active region 10b with an acceleration voltage of, for example, 3.5 keV and a dose of, for example, 2 × 10 ¹⁵ cm ⁻² . Implanted, a P-type source / drain region 18b is formed in a self-aligned manner in a region located laterally below the sidewall 17B in the active region 10b.

  Next, after a silicon oxide film (not shown) having a film thickness of, for example, 10 nm is formed on the entire surface of the semiconductor substrate 10, a resist (FIG. 5) covering a non-silicide formation region in which no silicide layer is formed on the silicon oxide film. (Not shown), and then etching is performed to remove portions formed in regions other than the non-silicide formation region (that is, silicide formation regions) of the silicon oxide film, and the surfaces of the source / drain regions 18a and 18b, The upper surfaces of the gate electrodes 13a and 13b are exposed. Thereafter, after removing the resist by ashing / cleaning treatment, a metal film (not shown) made of Ni having a film thickness of, for example, 5 nm is formed on the entire surface of the semiconductor substrate 10 by sputtering. Thereafter, silicide layers 19a1 and 19b1 made of nickel silicide are formed on the source / drain regions 18a and 18b by rapid thermal processing, and silicide layers 19a2 and 19b2 made of nickel silicide are formed on the gate electrodes 13a and 13b. Form. Thereafter, the unreacted metal film (that is, the portion formed in the non-silicide formation region of the metal film) is removed by SPM cleaning.

  In this way, gate structures Ga and Gb are formed on the semiconductor substrate 10.

  Here, the gate structures Ga and Gb include gate insulating films 12a and 12b formed on the active regions 10a and 10b, gate electrodes 13a and 13b formed on the gate insulating films 12a and 12b, and a gate electrode 13a. , 13b, offset spacers 14a, 14b formed on the side surfaces of the active regions 10a, 10b, extension regions 15a, 15b formed on the sides of the gate electrodes 12a, 12b, and side surfaces of the offset spacers 13a, 13b. Are formed on the side walls 17A and 17B of the active regions 10a and 10b, the source / drain regions 18a and 18b formed on the lower sides of the side walls 17A and 17B, and the source / drain regions 18a and 18b. Silicide layers 19a1, 19b1 and gate electrodes 13a, 1 Formed in an upper portion of the b and a silicide layer 19A2,19b2.

  Next, as shown in FIG. 1 (c), a first surface having a tensile stress, eg, a silicon nitride film having a thickness of 50 nm, is formed on the entire surface of the semiconductor substrate 10 by plasma CVD or LP-CVD. The liner film 20 is formed. Thereafter, an insulating film 21 made of a silicon oxide film having a thickness of, for example, 10 nm is formed on the first liner film 20.

  Next, as shown in FIG. 1 (d), a resist (not shown) that covers the NMOS region and opens the PMOS region is formed on the insulating film 21, and then the insulating film 21 in the PMOS region is formed by dry etching. This is removed to leave the insulating film 21a. Thereafter, the resist is removed by an ashing process. Thereafter, using the insulating film 21a as a mask, the first liner film 20 in the PMOS region is removed by dry etching to leave the first liner film 20a.

  Next, as shown in FIG. 2A, the entire surface of the semiconductor substrate 10 is compressed by a plasma CVD method or an LP-CVD method, and is formed of a silicon nitride film having a thickness of, for example, 50 nm. Two liner films 22 are formed.

  Next, as shown in FIG. 2B, a resist (not shown) that covers the PMOS region and opens the NMOS region is formed on the second liner film 22, and then the second liner film 22 is bonded to the second liner film 22. Then, etching is performed under conditions that are selective to the insulating film 21a, the second liner film 22 in the NMOS region is removed, and the second liner film 22b is left.

  Next, as shown in FIG. 2C, after a silicon oxide film is formed on the entire surface of the semiconductor substrate 10, a planarization process is performed on the silicon oxide film by the CMP method, and the interlayer insulating film 23 is formed. Form.

  In this way, as shown in FIG. 2C, the first liner film 20a, the insulating film 21a, and the interlayer insulating film 23 are formed on the semiconductor substrate 10 in the NMOS region so as to cover the gate structure Ga. The second liner film 22b and the interlayer insulating film 23 are sequentially formed on the semiconductor substrate 10 in the PMOS region so as to cover the gate structure Gb.

  Subsequently, contact holes are formed by using the contact hole forming method in this embodiment. Here, the cross-sectional views shown in FIGS. 3 (a) to 4 (c) are different from the cross-sectional views shown in FIGS. 1 (a) to 2 (c), and represent the PMOS region of FIG. It is described as. In FIG. 3A to FIG. 4C, the “dense area” is shown on the left side and the “sparse area” is shown on the right side. The “dense region” refers to a region where the gate structures Gb are densely arranged (that is, a region where the space between the adjacent gate electrodes 13b is narrow, in other words, the adjacent gate electrode 13b in the second liner film 22b. The thickness of the portion formed between them (the region where the film thickness is thick (see FIG. 3 (a): Tc)). On the other hand, the “sparse region” is a region in which the gate structures Gb are sparsely arranged (that is, a region where the space between the adjacent gate electrodes 13b is wide, in other words, the adjacent gate electrode 13b in the second liner film 22b. This refers to a region where the thickness of the portion formed between them is thin (see FIG. 3A: Ts).

-Formation of multilayer resist pattern-
First, as shown in FIG. 3A, a multilayer resist 27 is formed by sequentially laminating a lower layer resist 24, an intermediate layer resist 25, and an upper layer resist 26 on the interlayer insulating film 23. Thereafter, a hole 26h is formed in the upper layer resist 26 in the dense region to form an upper layer resist pattern.

  Next, as shown in FIG. 3B, the intermediate layer resist 25 and the lower layer resist 24 are sequentially dry etched using the upper layer resist pattern as a mask, and contact holes forming holes 27h are formed in the multilayer resist 27. Then, a multilayer resist pattern is formed.

Here, specific examples of dry etching conditions for the intermediate layer resist 25 include the following examples. For example, a two-frequency RIE etching apparatus is used, CF ₄ / CHF ₃ is used as an etching gas, and a flow rate is CF ₄ / CHF ₃ = 3.34 × 10 ⁻⁶ /0.668×10 ⁻⁶ m ³ / s. The pressure of the etching atmosphere is set to 13.33 Pa, the RF power of the upper electrode is set to 600 W, the RF power of the lower electrode is set to 300 W, and the substrate temperature is set to 20 ° C.

Here, specific examples of the dry etching conditions for the lower layer resist 24 include the following examples. For example, a two-frequency RIE etching apparatus is used, CO / O ₂ / Ar is used as an etching gas, and the flow rate is CO / O ₂ /Ar=1.67×10 ⁻⁶ /0.835×10 ⁻⁶ / 8. .35 × 10 ⁻⁶ m ³ / s, etching atmosphere pressure is 2.00 Pa, upper electrode RF power is 1500 W, lower electrode RF power is 300 W, and substrate temperature is 20 ° C.

-First etching of interlayer insulating film-
Next, with the multilayer resist pattern as a mask, dry etching is performed on the interlayer insulating film 23 until the second liner film 22b is exposed (here, although not shown, as shown in FIG. 3B). In the case where the gate structure Ga is not a dense region where the gate structures Gb are densely arranged but a dense region where the gate structures Ga are densely arranged, the first liner film 20a is formed with respect to the insulating film 21a and the interlayer insulating film 23. Dry etching until is exposed).

Here, specific examples of the dry etching conditions for the interlayer insulating film 23 include the following examples. For example, a two-frequency RIE etching apparatus is used, C ₄ F ₆ / Ar / O ₂ is used as an etching gas, and the flow rate is C ₄ F ₆ / Ar / O ₂ = 0.334 × 10 ⁻⁶ /25.05. × 10 ⁻⁶ /0.301×10 ⁻⁶ m ³ / s, etching atmosphere pressure is 4.00 Pa, upper electrode RF power is 1000 W, lower electrode RF power is 1500 W, and substrate temperature is 20 ° C. .

-First etching of liner film-
Next, dry etching is performed on the second liner film 22b until the thickness of the second liner film 22b reaches, for example, 20 nm (see FIG. 3B: Trc) (here, the gate structure Ga). In the case of a dense region in which the first liner film 20a is densely arranged, dry etching is performed on the first liner film 20a until the thickness of the first liner film 20a becomes 20 nm, for example.

Here, specific examples of the dry etching conditions of the second liner film 22b include the following examples. For example, a two-frequency RIE etching apparatus is used, CHF ₃ / Ar / O ₂ is used as an etching gas, and the flow rate is CHF ₃ / Ar / O ₂ = 0.334 × 10 ⁻⁶ /13.36×10 ^−6. /0.251×10 ⁻⁶ m ³ / s, the pressure of the etching atmosphere is set to 2.67 Pa, the RF power of the upper electrode is set to 1000 W, the RF power of the lower electrode is set to 300 W, and the substrate temperature is set to 20 ° C.

  In this manner, as shown in FIG. 3B, the region between the gate structures Gb adjacent to each other is opened in the second liner film 22b and the interlayer insulating film 23 in the dense region, and the bottom portion The first contact hole 28r in which the second liner film 22b having the first film thickness (specifically, for example, 20 nm) remains is formed.

-Formation of organic film-
Next, as shown in FIG. 3C, the multilayer resist pattern is removed by ashing / cleaning treatment. Thereafter, an organic film is formed on the interlayer insulating film 23 so as to fill the first contact hole 28r. Thereafter, a portion of the organic film formed outside the first contact hole 28r is removed by overall etch back, and an organic film 29 embedded in the first contact hole 28r is formed. At this time, for example, by detecting the end point based on the emission intensity, the upper surface of the organic film 29 embedded in the first contact hole 28r is not positioned below the upper end of the first contact hole 28r. It is preferable to detect the processing time of the entire etch back.

Here, the following example is given as a specific example of the conditions for the entire surface etch back of the organic film. For example, an RIE type etching apparatus is used, O ₂ is used as an etching gas, the flow rate is O ₂ = 3.34 × 10 ⁻⁶ m ³ / s, the pressure of the etching atmosphere is 10.00 Pa, and the RF power of the upper electrode is set. 400 W, the RF power of the lower electrode is set to 400 W, and the substrate temperature is set to 20 ° C.

-Formation of multilayer resist pattern-
Next, as shown in FIG. 3D, a multilayer resist 33 is formed on the interlayer insulating film 23 and the organic film 29 by sequentially laminating the lower layer resist 30, the intermediate layer resist 31, and the upper layer resist 32. . Thereafter, a hole 32h is formed in the upper layer resist 32 to form an upper layer resist pattern.

  Next, as shown in FIG. 4A, the intermediate layer resist 31 and the lower layer resist 30 are sequentially dry-etched using the upper layer resist pattern as a mask, and contact holes forming holes 33h are formed in the multilayer resist 33. Then, a multilayer resist pattern is formed. Here, specific examples of the dry etching conditions for the intermediate layer resist 31 and the lower layer resist 30 include the same conditions as the dry etching conditions for the intermediate layer resist 25 and the lower layer resist 24 in the step shown in FIG. It is done.

-Second etching of interlayer insulating film-
Next, using the multilayer resist pattern as a mask, dry etching is performed on the interlayer insulating film 23 until the second liner film 22b is exposed (here, in the case of a sparse region where the gate structures Ga are sparsely arranged). Then, dry etching is performed on the insulating film 21a and the interlayer insulating film 23 until the first liner film 20a is exposed). Here, specific examples of the dry etching conditions for the interlayer insulating film 23 include, for example, the same conditions as the dry etching conditions for the interlayer insulating film 23 in the step shown in FIG.

-Second etching of liner film-
Next, dry etching is performed on the second liner film 22b until the thickness of the second liner film 22b reaches, for example, 20 nm (see FIG. 4A: Trs) (here, the gate structure Ga). In the case of a sparse region in which sparsely arranged, dry etching is performed on the first liner film 20a until the thickness of the first liner film 20a becomes 20 nm, for example. Here, specific examples of the dry etching conditions for the second liner film 22b include the same conditions as the dry etching conditions for the second liner film 22b in the step shown in FIG. 3B.

  In this way, as shown in FIG. 4A, the region between the gate structures Gb adjacent to each other is opened in the second liner film 22b and the interlayer insulating film 23 in the sparse region, and the bottom portion Then, a second contact hole 34r in which the second liner film 22b having the second film thickness (specifically, for example, 20 nm) remains is formed.

-Removal of organic film-
Next, as shown in FIG. 4B, the multilayer resist pattern and the organic film 29 are removed by ashing / cleaning treatment.

  In this way, as shown in FIG. 4B, the first and second contact holes 28r and 34r having the same film thickness of the second liner film 22b remaining at the bottom are formed.

-Third etching of liner film-
Next, as shown in FIG. 4C, by dry etching, the second liner film 22b remaining at the bottom of the first contact hole 28r and the second liner film remaining at the bottom of the second contact hole 34r. The liner film 22b is removed, and first and second contact holes 28 and 34 where the silicide layer 19b1 is exposed are formed at the bottom (here, a gate structure Gb as shown in FIG. 4C is disposed). In the case where the gate structure Ga is disposed (that is, the NMOS region) instead of the region (that is, the PMOS region), the first liner film and the second contact hole remaining at the bottom of the first contact hole. The first liner film remaining at the bottom is removed, and first and second contact holes are formed in the bottom to expose the silicide layer 19a1).

Here, specific examples of the dry etching conditions of the second liner film 22b include the following examples. For example, a two-frequency RIE etching apparatus is used, CHF ₃ / Ar / O ₂ is used as an etching gas, and the flow rate is CHF ₃ / Ar / O ₂ = 0.334 × 10 ⁻⁶ /13.36×10 ^−6. /0.251×10 ⁻⁶ m ³ / s, the pressure of the etching atmosphere is set to 2.67 Pa, the RF power of the upper electrode is set to 1000 W, the RF power of the lower electrode is set to 300 W, and the substrate temperature is set to 20 ° C.

  Thereafter, although not shown, first and second contacts are formed in the first and second contact holes 28 and 34, with a conductive film embedded through a barrier metal film.

  As described above, the semiconductor device according to this embodiment can be manufactured.

  According to this embodiment, before performing the third etching of the liner film (see FIG. 4C), the first etching of the liner film (see FIG. 3B) and the second etching of the liner film (see FIG. 4). (see (a)) are performed independently, the second liner film (hereinafter referred to as “first residual film”) remaining at the bottom of the first contact hole, and the second The film thickness of the second liner film (hereinafter referred to as “second residual film”) remaining at the bottom of the contact hole is independently controlled, and the first residual film and the second residual film are controlled. It can be controlled to an equivalent film thickness. Therefore, in the third etching of the liner film, the amount of overetching of the first remaining film and the amount of overetching of the second remaining film can be controlled equally.

  Therefore, when the contact hole is formed in the sparse region, it is possible to prevent the active region or the element isolation region from being scraped due to excessive overetching, and to prevent an increase in junction leakage. At the same time, it is possible to prevent an open defect of the contact hole due to insufficient etching when forming the contact hole in the dense region.

  In addition, the first remaining film and the second remaining film are made thin (specifically, for example, 20 nm), so that the first remaining film and the second remaining film are formed in the third etching of the liner film. Therefore, it is possible to effectively prevent the active region or the element isolation region from being scraped.

  In the present embodiment, as a method for controlling the first remaining film (see FIG. 3B: Trc) and the second remaining film (see FIG. 4A: Trs) to the same film thickness, As shown in FIG. 3B, after the first etching of the interlayer insulating film is performed in the dense region, the first etching of the liner film is performed until the thickness of the first remaining film reaches 20 nm, and then As shown in FIG. 4A, after the second etching of the interlayer insulating film is performed in the sparse region, the second etching of the liner film is performed until the thickness of the second remaining film reaches 20 nm. However, the present invention is not limited to this.

  For example, after the first etching of the interlayer insulating film in the dense region, the thickness of the first residual film is the thickness of the portion formed between the gate electrodes 13b in the second liner film 22b in the sparse region. The liner film in the dense region may be subjected to the first etching until the time (see FIG. 3A: Ts), and then the interlayer insulating film in the sparse region may be subjected to the second etching. This eliminates the need for the second etching of the liner film in the sparse region.

  Further, in the present embodiment, in the step shown in FIG. 3B, the case where the first contact hole 28r is formed in the second liner film 22b and the interlayer insulating film 23 using the multilayer resist pattern as a mask is specifically described. Although described as an example, the present invention is not limited to this, and a single layer resist pattern may be used instead of the multilayer resist pattern. Similarly, in the step shown in FIG. 4A, a case where the second contact hole 34r is formed in the second liner film 22b and the interlayer insulating film 23 using the multilayer resist pattern as a mask will be described as a specific example. Although described, the present invention is not limited to this, and a single layer resist pattern may be used instead of the multilayer resist pattern.

(Second Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 5 (a) to (b), FIGS. 6 (a) to (c), and FIGS. 7 (a) to (b). Will be described with reference to FIG. FIG. 5A to FIG. 7B are cross-sectional views of relevant steps showing a semiconductor device manufacturing method according to the second embodiment of the present invention in the order of steps. In FIG. 5 (a) to FIG. 7 (b), the same reference numerals as those shown in FIG. 1 (a) to FIG. 2 (c) are given to the same constituent elements as those in the first embodiment. Attached. Therefore, in this embodiment, the description common to the first embodiment is omitted as appropriate.

  First, steps similar to those shown in FIGS. 1A to 2C in the first embodiment are sequentially performed.

  Subsequently, contact holes are formed by using the contact hole forming method in this embodiment. Here, the sectional views shown in FIGS. 5A to 7B in this embodiment are different from the sectional views shown in FIGS. 1A to 2C in the first embodiment. The PMOS region of FIG. 2 is shown as a representative. 5A to 7B show a region (specifically, for example, an SRAM region) in which three gate structures Gb are densely arranged.

-Formation of multilayer resist pattern-
First, as shown in FIG. 5A, a multilayer resist 27 is formed by sequentially laminating a lower layer resist 24, an intermediate layer resist 25, and an upper layer resist 26 on the interlayer insulating film 23. Thereafter, holes 26hx are formed in the upper layer resist 26 to form an upper layer resist pattern. At this time, as shown in FIG. 5A, the hole 26hx is formed so that the planar shape thereof is a rectangular shape whose width in the gate width direction is longer than the width in the gate length direction.

  Next, as shown in FIG. 5B, the intermediate layer resist 25 and the lower layer resist 24 are sequentially dry-etched using the upper layer resist pattern as a mask, and contact holes forming holes 27hx are formed in the multilayer resist 27. Then, a multilayer resist pattern is formed. Here, as a specific example of the dry etching conditions of the intermediate layer resist 25 and the lower layer resist 24, for example, the dry etching conditions of the intermediate layer resist 25 and the lower layer resist 24 in the step shown in FIG. 3B of the first embodiment. The same conditions are mentioned.

-First etching of interlayer insulating film-
Next, dry etching is performed on the interlayer insulating film 23 using the multilayer resist pattern as a mask until the second liner film 22b is exposed (not shown here, as shown in FIG. 5B). In the case where the gate structure Ga is not a region where the gate structures Gb are densely arranged but a region where the gate structures Ga are densely arranged, the first liner film 20a is exposed to the insulating film 21a and the interlayer insulating film 23. Until dry etching). Here, as a specific example of the dry etching conditions of the interlayer insulating film 23, for example, the same conditions as the dry etching conditions of the interlayer insulating film 23 in the step shown in FIG. .

-First etching of liner film-
Next, dry etching is performed on the second liner film 22b until the film thickness of the second liner film 22b reaches, for example, 20 nm (in the case where the gate structure Ga is a densely arranged region, (Dry etching is performed on the first liner film 20a until the thickness of the first liner film 20a reaches, for example, 20 nm). Here, as a specific example of the dry etching conditions for the second liner film 22b, for example, conditions similar to the dry etching conditions for the second liner film 22b in the step shown in FIG. 3B of the first embodiment are used. Is mentioned.

  In this way, as shown in FIG. 5 (b), the second liner film 22b and the interlayer insulating film 23 are opened in the region between the gate structures Gb adjacent to each other, and the first portion is formed at the bottom. The first contact hole 28rx in which the second liner film 22b having a thickness of 20 nm (specifically, for example, 20 nm) remains is formed. Here, as shown in FIG. 5B, the planar shape of the first contact hole 28rx is a rectangular shape in which the width in the gate width direction is longer than the width in the gate length direction.

-Formation of organic film-
Next, as shown in FIG. 6A, the multilayer resist pattern is removed by ashing / cleaning treatment. Thereafter, an organic film is formed on the interlayer insulating film 23 so as to fill the first contact hole 28rx. Thereafter, the portion of the organic film formed outside the first contact hole 28rx is removed by overall etch back to form the organic film 29x embedded in the first contact hole 28rx. At this time, for example, endpoint detection based on emission intensity is performed so that the upper surface of the organic film 29x embedded in the first contact hole 28rx is not located below the upper end of the first contact hole 28rx. Thus, it is preferable to detect the processing time of the entire surface etch back. Here, as a specific example of the whole-surface etch-back condition of the organic film, for example, the same condition as the whole-surface etch-back condition of the organic film in the step shown in FIG.

-Formation of multilayer resist pattern-
Next, as shown in FIG. 6B, a multilayer resist 33 is formed by sequentially laminating a lower layer resist 30, an intermediate layer resist 31, and an upper layer resist 32 on the interlayer insulating film 23 and the organic film 29x. . Thereafter, a hole 32hx is formed in the upper layer resist 32 to form an upper layer resist pattern. At this time, the hole 32hx is formed so that the planar shape thereof is a rectangular shape whose width in the gate width direction is longer than the width in the gate length direction.

  Next, as shown in FIG. 6C, the intermediate layer resist 31 and the lower layer resist 30 are sequentially dry-etched using the upper layer resist pattern as a mask, and contact holes forming holes 33hx are formed in the multilayer resist 33. Then, a multilayer resist pattern is formed. Here, specific examples of the dry etching conditions for the intermediate layer resist 31 and the lower layer resist 30 include the same conditions as the dry etching conditions for the intermediate layer resist 25 and the lower layer resist 24 in the step shown in FIG. It is done.

-Second etching of interlayer insulating film-
Next, using the multilayer resist pattern as a mask, dry etching is performed on the interlayer insulating film 23 until the second liner film 22b is exposed (here, in the case where the gate structure Ga is densely arranged, Dry etching is performed on the insulating film 21a and the interlayer insulating film 23 until the first liner film 20a is exposed). Here, specific examples of the dry etching conditions for the interlayer insulating film 23 include the same conditions as the dry etching conditions for the interlayer insulating film 23 in the step shown in FIG.

-Second etching of liner film-
Next, dry etching is performed on the second liner film 22b until the film thickness of the second liner film 22b reaches, for example, 20 nm (in the case where the gate structure Ga is a densely arranged region, (Dry etching is performed on the first liner film 20a until the thickness of the first liner film 20a reaches, for example, 20 nm). Here, specific examples of the dry etching conditions for the second liner film 22b include the same conditions as the dry etching conditions for the second liner film 22b in the step shown in FIG. 5B.

  In this way, as shown in FIG. 6 (c), the second liner film 22b and the interlayer insulating film 23 are opened in the region between the adjacent gate structures Gb, and the second portion is formed at the bottom. The second contact hole 34rx in which the second liner film 22b having a thickness of 20 nm (specifically, for example, 20 nm) remains is formed. Here, the planar shape of the second contact hole 34rx is a rectangular shape in which the width in the gate width direction is longer than the width in the gate length direction.

-Removal of organic film-
Next, as shown in FIG. 7A, the multilayer resist pattern and the organic film 29x are removed by ashing / cleaning treatment.

  In this way, as shown in FIG. 7A, the first and second contact holes 28rx and 34rx having the same thickness of the second liner film 22b remaining at the bottom are formed.

-Third etching of liner film-
Next, as shown in FIG. 7B, the second liner film 22b remaining at the bottom of the first contact hole 28rx and the second residue remaining at the bottom of the second contact hole 34rx by dry etching. The liner film 22b is removed, and first and second contact holes 28x and 34x exposing the silicide layer 19b1 are formed at the bottom (here, a gate structure Gb as shown in FIG. 7A is disposed). In the case where the gate structure Ga is disposed (that is, the NMOS region) instead of the region (that is, the PMOS region), the first liner film and the second contact hole remaining at the bottom of the first contact hole. The first liner film remaining at the bottom is removed, and first and second contact holes are formed in the bottom to expose the silicide layer 19a1). Here, as a specific example of the dry etching condition of the second liner film 22b, for example, the same condition as the dry etching condition of the second liner film 22b in the step shown in FIG. Is mentioned.

  In this way, as shown in FIG. 7B, the first and second contact holes 28x and 34x having a rectangular shape whose planar shape is longer in the gate width direction than in the gate length direction are formed. Form.

  Thereafter, although not shown, first and second contacts are formed in the first and second contact holes 28x and 34x through a barrier metal film with a conductive film embedded therein.

  As described above, the semiconductor device according to this embodiment can be manufactured.

  Here, FIG. 8 is a diagram showing a CD-shift relationship between a normal square contact and a rectangular contact whose one side is longer than the other side. As shown in FIG. 8, in the case of a rectangular contact, the CD-shift amount is larger than that of a square contact.

  Therefore, in the case of a rectangular contact, adjacent contact holes are formed by a normal method, that is, formed by one lithography and one etching (for example, as shown in FIG. 9A, (When the contact holes 36l and 36r are formed using the resist pattern in which the hole forming hole patterns 35l and 35r are formed as a mask), the contact hole forming hole patterns 35l and 35r are spaced apart from each other by one resist pattern. Therefore, the distance L between the contact holes 36l and 36r becomes relatively wide (see FIG. 9B, FIG. 9B shows the SEM photograph after lithography on the left side, and after etching on the right side. SEM photograph is shown).

  On the other hand, when adjacent contact holes are formed by the contact hole forming method in this embodiment, that is, formed by two lithography and two etchings (for example, as shown in FIG. The first contact hole 38 is formed using the first resist pattern in which the formation hole pattern 37 is formed as a mask, then the first resist pattern is removed, and then the contact hole formation hole pattern 39 is formed. When the second contact hole 40 is formed using the second resist pattern as a mask), the arrangement position of the contact hole formation hole pattern 39 is arranged so as to overlap the arrangement position of the contact hole formation hole pattern 37. The first and second contact holes Distance L between 8, 40 are relatively narrow.

  As described above, the distance L between the first and second contact holes 38 and 40 formed by the contact hole forming method in the present embodiment is used as the distance L between the contact holes 36l and 36r formed by the usual method. It can be made narrower than

  According to the present embodiment, by forming the first contact hole 28rx and the second contact hole 34rx independently, the distance between the adjacent first and second contact holes 28rx and 34rx is reduced. By increasing the density of contact holes, the density of contacts having a rectangular planar shape can be increased. That is, since the distance between the first and second contact holes 28rx and 34rx can be reduced, the gate structure (transistor) is further miniaturized, and the distance between adjacent gate structures is reduced. The contact hole can be formed without inconvenience even if it is changed.

  Further, as shown in FIG. 7 (b), the planar shape of the first and second contact holes 28x, 34x is made rectangular so that the first and second contact holes 28x, 34x First and second contacts having a rectangular shape can be formed. Therefore, even if the gate structure is further miniaturized, a sufficient contact area between the contact and the active region can be ensured, so that an increase in contact resistance can be suppressed.

(Third embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 11 (a) to (b), FIGS. 12 (a) to (b), and FIGS. 13 (a) to (c). Will be described with reference to FIG. FIG. 11A to FIG. 13C are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps. In FIG. 11 (a) to FIG. 13 (c), the same reference numerals as those shown in FIG. 1 (a) to FIG. 2 (c) are given to the same constituent elements as those in the first embodiment. Attached. Therefore, in this embodiment, the description common to the first embodiment is omitted as appropriate.

  First, steps similar to those shown in FIGS. 1A to 2C in the first embodiment are sequentially performed.

  Subsequently, the combined contact hole is formed by using the combined contact hole forming method in the present embodiment. Here, the cross-sectional views shown in FIGS. 11 (a) to 13 (c) in the present embodiment are different from the cross-sectional views shown in FIGS. 1 (a) to 2 (c) in the first embodiment. The PMOS region of FIG. 2 is shown as a representative. 11A to 13C, an area (specifically, for example, an SRAM area) in which two gate structures Gb are densely arranged is shown.

-Formation of multilayer resist pattern-
First, as shown in FIG. 11A, a multilayer resist 27 is formed by sequentially laminating a lower layer resist 24, an intermediate layer resist 25, and an upper layer resist 26 on the interlayer insulating film 23. Thereafter, using a mask (not shown), holes 26hy are formed in the upper resist 26 to form an upper resist pattern. At this time, since a mask having a square shape of the drawn pattern is used, the hole 26hy has a square shape (or a circular shape) with rounded corners as shown in FIG. ). At this time, the hole 26hy is formed in the first partial region in the region extending from the gate electrode 13b constituting the gate structure Gb to the source / drain region 18b.

  Next, as shown in FIG. 11B, dry etching is sequentially performed on the intermediate layer resist 25 and the lower layer resist 24 using the upper layer resist pattern as a mask, and contact holes forming holes 27hy are formed in the multilayer resist 27. Then, a multilayer resist pattern is formed. Here, specific examples of the dry etching conditions for the intermediate layer resist 25 and the lower layer resist 24 are the same as the dry etching conditions for the intermediate layer resist 25 and the lower layer resist 24 in the step shown in FIG. 3B of the first embodiment. These conditions are listed.

-First etching of interlayer insulating film-
Next, dry etching is performed on the interlayer insulating film 23 using the multilayer resist pattern as a mask until the second liner film 22b is exposed (not shown here, as shown in FIG. 11B). In the case where the gate structure Ga is not a region where the gate structures Gb are densely arranged but a region where the gate structures Ga are densely arranged, the first liner film 20a is exposed to the insulating film 21a and the interlayer insulating film 23. Until dry etching). Here, specific examples of the dry etching conditions for the interlayer insulating film 23 include the same conditions as the dry etching conditions for the interlayer insulating film 23 in the step shown in FIG. 3B of the first embodiment.

-First etching of liner film-
Next, dry etching is performed on the second liner film 22b until the film thickness of the second liner film 22b reaches, for example, 20 nm (in the case where the gate structure Ga is a densely arranged region, (Dry etching is performed on the first liner film 20a until the thickness of the first liner film 20a reaches, for example, 20 nm). Here, as a specific example of the dry etching conditions for the second liner film 22b, for example, conditions similar to the dry etching conditions for the second liner film 22b in the step shown in FIG. 3B of the first embodiment are used. Is mentioned.

  In this manner, as shown in FIG. 11B, regions extending from the gate electrode 13b constituting the gate structure Gb to the source / drain regions 18b are formed on the second liner film 22b and the interlayer insulating film 23. A first contact hole 28ry in which a second liner film 22b having a first film thickness (specifically, for example, 20 nm) remains on the bottom is formed by opening a first partial region of the first partial region. Here, the planar shape of the first contact hole 28ry is a square shape (or a circular shape) with rounded corners.

-Formation of organic film-
Next, as shown in FIG. 12A, the multilayer resist pattern is removed by ashing / cleaning treatment. Thereafter, an organic film is formed on the interlayer insulating film 23 so as to fill the first contact hole 28ry. Thereafter, a portion of the organic film formed outside the first contact hole 28ry is removed by overall etch back to form an organic film 29y embedded in the first contact hole 28ry. At this time, for example, endpoint detection based on light emission intensity is performed so that the upper surface of the organic film 29y embedded in the first contact hole 28ry is not located below the upper end of the first contact hole 28ry. Thus, it is preferable to detect the processing time of the entire surface etch back. Here, as a specific example of the whole-surface etch-back condition of the organic film, for example, the same condition as the whole-surface etch-back condition of the organic film in the step shown in FIG.

-Formation of multilayer resist pattern-
Next, as shown in FIG. 12B, a multilayer resist 33 in which a lower layer resist 30, an intermediate layer resist 31, and an upper layer resist 32 are sequentially stacked is formed on the interlayer insulating film 23 and the organic film 29y. . Thereafter, using a mask (not shown), holes 32hy are formed in the upper resist 32 to form an upper resist pattern. At this time, since a mask having a square shape of the drawn pattern is used, the hole 32hy has a square shape (or a circular shape) with rounded corners as shown in FIG. ). At this time, the hole 32hy is formed in the second partial region of the region extending from the gate electrode 13b constituting the gate structure Gb to the source / drain region 18b. At this time, as shown in FIG. 12 (b), the hole 32hy has a region where the hole 32hy is formed adjacent to the region where the first contact hole 28ry is formed along the gate length direction, and the hole 32hy. A part of the formation region is formed so as to overlap with a part of the formation region of the first contact hole 28ry.

  Next, as shown in FIG. 13A, dry etching is sequentially performed on the intermediate layer resist 31 and the lower layer resist 30 using the upper layer resist pattern as a mask, and contact holes forming holes 33hy are formed in the multilayer resist 33. Then, a multilayer resist pattern is formed. Here, specific examples of the dry etching conditions for the intermediate layer resist 31 and the lower layer resist 30 include the same conditions as the dry etching conditions for the intermediate layer resist 25 and the lower layer resist 24 in the step shown in FIG.

-Second etching of interlayer insulating film-
Next, using the multilayer resist pattern as a mask, dry etching is performed on the interlayer insulating film 23 until the second liner film 22b is exposed (here, in the case where the gate structure Ga is densely arranged, Dry etching is performed on the insulating film 21a and the interlayer insulating film 23 until the first liner film 20a is exposed). Here, specific examples of the dry etching conditions for the interlayer insulating film 23 include the same conditions as the dry etching conditions for the interlayer insulating film 23 in the step shown in FIG.

-Second etching of liner film-
Next, dry etching is performed on the second liner film 22b until the film thickness of the second liner film 22b reaches, for example, 20 nm (in the case where the gate structure Ga is a densely arranged region, (Dry etching is performed on the first liner film 20a until the thickness of the first liner film 20a reaches, for example, 20 nm). Here, specific examples of the dry etching conditions for the second liner film 22b include the same conditions as the dry etching conditions for the second liner film 22b in the step shown in FIG.

  In this manner, as shown in FIG. 13A, the second liner film 22b and the interlayer insulating film 23 are regions extending from the gate electrode 13b constituting the gate structure Gb to the source / drain regions 18b. A second contact hole 34ry in which a second liner film 22b having a second film thickness (specifically, for example, 20 nm) remains is formed at the bottom by opening the second partial region. Here, the planar shape of the second contact hole 34ry is a square shape (or a circular shape) with rounded corners. Also, here, the second contact hole 34ry is adjacent to the first contact hole 28ry along the gate length direction, and a part of the second contact hole overlaps a part of the first contact hole. Be placed.

-Removal of organic film-
Next, as shown in FIG. 13B, the multilayer resist pattern and the organic film 29y are removed by ashing / cleaning treatment.

  In this way, as shown in FIG. 13B, the first and second contact holes 28ry and 34ry having the same thickness of the second liner film 22b remaining at the bottom are formed.

-Third etching of liner film-
Next, as shown in FIG. 13C, by dry etching, the second liner film 22b remaining at the bottom of the first contact hole 28ry and the second liner film remaining at the bottom of the second contact hole 34ry. The liner film 22b is removed, the silicide layer 19b1 is exposed at the bottom, and a combined contact hole 34Y including the first contact hole 28y and the second contact hole 34y is formed. (Here, not the region where the gate structure Gb is arranged as shown in FIG. 13C (ie, the PMOS region), but the region where the gate structure Ga in the first embodiment is arranged (ie, the NMOS). Region), the first liner film remaining at the bottom of the first contact hole and the first liner film remaining at the bottom of the second contact hole are removed, and the silicide layer 19a1 is exposed at the bottom, A combined contact hole including a first contact hole and a second contact hole is formed). Here, the dry etching conditions for the second liner film 22b include the same conditions as the dry etching conditions for the second liner film 22b in the step shown in FIG. 4C of the first embodiment.

  Thereafter, although not shown, a combined contact (shared contact) is formed in the combined contact hole 34Y with a conductive film embedded through a barrier metal film.

  As described above, the semiconductor device according to this embodiment can be manufactured.

  Here, a method for forming two adjacent united contact holes using the united contact hole forming method in the present embodiment will be briefly described below.

  In the case of the present embodiment, as shown in FIG. 14 (a), opposing first and third contact holes 41l and 41r are formed using a first resist pattern (not shown) as a mask. Thereafter, using the second resist pattern (not shown) as a mask, second and fourth contact holes 42l and 42r are formed, and the first combined contact hole composed of the first and second contact holes 41l and 42l. A second combined contact hole 42R formed of 42L and the third and fourth contact holes 41r and 42r is formed. Thereafter, the first and second combined contacts 43l and 43r are embedded in the first and second combined contact holes 42L and 42R. Here, the first merged contact hole 42L and the second merged contact hole 42R are adjacent to each other with a space along the gate width direction and are shifted from each other along the gate length direction. The first contact hole 41l and the third contact hole 41r are arranged to face each other along the gate width direction. Although not shown, the first, second, third, and fourth contact holes 41l, 42l, 41r, and 42r are formed in a region from the gate electrode to the source / drain region. .

  In the conventional case, as shown in FIG. 14 (c), after forming adjacent rectangular contact holes 44l and 44r using a resist pattern (not shown) as a mask, Contacts 45l and 45r are embedded.

  Here, as described above, as shown in FIG. 8, in the case of a square contact, the CD-shift amount is smaller than that of a rectangular contact. Therefore, in the first resist pattern, the pattern for forming the first contact hole 41l (not shown) and the pattern for forming the third contact hole 41r (not shown) are arranged close to each other. The distance between the first contact hole 41l and the third contact hole 41r can be reduced, and the distance between the first combined contact 43l and the second combined contact 43r can be reduced.

  According to the present embodiment, the planar shape forms the combined contact hole 34Y composed of the first and second contact holes 28y, 34y having a square shape (or a circular shape) with rounded corners, and the planar shape is By forming a combined contact hole composed of third and fourth contact holes having a square shape (or circular shape) with rounded corners, adjacent combined contacts spaced apart from each other along the gate width direction The interval between the holes can be reduced, the density of the combined contact holes can be increased, and the density of the combined contacts can be increased.

  Here, the first contact hole 28ry and the second contact hole 34ry are formed so as to partially overlap each other so that the first contact hole 28ry and the second contact hole 34ry are not formed apart from each other. It is preferable. Further, as shown in FIG. 14 (a), the third contact hole 41r and the fourth contact hole 42r are formed so as to partially overlap each other so that the third contact hole 41r and the fourth contact hole 42r are not formed apart from each other. The contact holes 41r and 42r are preferably formed.

  Further, as shown in FIG. 14 (b), the distance between the first and third contact holes 41lx and 41rx facing each other is set to the distance between the first and third contact holes 41l and 41r facing each other (FIG. a) to prevent the short circuit between the first combined contact 43lx and the second combined contact 43rx (that is, the short circuit between the first combined contact 43lx and the second combined contact 43rx). The margin area) can be made larger than the short margin between the first combined contact 43l and the second combined contact 43r.

  In the present embodiment, the shared contact arranged in the SRAM region is described as a specific example as the rectangular united contact, but the present invention is not limited to this.

  The present invention relates to an active region when a contact hole is formed in a semiconductor device in which the thickness of a liner film in a first region (eg, a dense region) and the thickness of a liner film in a second region (eg, a sparse region) are different from each other. Further, since it is possible to prevent scraping from being formed in the element isolation region, it is useful for a method for manufacturing a contact in a semiconductor device having a liner film.

(a)-(d) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (a)-(d) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (a)-(b) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (a)-(b) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. It is a figure which shows the relationship of CD-shift of a square type contact and a rectangular type contact. (a) is a plan view simply showing a conventional method for forming a contact hole. (b) shows the SEM photograph after lithography on the left side, and the SEM photograph after etching on the right side. It is a top view which shows simply the formation method of the contact hole in the 2nd Embodiment of this invention. (a)-(b) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. (a)-(b) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. (a)-(b) is a top view which shows simply the formation method of the united contact in the 3rd Embodiment of this invention, (c) is a top view which shows the formation method of the conventional contact simply is there. (a)-(d) is principal part process sectional drawing which shows the manufacturing method of the conventional semiconductor device to process order. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. (a)-(c) is sectional drawing which shows the problem of the manufacturing method of the conventional semiconductor device.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Element isolation region 12a, 12b Gate insulating film 13a, 13b Gate electrode 14a, 14b Offset spacer 15a, 15b Extension region 16a, 16b Inner side wall 17a, 17b Outer side wall 17A, 17B Side wall 18a, 18b Drain region 19a1, 19b1, 19a2, 19b2 Silicide layer 20, 20a First liner film 21, 21a Insulating film 22, 22b Second liner film 23 Interlayer insulating film 24 Lower layer resist 25 Middle layer resist 26 Upper layer resist 26h, 26hx, 26hy hole 27 multilayer resist 27h, 27hx, 27hy contact hole forming hole 28r, 28, 28rx, 28x, 28ry, 28y first contact hole 29 29x, 29y Organic film 30 Lower layer resist 31 Intermediate layer resist 32 Upper layer resist 32h, 32hx, 32hy hole 33 Multilayer resist 33h, 33hx, 33hy Contact hole forming hole 34r, 34, 34rx, 34x, 34ry, 34y Second contact hole 35l, 35r Contact hole forming hole pattern 36l, 36r Contact hole 37 Contact hole forming hole pattern 38 First contact hole 39 Contact hole forming hole pattern 40 Second contact hole 41l, 41lx First contact hole 41r, 41rx third contact hole 42l second contact hole 42r fourth contact hole 42L, 42Lx first combined contact hole 42R, 42 x second merged contact hole 43l, 43lx first polymer contacts 43r, 43rx second merged contact 44l, 44r contact hole 45l, 45r Contacts

Claims (6)

A step (a) of forming a plurality of gate structures on a semiconductor substrate;
(B) sequentially forming a liner film and an interlayer insulating film on the semiconductor substrate so as to cover the plurality of gate structures;
A region between the gate structures adjacent to each other is opened in the liner film and the interlayer insulating film in the first region where the gate structures are densely arranged, and has a first film thickness at the bottom. A step (c) of forming a first contact hole in which the liner film remains;
A region between the gate structures adjacent to each other is opened in the liner film and the interlayer insulating film in the second region where the gate structures are sparsely arranged, and a second film thickness is provided at the bottom. A step (d) of forming a second contact hole in which the liner film remains;
After the step (c) and the step (d), the step of removing the liner film remaining on the bottom of the first contact hole and the liner film remaining on the bottom of the second contact hole ( e)
The method for manufacturing a semiconductor device, wherein the first film thickness and the second film thickness are equal. Forming a first gate structure, a second gate structure, and a third gate structure on a semiconductor substrate;
(B) sequentially forming a liner film and an interlayer insulating film on the semiconductor substrate so as to cover the first gate structure, the second gate structure, and the third gate structure; ,
The liner film having a first film thickness at the bottom by opening a region between the first gate structure and the second gate structure adjacent to each other in the liner film and the interlayer insulating film Forming a first contact hole in which is left;
The liner film having the second film thickness at the bottom by opening a region between the second gate structure and the third gate structure adjacent to each other in the liner film and the interlayer insulating film. Forming a second contact hole in which is left;
After the step (c) and the step (d), the step of removing the liner film remaining on the bottom of the first contact hole and the liner film remaining on the bottom of the second contact hole ( e)
The planar shape of the first contact hole and the second contact hole is a rectangular shape whose length in the gate width direction is longer than the length in the gate length direction,
The method for manufacturing a semiconductor device, wherein the first film thickness and the second film thickness are equal. A step (a) of forming a gate structure on a semiconductor substrate;
(B) sequentially forming a liner film and an interlayer insulating film on the semiconductor substrate so as to cover the gate structure;
In the liner film and the interlayer insulating film, a first partial region of the region extending from the gate electrode constituting the gate structure to the source / drain region is opened, and the first film thickness is formed at the bottom. A step (c) of forming a first contact hole in which the liner film is left,
A second partial region of the region extending from the gate electrode constituting the gate structure to the source / drain region is opened in the liner film and the interlayer insulating film, and the second film thickness is formed at the bottom. A step (d) of forming a second contact hole in which the liner film having:
After the step (c) and the step (d), the liner film remaining at the bottom of the first contact hole and the liner film remaining at the bottom of the second contact hole are removed, Forming a first combined contact hole comprising the first contact hole and the second contact hole (e),
The first contact hole and the second contact hole are adjacent to each other along the gate length direction, and a part of the first contact hole and a part of the second contact hole overlap each other. And
The planar shape of the first contact hole and the second contact hole is a circular shape or a square shape with rounded corners,
The method for manufacturing a semiconductor device, wherein the first film thickness and the second film thickness are equal. In the manufacturing method of the semiconductor device according to claim 3,
In the step (c), a third partial region of the region from the gate electrode constituting the gate structure to the source / drain region is opened in the liner film and the interlayer insulating film, Forming a third contact hole in which the liner film having the third film thickness remains on the bottom,
In the step (d), a fourth partial region of the region extending from the gate electrode constituting the gate structure to the source / drain region is opened in the liner film and the interlayer insulating film, Forming a fourth contact hole in which the liner film having the fourth film thickness remains on the bottom,
In the step (e), the liner film remaining at the bottom of the third contact hole and the liner film remaining at the bottom of the fourth contact hole are removed, and the third contact hole and the Forming a second combined contact hole comprising a fourth contact hole;
The first combined contact hole and the second combined contact hole are adjacent to each other with a space along the gate width direction, and are shifted from each other along the gate length direction,
The first contact hole and the third contact hole are disposed to face each other along the gate width direction,
The third contact hole and the fourth contact hole are adjacent to each other along the gate length direction, and a part of the third contact hole and a part of the fourth contact hole overlap each other. And
The planar shape of the third contact hole and the fourth contact hole is a circular shape or a square shape with rounded corners,
The method of manufacturing a semiconductor device, wherein the third film thickness and the fourth film thickness are equal to the first film thickness and the second film thickness. In the manufacturing method of the semiconductor device of any one of Claims 1-3,
The step (d) is performed after the step (c) and before the step (e),
A semiconductor device further comprising a step (f) of burying an organic film in the first contact hole after the step (c) and before the step (d). Manufacturing method. In the manufacturing method of the semiconductor device of any one of Claims 1-3,
The step (c) is performed after the step (d) and before the step (e),
A semiconductor device further comprising a step (g) of burying an organic film in the second contact hole after the step (d) and before the step (c). Manufacturing method.