JPS63137450A - Laminated type cmos gate array - Google Patents

Abstract

PURPOSE:To improve the integration density of a device and to prevent a latch-up phenomenon, by completely isolating MISFETs having different kinds of channels with an insulating film, and providing three-dimensional arrangement. CONSTITUTION:A lower p-channel MOSFET layer pTr1 is formed on an n<->Si substrate. An n-channel MOSFET nTr1 is formed as specified on an SOI base substrate 11, which is selectively laminated and arranged on the pTr1 through an interlayer insulating film 10. A gate electrode 6 of the pTr1 and a gate electrode 14 of the nTr1 are mutually connected 20 through a window 19. A p<+> type SOI-base-substrate connecting region 12 is isolated from an n<+> source 15 and a drain 16 and located at right angles to the extending direction of the gate at the base substrate 11 in contact with the other end of the gate electrode 14. The region 12 also serves the role of a channel stopper. In this constitution, the MISFETs having the different channels are completely isolated by means of the existing insulating film. The latch-up phenomenon of an LSI using a CMOS gate array is removed, and integration can be implemented.

Description

[Detailed Description of the Invention] [Summary] A lower layer of an opposite conductivity type MI formed on a semiconductor substrate of one conductivity type.
The gate electrodes of the S transistor and the upper layer one conductivity type MrS transistor formed on the opposite conductivity type recrystallized semiconductor substrate selectively laminated on the opposite conductivity type MIS transistor through an insulating film are connected in common. Laminated layer 3 composed of
A stacked CMOS gate array that has complementary basic cells with a dimensional structure and interconnects the upper and lower transistors using a common wiring channel placed on top of the upper transistor. , channel M
By completely separating the IS transistors through an insulating film and stacking them in a three-dimensional arrangement, the degree of integration can be greatly improved and the latch amplifier phenomenon can be completely prevented.

[Industrial application field]

The present invention relates to a stacked CMOS gate array in which MIS transistors of different conductivity types are stacked with an insulating film interposed therebetween.

Nowadays, as large-scale integrated circuits become larger, there is a remarkable trend toward high-mix, low-volume production.In order to reduce manufacturing costs and shorten manufacturing time, large-scale integrated circuit manufacturing using the master slice method has become popular. There is.

The master slicing method is a method in which a semiconductor substrate (gate array) is prepared in advance, consisting of a large array of basic element sets, that is, basic circuit sets usually consisting of transistors, resistors, etc. Since only the mask is manufactured and the circuit wiring is performed to complete the large-scale integrated circuit,
Manufacturing time is significantly shortened. Furthermore, since the basic element set can be used in common for various large-scale integrated circuits, manufacturing costs are also reduced.

In gate arrays used in the above-mentioned master slice type large-scale integrated circuits, complementary type gate arrays, that is, CMO8 gate arrays, are often used because the circuit configuration is easy and high integration can be achieved. However, in order to prevent the well-known launch-up phenomenon, the current high-density arrangement is the limit, and in order to meet the demand for even larger scale, a cell structure that can prevent the rough-up phenomenon and achieve even higher integration is required. ing.

[Conventional technology]

FIG. 8 is an equivalent circuit diagram 18) and a schematic plan view tb of a basic cell of a conventional CMOS gate array.

In the figure, 51 is an n-type silicon (St) substrate, 52 is a p-
53 is an n-type substrate contact region, 54 is a p-type well contact region, 55 and 56 are gate electrodes, 5
7 is a p+ type drain region, 58 is a p'' source region, 5
9 is a p-type drain region 60 is an n-type drain region 61 is an n-type source region, 62 is an n''-type drain region, LN, □, L Nff, etc. are n-channel wiring channels, L PI% L pt , L P3, etc. are p-channel side wiring channels, pTrls pTrz are p-channel M
IS transistors, nTr, , nTr2 are n-channel M
An IS transistor is shown.

As shown in the figure, in the basic cell of a conventional CMOS gate array, a p-channel Mis transistor pT
ripTr2 and n-channel MIS transistor nTrl
snTr2 are arranged side by side in a plane on the same substrate.

As a result, the planar area occupied by the cell increases and the degree of integration decreases, and in addition, parasitic silage occurs between the p-channel MIS transistor and the n-channel MIS transistor through the substrate and the well, which is caused by conduction in the known latch. In order to prevent performance deterioration due to the up phenomenon, an n-type substrate contact region 53 is provided around the outer periphery of the p-channel MIS transistor pTr, and a p-type well contact region 54 is provided around the outer periphery of the n-channel MIS transistors nTr r and nTr 2. Even by providing each, there is a problem that the degree of integration is further reduced.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention is that in the conventional CMOS gate array using the above-mentioned basic cellular, the p-channel MIS transistor and the n-channel MIS transistor are arranged two-dimensionally side by side, so that the area occupied by the unit cell is reduced. Moreover, by providing substrate contact regions H, I and well contact regions surrounding the transistors to prevent latch-up, the occupied plane area further increases, which impedes high integration.

[Means for solving problems]

The above problem is that an opposite conductivity type channel MIS transistor comprising a first gate electrode, a source region of an opposite conductivity type, and a drain region of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type; A recrystallized semiconductor substrate of an opposite conductivity type selectively laminated on the MIS transistor via an insulating film has one end connected to the first gate electrode and extends along the first gate electrode. Second to do
A one-conductivity type channel MIS transistor having a gate electrode, a one-conductivity type source region and a one-conductivity type drain region is formed, and a lower region of the other end of the second gate electrode is formed in the recrystallized semiconductor substrate. an opposite conductivity type base contact ef with a higher impurity concentration than the recrystallized semiconductor base, which is in contact with and separated from the one conductivity type source region and the one conductivity type drain region;
It has a complementary basic cell with a laminated structure in which a t region is selectively provided, and the channel MIS transistor of opposite conductivity type in the lower layer and the channel MIS transistor of one conductivity type in the upper layer are connected to the channel MIS transistor of one conductivity type in the upper layer. This problem is solved by a stacked CMOS gate array according to the present invention, which is interconnected using a common wiring channel provided above the transistors through an insulating film.

[For production]

That is, in the basic cell of the stacked CMOS gate array according to the present invention, for example, a p-channel MIS transistor is disposed on a semiconductor substrate, and an n-channel MIS transistor is stacked on the p-channel MIS transistor with an insulating film interposed therebetween. The formed recrystallized semiconductor substrate, namely 5OI (S
ilicon (on inverter) is arranged on the substrate, and the lower layer p-channel MIS transistor and the upper layer n-channel
A p-channel MIS transistor constitutes a complementary type by forming a complementary basic cell of a stacked structure with a channel MIS transistor, and interconnecting the wing type channel transistors using wiring channels on the stacked body. In addition to significantly reducing the plane area occupied by the and n-channel MIS transistor on the substrate, for example, the p-channel MIS transistor on the semiconductor substrate and the n-channel MIS transistor on the SOI substrate are completely separated by an intervening insulating film. This completely eliminates the latch amplifier phenomenon, thereby eliminating the need for a substrate contact region and further reducing the cell area accordingly.

In this way, the rough drop phenomenon in large-scale integrated circuits using CMOS gate arrays can be completely eliminated, and high integration can be achieved.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a plan view (al, A
-A sectional view (b) and B-B arrow sectional view (C), Figure 2 is an equivalent circuit diagram of the first embodiment, and Figure 3 is a summary of a modification of the first embodiment. FIG. 4 is a plan view schematically showing the second embodiment (al and A-A sectional view (b); FIG. bl, B-
5 is an equivalent circuit diagram of the second embodiment, and FIG. 6 is a circuit diagram of a two-manpower NAND gate (al) and a wiring connection diagram (1+1, FIG. 7 is a circuit diagram of a two-man power NOR gate and a wiring connection diagram of a basic cell according to the present invention.

Identical objects are indicated by the same reference numerals throughout the figures.

In FIG. 1, 1 is an n-type Si substrate, 2 is a field oxide film separating elements, 3 is an n-type channel stopper,
4a and 4b are first and second element forming regions separated by a field oxide film and a channel stopper; 5 is a first (
6 is a first gate oxide film made of polySt, etc.
(lower layer) gate electrode, 7 is a p type source region, 8 is a p
゛The electric type drain region 9 is the first impurity block oxide film, 10 is the fJJl interlayer insulating film, and 11 is the p-type recrystallization film 5.
t(SOI) substrate, 12 is a p-type SO1 substrate contact region, 13 is a second gate oxide film, 14 is a second (upper layer) gate electrode made of poly-Si, etc., 15 is an n-type source N region, 16 is the n-type drain region 17 is the second impurity blocking oxide film, 18 is the second interlayer insulating film, 19 is the contact window, 20 is the common connection part of the gate electrode, pTr
,, pTr2 indicates a p-channel MOS transistor in the lower layer, and nTr , , nTr2 indicates an n-channel MoS transistor in the upper layer.

A basic cell of a stacked CMOS gate array having the simplest structure according to the present invention has, for example, a lower p-channel MOS transistor pTrl having the structure shown in the figure formed on an n-type Si substrate l, and the transistor pTr
, an upper layer n-channel MO5 transistor nTr having the illustrated configuration is formed on a p-type SOI substrate 11 selectively laminated thereon via a first interlayer insulating film 10,
The gate electrode 6 of the lower layer p-channel MOS transistor pTr, and the upper layer n-channel MOS transistor nTr,
For example, a contact window 19 is connected to the gate electrode 14 at one end.
(20 is a connecting portion), and the lower layer p-channel MOS transistor pTr and the upper layer n-channel MOS transistor nTr+ constitute a complementary type.

Then, in contact with the lower region of the end of the upper layer gate electrode 14 on the side different from the connection end, it traverses the p-type SOI substrate 11 in a direction intersecting the gate extension direction, and forms an n-type source region 15 and an n-type source region 15 and n° p type S separated from type drain region 16
An ol substrate contact region 12 is provided which also serves as a channel stopper. In order to increase the degree of integration, the p-type SO1 substrate is formed to extend over, for example, an adjacent lower layer p-channel MOS transistor pTr2, and the p-type SOI
Base contact region 12 is also formed in common with adjacent n-channel MOS transistor nTr2, for example, as shown in the figure.

In this embodiment, the upper layer gate electrode 14 and the lower layer gate electrode 6 are directly connected through the contact window 19, but the connection between these gate electrodes may be made through wiring in the master slicing process. good.

In the figure, 119a, 119b, 119c, 119d, 1
19e, 119f, etc. illustrate wiring contact windows formed during master slicing. The master slice wiring using the wiring contact window is the upper region of the stacked cell, that is, the n-channel MOS transistor nTr,
This is done using the upper wiring channel.

The basic cell shown in the first embodiment has a circuit configuration as shown in the equivalent circuit diagram shown in FIG.

FIG. 3 shows a modified example of the basic cell having the configuration shown in the first embodiment. In this example, the width in the direction perpendicular to the extension axis of the gate electrode 6 of the lower transistor pTr A p-type SO1 substrate 11 having a width equal to that is disposed directly above the lower transistor pTr, thus enabling connection between the source and drain regions 7.8 of the lower transistor pTr and wiring. As shown in the figure, one more layer of the lower insulating film 21 is formed, and a source lead electrode 22 and a drain lead electrode 23 of the lower layer transistor pTr made of polyst or the like as shown in the figure are provided thereon. This extraction electrode may be formed together with the lower gate electrode.

In the figure, 24a, 24b, 25a, and 25b are contact windows, 26 is an oxide film for impurity blocking, and other symbols indicate the same objects as in FIG. 1.

FIG. 4 shows that the transistor formed on the semiconductor substrate is composed of two p-channel MOS transistors that share either the source or the drain, and the transistor formed on the SOI substrate above the p-channel MOS transistor has the source and drain regions shared. This is an example of a stacked CMO3 basic cell having a four-transistor configuration consisting of two independent n-channel MO3 transistors.

In the figure, 6a, 6b are first and second lower gate electrodes, 7a, 7b, and 7c are first, second, and third p+ type source or drain (S/D) regions, 14a, 14
b are first and second upper layer gate electrodes, 15a, 15b
, 15c and 15d are first, second, third and fourth n9 type source or drain (S/D) regions, 19a
, 19b is a cositact window, 20a and 20b are connection parts of upper and lower gate electrodes, pTr, and pTr, □ is S
The lower layer p-channel MO3 transistors, nTr+ and nTr, which share one of the /D regions are the upper layer n-channel MO3 transistors, pTrz, whose S/D regions are independent.
+ and pTrzz are lower p layers adjacent to each other in the gate extending direction.
Channel MO3 transistors, nTrz+ and nTrz
□ is an upper layer n-channel MO3 adjacent to the gate extending direction
Transistors and other symbols indicate the same objects as in FIG.

In this configuration, the upper layer gate electrodes 14a, 14b
p
- type Sol substrate 11 in a direction crossing the gate extension direction, and n-type S/D regions 15a, 15b, 15
A p-type So1 substrate contact region 12 separated from c and 15d is provided to also serve as a channel stopper.

In order to increase the degree of integration, the p-type 501 substrate 11 has, for example, a p-channel MO in the lower layer adjacent to the gate in the extending direction.
A p" type S is formed selectively extending over the three transistors pTrz+ and pTlz, and also serves as a channel stopper.
The o1 substrate contact region 12 is also connected to an adjacent n-channel MOS transistor nTrz+ % n, for example, as shown in the figure.
It is formed in common with the Trz□ side.

Also in this embodiment, the upper layer gate electrode 14a114b
and lower layer gate electrodes 6a and 6b are directly connected through contact windows 19a and 19b, respectively, but these gate electrodes may be connected through wiring in the master slicing process.

In the figure, 119a to 119h are examples of wiring contact windows formed during master slicing.

The basic cell having the configuration of the above embodiment includes two p-channel MO3 transistors pTr++ and pTr+z and two n-channel M
A circuit structure consisting of four transistors, OS transistors nTr and % nTr+2, in which p-channel transistors share one S/D region, and different channel transistors share a gate electrode. has.

FIG. 6 is a diagram showing a circuit diagram (a) of a two-manpower NAND gate and a wiring connection diagram (b) when constructed using the basic cell shown in the second embodiment, in which IN, , IN2 are shown. is the first
, the second input terminal, OUT the output terminal, VCC the high potential power supply, VSS the ground, the x mark the wiring contact window, and other symbols the same objects as in FIG. 3.

Figure 7 shows the circuit diagram (a) of the two-man powered NOR gate and the circuit diagram of the second
6 is a diagram showing a wiring connection diagram (b) when configured using the basic cell shown in the embodiment, and is indicated using the same reference numerals as in FIG. 6. FIG.

As can be seen from the above circuit formation example, if the stacked CMOS basic cell according to the present invention is used, the same circuit can be formed with approximately half the occupied area compared to the case of using a conventional two-dimensional, that is, planar, CMOS basic cell. It is clear that it can be done.

Furthermore, since the MOS transistors of different conductivity types are completely separated vertically by the insulating film, no latch-up phenomenon occurs.

〔Effect of the invention〕

As described above, by using the stacked CMOS gate array according to the present invention, it becomes possible to prevent the latch amplifier phenomenon and significantly increase the degree of integration of a master slice type large-scale integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a plan view (a) schematically showing a first embodiment of a stacked CMOS basic cell according to the present invention, a cross-sectional view taken along the line A-A (bl), and a cross-sectional view taken along the line B-B (C1, FIG. 2 is an equivalent circuit diagram of the first embodiment, and FIG. 3 is a plan view schematically showing the main parts of a modification of the first embodiment. Figure 4 is the second
A plan view (al) schematically showing an embodiment of the present invention (A-A cross-sectional view (b), a B-B arrow cross-sectional view (C), FIG. 5 is an equivalent circuit diagram of the second embodiment, Figure 6 is a circuit diagram of a two-person NAND gate (al and 8th
The figures are an equivalent circuit diagram (a) and a schematic plan view (b) of a basic cell of a conventional CMOS gate array. In the figure, 1 is an n-type Si substrate, 2 is a field oxide film, 3 is an n-type channel stopper, 4a and 4b are element formation regions, 5 is a first (lower layer) gate oxide film, and 6 is a first (lower layer) gate oxide film. ), 7 is a p1 type source region, 8 is a p1 type drain region, 9 is a first impurity blocking oxide film, 10 is a first interlayer insulating film, 11 is a p-type recrystallized Si (SOI) Substrate, 12 is p+
13 is the second gate oxide film, 14 is the second (upper layer) gate electrode, 15 is the n-type source region, 16 is the n-type drain region, 17 is for the second impurity block oxide film, 18 is a second glabellar insulating film, 19 is a contact window, 20 is a common connection part of the gate electrode, 21 is a lower layer insulating film, 22 is a source extraction electrode, 23 is a drain extraction electrode, 24a, 24b, 25a, 25b is a contact window, 26 is an oxide film for impurity blocking, 119a to 119f are wiring contact windows formed by master slicing, pTr is a lower layer p-channel MOS transistor, nTr +, nTr2 are upper layer n-channel MOS transistors shows. ((1) Plane m (b) A-A Nu perspective city map (c) g-a3-o (z, new dn Figure 2 mantle, eaves a
Month 1 Nii Tatsuro Difference, 2 To.
Figure 2 ((2) Plan Cb) A-A arrow view lfT view Example of candy rotation and rib shape η Yabu (Ten 33 Zushukyo 2nd Yuhirusu Price Danro Zuko 5m (α) Circuit da (b) Layout thickness map 2 people pNAND
Data 1-Diagram 6 (a) Circuit diagram <b) Wiring thin map Diagram of 2 people 6 NO scale γ゛-to Figure 7 (θ,) Etc. −Side view

Claims (1)

[Claims] An opposite conductivity type channel MIS transistor comprising a first gate electrode, a source region of an opposite conductivity type, and a drain region of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and the opposite conductivity type A recrystallized semiconductor substrate of an opposite conductivity type selectively stacked on the channel MIS transistor via an insulating film has one end connected to the first gate electrode and extends along the first gate electrode. a one conductivity type channel MIS transistor comprising a second gate electrode, a one conductivity type source region and a one conductivity type drain region, the other end of the second gate electrode being formed on the recrystallized semiconductor substrate; A complementary basic structure having a laminated structure in which a substrate contact region of an opposite conductivity type with a higher impurity concentration than the recrystallized semiconductor substrate is selectively provided in contact with a lower region of the recrystallized semiconductor substrate and separated from a source region of one conductivity type and a drain region of one conductivity type. The channel MIS transistor of opposite conductivity type in the lower layer and the channel MIS transistor of one conductivity type in the upper layer have a common wiring channel provided above the channel MIS transistor of one conductivity type in the upper layer via an insulating film. A stacked CMOS gate array characterized in that the stacked CMOS gate array is interconnected using wires.