JPS5939061A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive high integration and high efficiency of the titled semiconductor device by a method wherein the channel direction of the upper MOS transistor is positioned in the direction where it is intersecting with the channel direction of the lower MOS transistor. CONSTITUTION:An N-channel MOS transistor (NMOSTr), consisting of a drain 5, a source 7 and a gate 4, is three-dimensionally constituted on a P-channel MOS transistor (PMOSTr) consisting of a drain 2, a source 3 and a gate 4 using said gate 4 as a common electrode. The above-mentioned transistors are superposed in such a manner that the current flowing between the PMOSTr and the sources 3 and 7, the drains 2 and 5 of the NMOSTr is applied vertically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to 0MO8 (Complement arY
Metal-■■1-■■■--1-□11■-1χ See, picL63emieonductor) Related to circuit configuration), particularly related to semiconductor devices having an optimal configuration layout for high integration, high performance, and mass production. .

[Prior art]

In recent years, with the aim of increasing the integration of CMOS devices, the first
A common gate vertical stack type CMOS inverter (Joint-gate, vertical
lystacked 0MO81nverter) was proposed (Q, T, Qoeloe et a
t,, 1981 IEDM l)igestoft
electrical paperS, 24°6,
l') I) 554-556). In the same figure, 1 is n
2.3 is a p-type impurity layer, 4 is a gate electrode, and 6 is a p-type polysilicon layer, which is crystallized by laser annealing technology. 5.7 is n-type impurity layer, 8.9
is a gate oxide film, and 10, 11, 12.13 are metal electrodes such as At. In this structure, p-channel MO8) with 2 and 3°4 as the drain, source, and gate, respectively.
transistor (hereinafter abbreviated as pMO8), an n-channel MO with 5 and 7.4 as the drain, source, and gate, respectively.
An S transistor (hereinafter abbreviated as 1MO8) is formed,
In particular, the feature is that the gate electrode 4 is used as a common electrode for 9MO8 and 1MO8, and the n MOS is three-dimensionally configured on 0MO8. That is, conventionally the above pMO8°1M
A CMOS inverter circuit was constructed by separately forming O8 on the surface of S1, but in the configuration shown in FIG. It was reduced to 2 to 1/3.

However, according to the above-mentioned conventional example, since 1MO8 consisting of 4°5.6.7 is formed on the 9MO8 gate 4 formed on the surface of the 3i substrate, the pMOS channel length is (Ll), the channel length (L2) of the upper nMOS has to be extremely short. In other words, the minimum channel dimension is 2 μm and the mask alignment margin is 1.5 μm.
In this case, L2 = 2 μn'l + L+ = 25
pm, causing a large imbalance in the dimensions of both MOS transistors, undesirably increasing the occupied area, and at the same time reducing the driving ability of the circuit body.

[Purpose of the invention]

An object of the present invention is to overcome the drawbacks of the conventional examples described above and provide a highly integrated and high-performance semiconductor device.

[Summary of the Invention J In the present invention, in order to form an upper MO8) transistor having a channel length of any size, regardless of the channel dimensions of the MOS transistor formed at the lower part, the direction of the channel is different from that of the lower MOS transistor. They are characterized by their crossing directions.

An embodiment of the present invention will be explained below with reference to FIG. Second
The figure shows a pattern layout diagram of a semiconductor device according to the present invention. The numbers in the figure correspond to the numbers of each layer in FIG.

However, in FIG. 2, 10 and 13 in FIG. 1 are connected by the same metal wiring to form an inverter circuit configuration. CA is A
t and a contact region between the diffusion layer, CB a contact region between At and the gate electrode, and CC a contact region with, for example, a polysilicon layer stacked on top. As is clear from the figure, in the present invention, the 9M formed at the bottom
Regardless of the channel length L1 of O8, the gate electrode 4 of the MO8 can be shared to form one MO8 having a channel length L2 on the upper part. This differs from the conventional structure in which the current flows between the sources and drains of the upper and lower MOS transistors in parallel, but in that it flows perpendicularly. On the other hand, in this structure, the channel region of the upper MOS transistor is the region 6 shown in FIG. 2, and the area is L2.
It becomes XW.

In this example, W is smaller than the effective width WE of the upper MOS transistor, but this is because the width Wg of the gate electrode 4 shared with the lower part deviates from WE due to mask alignment. . This problem can be solved by laying out the WE completely covering the WII or the Ws completely covering the WE.

As described above, according to the present invention, it is possible to obtain a highly integrated semiconductor device without deteriorating the performance of a MOS transistor.

FIG. 3 shows an example of application of the present invention, and shows a circuit diagram of a static memory cell composed of six MOS transistors composed of a CMOS inverter circuit. In the figure, 31.32 is a data line, 39 is a word line, and 33 is a data line.
~36 is 1MO8°37.38 is I) MOS. Here, the features of the present invention are most exhibited at points 33 to 36.
An nMO8l-transistor of 37.38 mm is formed on the surface of a Si semiconductor, and 9 MO8 transistors of 37.38 mm are laminated on top of the transistor so as to share the gate electrode of 34.35 mm. The reason for this is (1) Due to the structure and manufacturing process, it is impossible to make the gate oxide film of the MOS transistor stacked on the top as thin as the gate oxide film of the transistor stacked on the bottom. 34 or 35.36) is S
i Formation on the semiconductor surface is advantageous in terms of faster operation speed.

(2) The 9MO8 of 37.38 only needs to supply a current sufficient to hold the information stored at point B or 0 in FIG. 3, and does not require a large driving capacity.

Therefore, forming it by stacking it on the lower nMO8 is most effective in terms of increasing the degree of integration. In particular, by using the semiconductor device of the present invention, stacking can be performed without impairing the degree of integration. Also, as explained in Figure 2,
Even if the effective gate width of pMO8 formed on the upper part becomes smaller due to mask alignment misalignment, as described above, 1) MO8
It does not detract from its original role.

〔Effect of the invention〕

As described above, according to the present invention, there is little difference in the channel lengths of two vertically arranged transistors that share a gate, and therefore the 0M08 transistor has a small occupied area and a large drive capacity.
You can get the circuit.

DESCRIPTION OF SYMBOLS 1... N-type Si semiconductor substrate, 2, 3... P-type impurity layer, 4... Gate electrode, 6... P-type silicon layer, 5
．． 7...n-type impurity layer.

Circulation 1 Diagram yz diagram V, S blade cc Figure 3 1-280 Higashikoigakubo, Kokubunji City Hitachi, Ltd. Central Research Inside the office 0 shots by Masaaki Aoki 1-280 Higashikoigakubo, Kokubunji City Hitachi, Ltd. Central Research Inside the office

Claims (1)

[Claims] 1. Source and drain formed on one semiconductor surface,
A MOS transistor of a first conductivity type having a gate, a source drain stacked on the upper part of the transistor, and a MOS transistor of a second conductivity type having a gate, the first conductivity type MOS transistor and the second conductivity type MOS transistor. MO8)
In a semiconductor device in which gates of transistors are formed of the same material and shared by each other, the direction of current flowing between the source and drain of the first conductivity type MO transistor;
A semiconductor device characterized in that the directions of currents flowing between the sources and drains of the second conductivity type MOS transistors are directions that intersect with each other.