JPS5939061A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5939061A JPS5939061A JP57147641A JP14764182A JPS5939061A JP S5939061 A JPS5939061 A JP S5939061A JP 57147641 A JP57147641 A JP 57147641A JP 14764182 A JP14764182 A JP 14764182A JP S5939061 A JPS5939061 A JP S5939061A
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- gate
- transistor
- channel
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000463 material Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、0MO8(Compl ement arY
Metal−■■1−■■■−−1−□11■−1χ
見、picL63emieonductor )回路の
構成に係)、特に高集積化、高性能化、量産性に最適な
構成配置を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to 0MO8 (Complement arY
Metal-■■1-■■■--1-□11■-1χ See, picL63emieonductor) Related to circuit configuration), particularly related to semiconductor devices having an optimal configuration layout for high integration, high performance, and mass production. .
近年、CMOSデバイスの高集積化を目的として、第1
図に示す様な共通ゲート垂直スタック型CMOSインバ
ータ(Joint −gate 、 vertical
lystacked 0MO81nverter )が
提案されていた(Q、 T、 Qoeloe et a
t、、 1981 IEDM l)igestof t
echnical paperS 、 24゜6 、
l’)I) 554〜556)。同図において、1はn
形Si半導体基板、2.3はp形不純物層、4はゲート
電極、6はp形ポリシリコン層でレーザ・アニール技術
によシ結晶化している。5.7はn形不純物層、8.9
はゲート酸化膜、10,11,12.13はAtなどの
金属電極である。この構造では、2,3゜4をそれぞれ
、ドレイン、ソース、ゲートとするpチャネルMO8)
ランジスタ(以下pMO8と略す)、5,7.4をそれ
ぞれ、ドレイン、ソース、ゲートとするnチャネルMO
Sトランジスタ(以下、1MO8と略す)が形成され、
特に、4なるゲート電極を9MO8,1MO8の共通電
極とし、0MO8上にn M OSを立体的に構成した
所に特徴がある。すなわち、従来は上記pMO8゜1M
O8を同−S1表面上に分離して形成しCMOSインバ
ータ回路を構成していたが、該第1図の構成では、トラ
ンジスタの一方を上部に積み上げることで実質的に占有
面積を従来の1/2〜1/3に減少せしめた。In recent years, with the aim of increasing the integration of CMOS devices, the first
A common gate vertical stack type CMOS inverter (Joint-gate, vertical
lystacked 0MO81nverter) was proposed (Q, T, Qoeloe et a
t,, 1981 IEDM l)igestoft
electrical paperS, 24°6,
l') I) 554-556). In the same figure, 1 is n
2.3 is a p-type impurity layer, 4 is a gate electrode, and 6 is a p-type polysilicon layer, which is crystallized by laser annealing technology. 5.7 is n-type impurity layer, 8.9
is a gate oxide film, and 10, 11, 12.13 are metal electrodes such as At. In this structure, p-channel MO8) with 2 and 3°4 as the drain, source, and gate, respectively.
transistor (hereinafter abbreviated as pMO8), an n-channel MO with 5 and 7.4 as the drain, source, and gate, respectively.
An S transistor (hereinafter abbreviated as 1MO8) is formed,
In particular, the feature is that the gate electrode 4 is used as a common electrode for 9MO8 and 1MO8, and the n MOS is three-dimensionally configured on 0MO8. That is, conventionally the above pMO8°1M
A CMOS inverter circuit was constructed by separately forming O8 on the surface of S1, but in the configuration shown in FIG. It was reduced to 2 to 1/3.
しかしながら、上述した従来例によれば、3i基板表面
に形成した9MO8のケート4上に、4゜5.6.7か
ら成る1MO8を形成するため、マスク合わせ余裕等を
考慮すると、pMosのチャネル長(Ll)に比べ、上
部n M OSのチャネル長(L2)は極端に短かくせ
ざるをえないという欠点を有する。言いかえると、最小
チャネル寸法を2μm、マスク合わせ余裕を1.5μm
とした場合、L2 =2 μn’l + L+ =25
pmとなり、両MOSトランジスタの寸法に大きなア
ンバランスを生じ、占有面積が意に反して大きくなって
しまう、と同時に回路目体の駆動能力をも低下させてし
1う。However, according to the above-mentioned conventional example, since 1MO8 consisting of 4°5.6.7 is formed on the 9MO8 gate 4 formed on the surface of the 3i substrate, the pMOS channel length is (Ll), the channel length (L2) of the upper nMOS has to be extremely short. In other words, the minimum channel dimension is 2 μm and the mask alignment margin is 1.5 μm.
In this case, L2 = 2 μn'l + L+ = 25
pm, causing a large imbalance in the dimensions of both MOS transistors, undesirably increasing the occupied area, and at the same time reducing the driving ability of the circuit body.
本発明の目的は、上述した従来例の欠点を克服して、高
集積、高性能な半導体装置を提供することにある。An object of the present invention is to overcome the drawbacks of the conventional examples described above and provide a highly integrated and high-performance semiconductor device.
〔発明の概要J
本発明においては、下部に形成したMOS)ランジスタ
のチャネル寸法に依らず、自由自在な寸法のチャネル長
を有する上部MO8)ランジスタとするため、チャネル
の方向を下部のMOSトランジスタと交叉する方向とし
たところに特徴がある。[Summary of the Invention J In the present invention, in order to form an upper MO8) transistor having a channel length of any size, regardless of the channel dimensions of the MOS transistor formed at the lower part, the direction of the channel is different from that of the lower MOS transistor. They are characterized by their crossing directions.
以下、本発明の一実施例を第2図によシ説明する。第2
図は、本発明による半導体装置のパターン・レイアウト
図を示したものである。図中の番号は第1図における各
層の番号に対応している。An embodiment of the present invention will be explained below with reference to FIG. Second
The figure shows a pattern layout diagram of a semiconductor device according to the present invention. The numbers in the figure correspond to the numbers of each layer in FIG.
ただし、第2図では、第1図の10と13を同一金属配
線で接続してインバータ回路構成としである。CAはA
tと拡散層のコンタクト領域、CBはAtとゲート電極
とのコンタクト領域、CCは上部に積み上げて形成した
、例えばポリシリコン層とのコンタクト領域である。同
図から明らかな様に、本発明では、下部に形成した9M
O8のチャネル長L1と無関係に該MO8のゲート電極
4を共用して上部にチャネル長L2を有する1MO8を
形成できる。これは、従来例の如く、上部および下部の
MOS)ランジスタのソース、ドレイン間に流れる電流
を平行にはしらせる構造とは異なり、垂直にはしらせる
ことに依る。一方、本構造では上部MOSトランジスタ
のチャネル領域は第2図に示した6の領域で面積はL2
XWとなる。However, in FIG. 2, 10 and 13 in FIG. 1 are connected by the same metal wiring to form an inverter circuit configuration. CA is A
t and a contact region between the diffusion layer, CB a contact region between At and the gate electrode, and CC a contact region with, for example, a polysilicon layer stacked on top. As is clear from the figure, in the present invention, the 9M formed at the bottom
Regardless of the channel length L1 of O8, the gate electrode 4 of the MO8 can be shared to form one MO8 having a channel length L2 on the upper part. This differs from the conventional structure in which the current flows between the sources and drains of the upper and lower MOS transistors in parallel, but in that it flows perpendicularly. On the other hand, in this structure, the channel region of the upper MOS transistor is the region 6 shown in FIG. 2, and the area is L2.
It becomes XW.
本実施例では、上部MOSトランジスタの有効幅WEに
比べWは小さくなっているが、これはマスク合わせずれ
によって下部と共用するゲート電極4の幅WgとWEが
ずれている例を示したためである。WEがWIIを完全
におおう様に、あるいは、WsがWEを完全におおう様
にレイアウトすることにより、この問題は解決する。In this example, W is smaller than the effective width WE of the upper MOS transistor, but this is because the width Wg of the gate electrode 4 shared with the lower part deviates from WE due to mask alignment. . This problem can be solved by laying out the WE completely covering the WII or the Ws completely covering the WE.
以上述べた如く、本発明によれば高集積で、MOS)ラ
ンジスタの性能を低下させることのない半導体装置をえ
ることができる。As described above, according to the present invention, it is possible to obtain a highly integrated semiconductor device without deteriorating the performance of a MOS transistor.
第3図は、本発明の応用例を示したもので、CMOSイ
ンバータ回路で構成した6個のMOSトランジスタよ構
成るスタティック形メモリ・セルの回路図を示す。同図
の中で、31.32はデータ線、39はワード線、33
〜36は1MO8゜37.38はI)MOSである。こ
こで、本発明の特徴が最も発揮される点は、33〜36
なるnMO8l−ランジスタをSi半導体表面に形成し
、37.38なる9MO8をそれぞれ34.35のゲー
ト電極を共有する形で該トランジスタの上部に積層して
形成することである。この理由は、(1) 構造およ
び製造プロセス上、上部に積層したMOSトランジスタ
のゲート酸化膜を、下部に形成したトランジスタのケー
ト酸化膜はど薄くできないため、メモリの動作速度を決
める1MO8(33,34あるいは、35.36)はS
i半導体表面上に形成した方がより動作速度を速める点
で有利であること。FIG. 3 shows an example of application of the present invention, and shows a circuit diagram of a static memory cell composed of six MOS transistors composed of a CMOS inverter circuit. In the figure, 31.32 is a data line, 39 is a word line, and 33 is a data line.
~36 is 1MO8°37.38 is I) MOS. Here, the features of the present invention are most exhibited at points 33 to 36.
An nMO8l-transistor of 37.38 mm is formed on the surface of a Si semiconductor, and 9 MO8 transistors of 37.38 mm are laminated on top of the transistor so as to share the gate electrode of 34.35 mm. The reason for this is (1) Due to the structure and manufacturing process, it is impossible to make the gate oxide film of the MOS transistor stacked on the top as thin as the gate oxide film of the transistor stacked on the bottom. 34 or 35.36) is S
i Formation on the semiconductor surface is advantageous in terms of faster operation speed.
(2)37.38なる9MO8は、単に第3図における
Bあるいは0点に蓄積した情報を保持するに足る電流を
供給するだけでよく、−大きな駆動能力は必要でない。(2) The 9MO8 of 37.38 only needs to supply a current sufficient to hold the information stored at point B or 0 in FIG. 3, and does not require a large driving capacity.
従って、下部のnMO8上に積層して形成した方が集積
度を高める意味でも最も効果が太きい。特に、本発明の
半導体装置を用いることによって、集積度を損うことな
く積層化が可能となる。また、第2図で説明した如く、
マスク合わせずれによって上部に形成したpMO8の実
効ゲート幅が小さくなっても、上述した如く1)MO8
本来の役割りを損うものではない。Therefore, forming it by stacking it on the lower nMO8 is most effective in terms of increasing the degree of integration. In particular, by using the semiconductor device of the present invention, stacking can be performed without impairing the degree of integration. Also, as explained in Figure 2,
Even if the effective gate width of pMO8 formed on the upper part becomes smaller due to mask alignment misalignment, as described above, 1) MO8
It does not detract from its original role.
以上のように本発明によれば、ゲートを共用する垂直配
置のふたつのトランジスタのチャネル長に開きが少なく
、よって占有面積が小さくて駆動能力の大きな0M08
回路を得ることができる。As described above, according to the present invention, there is little difference in the channel lengths of two vertically arranged transistors that share a gate, and therefore the 0M08 transistor has a small occupied area and a large drive capacity.
You can get the circuit.
1・・・n形Si半導体基板、2,3・・・p形不純物
層、4・・・ゲート電極、6・・・p形シリコン層、5
.7・・・n形不純物層。DESCRIPTION OF SYMBOLS 1... N-type Si semiconductor substrate, 2, 3... P-type impurity layer, 4... Gate electrode, 6... P-type silicon layer, 5
.. 7...n-type impurity layer.
循 1 図 y z 図 V、S刃 しcc 第 3 図 国分寺市東恋ケ窪1丁目280番 地株式会社日立製作所中央研究 所内 0発 明 者 青木正明 国分寺市東恋ケ窪1丁目280番 地株式会社日立製作所中央研究 所内Circulation 1 Diagram yz diagram V, S blade cc Figure 3 1-280 Higashikoigakubo, Kokubunji City Hitachi, Ltd. Central Research Inside the office 0 shots by Masaaki Aoki 1-280 Higashikoigakubo, Kokubunji City Hitachi, Ltd. Central Research Inside the office
Claims (1)
ゲートを有する第1導電型のMOS)ランジスタと、該
トランジスタの上部に積層したソースドレイン、ゲート
を有する第2導電型のMOSトランジスタから成シ、該
第1導電型MOSトランジスタと該第2導電型MO8)
ランジスタのゲートが同一材料で形成されて互いに共用
してなる半導体装置において、該第1導電型MO8)ラ
ンジスタのソース、ドレイン間に流れる電流の方向と、
該第2導電型MOSトランジスタのソース、ドレイン間
に流れる電流の方向が互いに交差する方向としたことを
特徴とする半導体装置。1. Source and drain formed on one semiconductor surface,
A MOS transistor of a first conductivity type having a gate, a source drain stacked on the upper part of the transistor, and a MOS transistor of a second conductivity type having a gate, the first conductivity type MOS transistor and the second conductivity type MOS transistor. MO8)
In a semiconductor device in which gates of transistors are formed of the same material and shared by each other, the direction of current flowing between the source and drain of the first conductivity type MO transistor;
A semiconductor device characterized in that the directions of currents flowing between the sources and drains of the second conductivity type MOS transistors are directions that intersect with each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57147641A JPS5939061A (en) | 1982-08-27 | 1982-08-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57147641A JPS5939061A (en) | 1982-08-27 | 1982-08-27 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5939061A true JPS5939061A (en) | 1984-03-03 |
Family
ID=15434924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57147641A Pending JPS5939061A (en) | 1982-08-27 | 1982-08-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5939061A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01119052A (en) * | 1987-10-31 | 1989-05-11 | Nec Corp | Laminated mis semiconductor device |
US10472311B2 (en) | 2011-07-08 | 2019-11-12 | Mitsubishi Chemical Corporation | 1,4-butanediol-containing composition |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5028701U (en) * | 1973-07-09 | 1975-04-02 | ||
JPS5753972A (en) * | 1980-07-24 | 1982-03-31 | Siemens Ag |
-
1982
- 1982-08-27 JP JP57147641A patent/JPS5939061A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5028701U (en) * | 1973-07-09 | 1975-04-02 | ||
JPS5753972A (en) * | 1980-07-24 | 1982-03-31 | Siemens Ag |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01119052A (en) * | 1987-10-31 | 1989-05-11 | Nec Corp | Laminated mis semiconductor device |
US10472311B2 (en) | 2011-07-08 | 2019-11-12 | Mitsubishi Chemical Corporation | 1,4-butanediol-containing composition |
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