JP2001015719A - Gate array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a gate array, having a layout structure which realizes min. gate width requiring only low power consumption, even in a standard cell having a fixed number of horizontal wiring grids. SOLUTION: This gate array comprises standard cells, composed of n-wells 3 formed on a p-type semiconductor substrate, a rectangular pattern of p-type field diffusions 6 formed therein, p-type FETs having a common source or drain in the diffusions, a rectangular pattern of n-type field diffusions 7, and n-type FETs having a common source or drain in the diffusions, and the first and second conductive field effect transistors constituting the standard cell have gate widths reduced at the channel regions, as compared with the rectangular pattern height specifying the field diffusion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a gate array used for an information processing device and the like, and more particularly to a standard cell of a gate array.

[0002]

2. Description of the Related Art A gate array is a kind of semi-custom IC, and is diffused into standard cells having transistors regularly arranged on a semiconductor wafer in advance, and wiring corresponding to a circuit designed by a user is standard cell. To the desired L
This is to realize SI, and the wafer on which the standard cell is created is called a master or a base. However, since the manufacturing process is completed only by forming wiring on this wafer, the advantage that it can be completed in a shorter time than the cell-based IC is is there. Structurally, there are a channel type in which a standard cell portion and a wiring region are completely separated, and a channelless type in which a basic cell is spread over the entire surface of a chip so that a wiring region can be freely taken.
The latter ECA (Embedded Cell Arra
y).

FIG. 7 is a layout diagram showing an example of a layout pattern of a conventional gate array having a CMOS structure. In FIG.
The lower half shows an N-channel transistor portion, 1 is a power supply wire for power supply, 2 is a ground wire for ground supply, 3 is an N well, 4 and 5 are gate electrodes made of polycrystalline silicon or polysilicon, 6, Reference numeral 7 denotes a rectangular pattern having field diffusions of P-type and N-type, respectively. Reference numerals 8, 9, and 10 denote logic wirings made of a metal such as aluminum and formed by a second wiring layer to realize logical connection. Reference numeral 13 designates a logic wiring which is also made of a metal such as aluminum and is formed of a third wiring layer to realize logical connection, and reference numeral 14 denotes a wiring on which the center lines of the power supply wiring 1, the ground wiring 2 and the logical wirings 8 to 13 are placed. Lattice, 101 is a P-type semiconductor substrate, s51 to
s53 is a second via for electrically connecting the logic wirings 8 to 10 and the logic wirings 11 to 13, respectively, Wp is the gate width of the P-channel transistor, Lp is the gate length of the P-channel transistor, Wn is the gate width of the N-channel transistor, L
n is the gate length of the N-channel transistor.

A P channel region is formed below the gate electrode 4 with a gate insulating film (not shown) interposed therebetween. The gate electrode 4, a P-type field diffusion 6 formed in the N well 3, and a gate insulating film are formed. A p-channel MOS transistor having a plurality of P-channel MOS field-effect transistors or FETs (hereinafter referred to as pMOS) sharing a source or a drain by a film.
A MOS region is formed. Similarly, an N-channel region is formed below the gate electrode 5 via a gate insulating film, and a plurality of N-channels sharing a source or a drain are formed by the gate electrode 5, the N-type field diffusion 7, and the gate insulating film. MOS field effect transistor or F
An nMOS region including ET (hereinafter, referred to as nMOS) is formed. By including both the pMOS and the nMOS in the standard cell, the gate array of FIG. 7 has a CMOS structure. In addition, the above-mentioned nMOS and pMOS
Transistor size is related to the operating speed of the LSI composed of the gate array. To realize high-speed operation, the gate width W (together, Wn and Wp is referred to as W) is wide, and the gate length L (together Lp, Ln). L) is shorter.

FIG. 8 is a diagram showing a pattern relationship between a field diffusion and a gate electrode of a conventional gate array standard cell. In the figure, 6 and 7 are P-type or N-type field diffusion,
4, 5 are gate electrodes made of polysilicon, h is the height of field diffusion 6, 7, C / A is a channel region, A / A
Is the active area, and W is the gate width. Normally, the gate width W of the transistors formed in the field diffusions 6 and 7 is equal to the height h, and the channel region is defined by the product of the gate width W and the gate length L.

FIG. 9 is a layout diagram describing a two-input NAND circuit for explaining the operation of a conventional gate array.
FIG. 10 is an equivalent circuit diagram thereof. In the figure, the upper half shows a P-channel transistor portion, the lower half shows an N-channel transistor portion, 4a to 4d and 5a to 5d show gate electrodes made of polysilicon, and 11 'and 12' made of a metal such as aluminum. Logic wirings formed from wiring layers for realizing logical connection, 15 to 21 are also formed of a metal such as aluminum, and are formed from the first wiring layer for realizing logical connection, c1 to c13 are contacts,
f1 is the first electrical connection between the logic wiring 10 and the logic wiring 17
Vias s1 and s2 are second vias for electrically connecting the logic wirings 11 'and 12' to the logic wirings 8 and 9, respectively, and g1 and g2 are logic wirings 11 'and 12' and the logic wirings 18 and 19, respectively.
Are electrically connected to a first via and a second via, and t1 to t4 are a contact and a first via for contacting the power supply wiring 1 and the ground wiring 2 with the substrate, respectively. Hereinafter, the same reference numerals denote the same or corresponding parts, and a description thereof will be omitted.

Logic wirings 8 and 9 are electrically connected to inputs A and B, respectively, and receive a signal input of power supply VDD level, that is, "H" or ground level, that is, "L".
Outputs a "H" or "L" signal from the output Y after the logical operation.

Next, the operation will be described. In the layout configuration of FIG. 9, the VDD level, ie, “H” is input to the contacts c3 and c4 formed in the P-type field diffusion 6 from the power supply line 1 via (contact + first via) t1 and t2, respectively. The state in which the VSS level, that is, “L” is input to the contact c11 formed in the field diffusion 7 from the ground wiring 2 via the (contact + first via) t4 from the ground wiring 2 is shown.
ET is the gate electrodes 4b, 4c, 5b, 5c.

Here, for example, when the signal "H" is input to the input A, the logic wiring 8 passes through the logic wiring 11 'via the second via s1, and further (the first via + the second via). is transmitted to the inverted U-shaped logic wiring 18 via g1;
The signal “H” is supplied to the gate electrodes 4b and 5b via the contacts c6 and c8, and the gate electrode 5b on the nMOS side is turned on and the gate electrode 4b on the pMOS side is turned off.

On the other hand, when a signal "L" is input to the input B, the logic wiring 9 passes through the logic wiring 12 'via the second via s2, and further passes through the (first via + second via) g2. Through the inverted U-shaped logic wiring 19 via the contact c
The signal "L" is supplied to the gate electrodes 4c and 5c via the gate electrodes 7 and c9, the gate electrode 5c on the nMOS side is turned off, and the pMO
The S-side gate electrode 4c is turned on.

Therefore, on the pMOS side, the gate electrode 4
b and 4c are turned off and on, respectively, and a signal "H" is output to the output Y via the contact c5 and the first via f1. However, on the nMOS side, the gate electrodes 5b and 5c are turned on and off, respectively. No signal is supplied to the contact c10 because it is not continuously turned on, and as a result, "H" is output from the output Y.

[0012]

Since the conventional gate array is configured as described above, the field diffusions 6 and 7 of the standard cells have a rectangular pattern as shown in FIGS. The transistor gate widths Wp and Wn are determined by the height h of the rectangle. On the other hand, the vertical size, that is, the height h of the field diffusions 6, 7 is AND,
The minimum width required to create the logical gates such as OR and NAND through the horizontal logic wirings 8 to 10 is necessary. That is, the width is determined by the minimum number of horizontal wiring grids. This did not mean that there was a certain lower limit determined by the design rules between wires. As a result, the gate width W of the transistor also has a certain lower limit determined by the design rule between the wirings, which is determined according to this limit, which hinders a reduction in power consumption of the gate array standard cell. was there.

Further, in order to equalize the rising and falling operation speeds of the logic gate, as shown in FIG.
The ratio (ratio) between the gate width Wp of the P-channel transistor and the gate width Wn of the N-channel transistor needs to be 2: 1. For this reason, there is a restriction on the logic configuration on the N-channel transistor side where the transistor size is reduced. There is a problem that it is difficult to secure a sufficient number of wiring grids in the horizontal direction. The present invention has been made to solve the above problems,
It is an object of the present invention to obtain a gate array having a layout configuration that realizes a minimal gate width requiring low power consumption even in a standard cell having a fixed number of horizontal wiring grids.

[0014]

According to the present invention, there is provided a gate array comprising: a second conductive well formed on a first conductive semiconductor substrate; and a rectangular conductive first conductive diffusion layer formed therein. And a first conductive field effect transistor sharing a source or a drain in the diffusion layer, and a second conductive diffusion layer in a rectangular pattern formed on the substrate, and the source or the drain therein. And a standard cell including a second conductive field effect transistor sharing the same. At least one of the first and second conductive field effect transistors constituting the standard cell includes:
The gate width of the channel region immediately below the gate electrode is smaller than the height of the rectangular pattern defining the diffusion layer.

In the gate array according to the present invention, immediately below the gate electrode, the boundary between the channel region and the active region with the reduced gate width and the adjacent field oxide film overlaps the outline of the gate electrode.

In the gate array according to the present invention, the first and second conductive field-effect transistors constituting the standard cell have the same transistor area, while the first and second conductive field-effect transistors have the same area.
The gate width is partially reduced.

In the gate array according to the present invention, the rectangular pattern of the diffusion layer has an H shape, a comb shape,
It includes a hollow die, a meandering pattern, or a combination thereof.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 shows C according to Embodiment 1 of the present invention.
FIG. 3 is a layout diagram showing an example of a layout pattern of a gate array having a MOS structure, in which an upper half shows a P-channel transistor portion and a lower half shows an N-channel transistor portion, 1 is a power supply line for supplying power, and 2 is a ground. Ground wiring for supply, 3 an N well, 4 and 5 gate electrodes made of polycrystalline silicon or polysilicon, 6 and 7 rectangular P-type and N-type field diffusions, 8, 9, 1
Numeral 0 is a logical wiring made of a metal such as aluminum and formed from the second wiring layer to realize logical connection.
Reference numeral 13 denotes a logic wiring which is also made of a metal such as aluminum and is formed of a third wiring layer to realize a logical connection.
Is a wiring grid on which the center lines of the power supply wiring 1, the ground wiring 2, and the logic wirings 8 to 13 are mounted, 101 is a P-type semiconductor substrate, s5
1 to s53 are the second vias, Wp is the gate width of the P-channel transistor, Lp is the gate length of the P-channel transistor, Wn is the gate width of the N-channel transistor, and Ln is the gate length of the N-channel transistor.

A P-channel region is formed below the gate electrode 4 with a gate insulating film (not shown) interposed therebetween. The gate electrode 4, the P-type field diffusion 6 formed in the N well 3, and the gate insulating film are formed. PMO having a plurality of pMOS transistors sharing a source or a drain by a film
An S region is formed. Similarly, an N-type channel region is formed below the gate electrode 5 via a gate insulating film, and a plurality of nMOSs sharing a source or a drain are formed by the gate electrode 5, the N-type field diffusion 7 and the gate insulating film. An nMOS region including a transistor is formed.

The difference between the layout structure of the first embodiment and the conventional example is that the gate width Wp of the P-channel transistor is smaller than the height of the P-type field diffusion 6, as can be seen by comparing FIGS. Similarly, the gate width Wn of the N-channel transistor is also smaller than the height of the N-type field diffusion 7. In the conventional example, the number of wiring grids in the horizontal direction is different from six in the P-channel transistor part and three in the N-channel transistor part.
The first embodiment differs from the first embodiment in that the number of the wiring grids is the same as that of the former and the latter is five.

That is, in the first embodiment, even in an N-channel transistor having a high operating speed, the gate width Wn is locally reduced, so that the channel region can be reduced in area and the size of the transistor can be reduced. The gate width Wn can be determined independently of the size of the N-type field diffusion 7. Thus, the ratio of the gate width Wp of the P-channel transistor to the gate width Wn of the N-channel transistor can be set to 2: 1 while keeping the layout region on the P-channel transistor side and the layout region on the N-channel transistor equal. . As a result, the number of wiring grids in the horizontal direction can be equalized between the P-channel side and the N-channel side to configure the logic of the standard cell, and the layout of the logic wiring for configuring the logic can be more easily arranged. As a result, the area of the standard cell of the gate array is effectively reduced.

Next, the transistor structure of the standard cell of the gate array according to the first embodiment will be described with reference to the drawings. FIG. 2A is a top view of a pMOS transistor constituting a standard cell, and FIG. 2B is a longitudinal sectional view taken along line II. FIG. 3A is a top view of another pMOS transistor in the standard cell.
(B) is a cross-sectional view along the line II-II. In the figure, 3 is an N well, 4 is a gate electrode made of polysilicon, 6a and 6b are P type field diffusion,
31 is a field oxide film, 32 is T
An interlayer insulating film made of an organic silane such as EOS, 61
Is a power supply wiring contacting the active area A / A, C
/ A is a channel region.

As can be seen from FIG. 2B, the field oxide film 31 protrudes from both sides to narrow the gate width Wp and define the channel region C / A. The active region A / A is composed of P-type field diffusions 6a and 6b and a channel region C / A. When viewed as a single transistor, the active region A / A has an H-type pattern shape. The layout is such that the outlines of the power supply wiring constituting the electrode 4 are overlapped (see FIG. 3). This has the effect of minimizing the horizontal size of the standard cell, and consequently reducing the area of the LSI chip using the standard cell.

FIG. 4 is referred to in order to explain this in detail. FIG. 4 is a diagram showing a pattern relationship between a field diffusion and a gate electrode of a gate array standard cell according to the first embodiment of the present invention. In the figure, 6, 7 are P-type or N-type field diffusion, 4 and 5 are gate electrodes made of polysilicon, h is the height of field diffusion, C / A is a channel region, A / A is an active region, and W is Is the gate width.
The difference from the conventional example shown in FIG. 8 is that the gate width W of the transistor is reduced and the area of the channel region C / A is reduced. Thereby, H of the field diffusion 6, 7
It will be appreciated how the outlines inside the pattern are superimposed.

As described above, according to the first embodiment, the gate width is reduced by making the pattern shape of the field diffusions 6 and 7 of the transistor H-type, thereby making the transistor proportional to the reciprocal of the gate width. The effect that the power consumption of the device can be reduced is obtained.

The pattern shapes of the field diffusions 6 and 7 are the same as those of the above-described H type, as shown in FIGS.
The one shown in (c) can be considered. 5A shows a comb-shaped pattern, FIG. 5B shows a hollow pattern, and FIG. 5C shows a meandering pattern. A composite pattern obtained by combining these patterns can also be considered. This also has the effect of minimizing the lateral size of the standard cell and reducing the area of the LSI chip.

FIG. 6 is a layout diagram describing a two-input NAND circuit for describing the operation of the gate array according to the first embodiment, and FIG. 10 is an equivalent circuit diagram thereof. In the figure, the upper half shows a P-channel transistor part, and the lower half shows an N-channel transistor part.
To 5d are gate electrodes made of polysilicon, 11 ', 1
Reference numeral 2 'denotes a logical wiring made of a metal such as aluminum and formed of a third wiring layer for realizing a logical connection.
Are logical wirings c1 to c which are also made of a metal such as aluminum and formed from the first wiring layer to realize logical connection;
13 is a contact, f1 is a logical wiring 10 and a logical wiring 17
The first vias s1 and s2 electrically connect the logic wirings 11 ′ and 12 ′ to the logic wirings 8 and 9, respectively.
The vias, g1 and g2, are the first via + second via for electrically connecting the logic wirings 11 ', 12' and the logic wirings 18, 19, respectively, and t1 to t4 are the substrate contacts between the power supply wiring 1 and the ground wiring 2, respectively. Contact + first via.

Logic lines 8 and 9 are electrically connected to inputs A and B, respectively, and receive an input signal of power supply VDD level "H" or ground level "L". Logic line 10 outputs "H" from output Y after logical operation. Alternatively, an "L" signal is output. The power supply VDD level is supplied to the gate electrodes 4a, 4d via the contacts c1, c2, and the contacts c12,
The ground VSS level is changed to the gate electrodes 5a and 5 via c13.
The signal d is supplied for element isolation or isolation.

Next, the operation will be described. In the layout configuration of FIG. 6, the VDD level, that is, “H” is input to the contacts c3 and c4 formed in the P-type field diffusion 6 from the power supply wiring 1 via (contact + first via) t1 and t2, respectively. The state in which the VSS level, that is, “L” is input to the contact c11 formed in the field diffusion 7 from the ground wiring 2 via the (contact + first via) t4 from the ground wiring 2 is shown.
ET is the gate electrodes 4b, 4c, 5b, 5c.

Here, for example, when a signal "H" is input to the input A, the logic wiring 8 passes through the logic wiring 11 'via the second via s1, and further (the first via + the second via). is transmitted to the inverted U-shaped logic wiring 18 via g1;
The signal “H” is supplied to the gate electrodes 4b and 5b via the contacts c6 and c8, and the gate electrode 5b on the nMOS side is turned on and the gate electrode 4b on the pMOS side is turned off.

On the other hand, when the signal "H" is input to the input B, the logic wiring 9 passes through the logic wiring 12 'via the second via s2, and further (the first via + the second via) g2. Is transferred to the inverted U-shaped logic wiring 19 through the contact c
The signal "H" is supplied to the gate electrodes 4c and 5c via the gate electrodes 7 and c9, the gate electrode 4b on the nMOS side is turned on, and the pMO
The S-side gate electrode 4c is turned off.

Therefore, on the pMOS side, the gate electrode 4
Since both b and 4c are off and off, the contact c
5 is not supplied to the gate electrode 5 on the nMOS side.
Since b and 5c are turned on and on, respectively, they are continuously turned on, and the signal "c" is passed through the contact c10 and the first via f1.
L ”is supplied, and as a result, the signal“ L ”is output from the output Y.

As described above, according to the first embodiment, the pattern width of the field diffusions 6 and 7 constituting the transistor of the standard cell for the gate array is H-shaped, so that the gate width W of the transistor is reduced. Since it can be set arbitrarily irrespective of the height limitation of the array standard cells, the effect of reducing the power consumption of the standard cells determined by the gate width W can be obtained.

Further, according to the first embodiment, the layout in which the inner portions of the H-type patterns of the field diffusions 6 and 7 are overlapped with the outline of the polysilicon wiring forming the gate electrode is provided. This has the effect of minimizing the lateral size of the cell and consequently reducing the area of the gate array LSI chip using standard cells.

Further, according to the first embodiment, since the gate width W of the transistor can be determined independently of the size of field diffusions 6, 7, the layout region on the P-channel transistor side as shown in FIG. And the layout area on the N-channel side can be made equal, and the ratio of the gate width Wp of the P-channel transistor to the gate width Wn of the N-channel transistor can be made 2: 1. As a result, the number of horizontal wiring grids for configuring the logic of the standard cell can be equalized between the P-channel side and the N-channel side, and the layout of the logic wiring for configuring the logic can be more easily performed. As a result, the effect of realizing a reduction in the area of the standard cell and, consequently, the LSI chip is obtained.

[0036]

As described above, according to the present invention, at least one of the first and second conductive field effect transistors constituting the standard cell of the gate array has the gate width of the channel region immediately below the gate electrode. Is configured to be smaller than the height of the rectangular pattern defining the diffusion layer, so that the gate width of the field effect transistor can be arbitrarily reduced regardless of the height limitation of the rectangular pattern defining the diffusion layer. Can be set. Therefore, the drain current passing through the channel region can be controlled by changing the gate width while keeping the gate length of the field effect transistor constituting the standard cell constant, thereby reducing the power consumption of the standard cell and consequently the gate. This has the effect of reducing the power consumption of the entire array.

According to the present invention, the boundary between the channel region and the active region and the adjacent field oxide film due to the reduced gate width is formed so as to overlap the outline of the gate electrode. Has the effect of minimizing the size of the gate array chip and consequently reducing the area of the entire gate array chip.

According to the present invention, the first and second conductive field effect transistors constituting the standard cell are configured such that the gate width is partially reduced while the areas of the transistor regions are made uniform. Therefore, the number of horizontal wiring grids for configuring the logic of the standard cell can be equalized between the first conductive side and the second conductive side, thereby easily laying out wiring for logic configuration. As a result, the area of the standard cell of the gate array can be reduced.

According to the present invention, since the rectangular pattern of the diffusion layer is configured to include an H-shaped, comb-shaped, hollow-shaped, meandering pattern, or a combination thereof in relation to the channel region. There is an effect that standard cells of various gate arrays can be designed according to design needs.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a standard cell of a gate array according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a transistor structure of a standard cell of the gate array according to the first embodiment of the present invention;

FIG. 3 is a configuration diagram showing a transistor structure of a standard cell of the gate array according to the first embodiment of the present invention;

FIG. 4 is a diagram showing a pattern relation between a field diffusion of a standard cell of a gate array and a gate electrode according to the first embodiment of the present invention;

FIG. 5 is a pattern diagram showing a pattern shape of field diffusion according to the first embodiment of the present invention.

FIG. 6 is a layout diagram describing a two-input NAND circuit for a standard cell of the gate array according to the first embodiment of the present invention;

FIG. 7 is a layout diagram of a standard cell of a conventional gate array.

FIG. 8 is a diagram showing a pattern relationship between a field diffusion of a standard cell of a conventional gate array and a gate electrode.

FIG. 9 is a layout diagram describing a two-input NAND circuit for a standard cell of a conventional gate array.

FIG. 10 is an equivalent circuit diagram corresponding to the two-input NAND circuit of FIGS. 6 and 9;

[Explanation of symbols]

Reference Signs List 1 power supply wiring, 2 ground wiring, 3N well (second conductive well), 4, 4a to 4d, 5, 5a to 5d gate electrode, 6P field diffusion (first conductive diffusion layer), 6a , 6b P-type field diffusion (source / drain), 7 N-type field diffusion (second conductive diffusion layer), 8 to 13 logic wiring, 14 wiring grid, 31 field oxide film, 101 P-type semiconductor substrate (first Conductive semiconductor substrate), C / A channel region, A / A active region, W, Wp, Wn Gate width.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroaki Nishino 2-6-1 Otemachi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Engineering Co., Ltd. (72) Inventor Seiko Nakanishi 2-6-Otemachi, Chiyoda-ku, Tokyo No.2 Mitsubishi Electric Engineering Co., Ltd. F term (reference) 5F048 AA01 AB02 AC03 BB01 BC01 BD01 5F064 AA03 CC12 DD05 DD10 EE15

Claims (4)

[Claims] A second conductive well formed on a first conductive semiconductor substrate and a first conductive diffusion layer having a rectangular pattern formed therein; A first conductive field effect transistor sharing a source or a drain therein, and a rectangular conductive second conductive diffusion layer formed on the semiconductor substrate, wherein the source is disposed in the second conductive diffusion layer. Alternatively, in a gate array including a standard cell including a second conductive field effect transistor sharing a drain, at least one of the first and second conductive field effect transistors forming the standard cell includes a gate electrode. A gate array, wherein a gate width of a channel region immediately below the gate region is smaller than a height of a rectangular pattern defining the diffusion layer. 2. The semiconductor device according to claim 1, wherein immediately below the gate electrode, the boundary between the channel region and the active region and the adjacent field oxide film due to the reduced gate width is overlapped with the outline of the gate electrode. Gate array. 3. The first and second conductive field-effect transistors constituting the standard cell have at least one of these field-effect transistors having a gate width partially reduced while equalizing the area of each transistor region. The gate array according to claim 1, wherein the gate array is formed. 4. The method according to claim 1, wherein the rectangular pattern of the diffusion layer includes an H-shaped pattern, a comb-shaped pattern, a hollow pattern, a meandering pattern, or a combination thereof in relation to the channel region. Item 3. The gate array according to Item 2.