JP2000223575A - Design of semiconductor device, semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently reinforce power lines without having restriction on the layout of signal lines. SOLUTION: First layer power lines 3VDD1, 3VSS1, third layer power lines 3VDD3, 3VSS3 in parallel with the first layer power lines, and a second layer signal line 3S2 are disposed and wired to wire cells. Thereafter, a connection hole TH2 for electrically connecting the first layer power lines 3VDD1, 3VSS1 and the third layer power lines 3VDD3, 3VSS3 is disposed in a vacant channel of the second layer signal line. Thereby, the first layer power lines 3VDD1, 3VSS1 can be reinforced by the third layer power lines 3VDD3, 3VSS3 without causing restriction on the layout of the second layer signal line 3S2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device technology, and more particularly, to an ASIC (AP).
Replication Specific Integrated Circuit: a technology that is effective when applied to the manufacturing technology of IC for specific applications.

[0002]

2. Description of the Related Art A semiconductor device representing an ASIC is, for example, a gate array. In this gate array, a semiconductor substrate on which a plurality of basic cells are formed is prepared in advance, and a desired logic circuit is formed on the semiconductor substrate by changing the way of wiring between the basic cells. This constitutes a semiconductor device having a logical function. In ASICs, power supply reinforcement techniques for reducing power supply noise during circuit operation and preventing power supply wiring migration have become important along with improvements in the degree of element integration and operation speed in semiconductor devices. This type of technique is described in, for example, Japanese Patent Application Laid-Open No. 2-165652. This document describes a standard cell LSI.
In a (Large Scale Integrated Circuit), when a plurality of cells are arranged to form a standard cell row, a first layer wiring for power supply and a third layer wiring for power supply are electrically connected at the center of the cell row. By providing a dummy cell with a through through hole to connect, at the center of the cell row,
A structure is disclosed in which a power supply is reinforced from a power supply third-layer wiring to a power supply first-layer wiring through a through-hole.

[0003]

However, the present inventors have found that the technology disclosed in the above publication has the following problems.

That is, in the above technique, when arranging and wiring standard cells, a dummy cell having a through-hole electrically connecting the first-layer wiring for power supply and the third-layer wiring for power supply is arranged. Therefore, in the area where the dummy cells are arranged, the second layer wiring for signals cannot be arranged, and when the number of dummy cells is increased to sufficiently enhance the power supply, the signal in the second wiring layer is There is a problem that the arrangement of the wiring is restricted.

In the above-described technique in which a dummy cell having a through-hole is provided only at the center of a standard cell row, a power supply is disposed in a region farthest from the through-hole. Cannot be sufficiently reinforced, and there is a problem even from the viewpoint of power supply reinforcement.

In addition to the above technique, as a method of reinforcing the power supply, it is conceivable to arrange a large number of second-layer wirings for power supply in advance. Second layer for power supply
If a large number of layer wirings are arranged, there is a problem that the area required for arranging the second layer wiring for signals connecting the basic cells is extremely reduced.

An object of the present invention is to provide a technique that can efficiently reinforce a power supply wiring without limiting the arrangement of signal wiring.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A method for designing a semiconductor device according to the present invention is a method for designing a semiconductor device having a multi-layer wiring, comprising: (a) a step of arranging a plurality of basic cells; And (c) after the step (b), a step of disposing a power supply reinforcing connection hole for electrically connecting different wiring layers in the empty channel.

A semiconductor device according to the present invention is a semiconductor device having a multi-layer wiring, wherein field effect transistors of a plurality of basic cells are formed in a first region of a semiconductor substrate, and a predetermined potential is applied to the first region. And a first power supply line electrically connected to a source of a field effect transistor of the plurality of basic cells is arranged in the first direction. And a second power supply wiring and a first wiring extend in the first direction in a second wiring layer above the first power supply wiring and the first power supply wiring. The second power supply line is formed above the first power supply line, and is electrically connected to the first power supply line, and a wiring channel is provided above the first power supply line. And the wiring channel region is provided with the first power supply. The line in which electrically unconnected said first wiring is disposed.

Further, in the semiconductor device according to the present invention, a cross-sectional area of the second power supply wiring is larger than a cross-sectional area of the first power supply wiring.

Further, in the semiconductor device according to the present invention, a silicide layer is provided on a surface layer of the power supply region.

Further, in the semiconductor device according to the present invention, a metal film which is in direct contact with the power supply region and extends along the extending direction is provided on the power supply region.

Another brief description of the present invention is as follows.

In the semiconductor device of the present invention, among the two types of field effect transistors having different gate widths, the field effect transistor having a relatively small gate width is composed of a plurality of p-channel type field effect transistors and a plurality of n type field effect transistors. A wide pattern comprising a channel-type field-effect transistor, each gate electrode of which is arranged in a region between the plurality of p-channel-type field-effect transistors and the plurality of n-channel-type field-effect transistors. And are electrically connected to each other.

Further, in the semiconductor device of the present invention, the same channel conductivity type field effect transistors of the two types of field effect transistors having different gate widths in the basic cell are adjacent to each other in a plane, and They are arranged in the same semiconductor region.

The semiconductor device according to the present invention is provided with switching means for switching a voltage applied to the semiconductor region to an operating voltage or a substrate voltage.

The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, comprising: (a) a step of arranging a plurality of basic cells on a main surface of a semiconductor substrate;
Arranging a first power supply wiring composed of a first wiring layer in a channel in a first direction; and (c) in a second wiring layer above the first wiring layer in the first direction. Arranging a second power supply line for reinforcing the first power supply line in a channel parallel to the first and second wiring layers; and (d) forming a third power supply line between the first and second wiring layers. (E) after the step (d), arranging a signal line in a channel in a second direction intersecting with the first direction in the wiring layer.
Arranging a connection hole for electrically connecting the first power supply wiring and the second power supply wiring.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. In the present embodiment, an n-channel MISFET (Me
tal Insulator Semiconductor Field Effect Transisto
r) is abbreviated as nMIS, and a p-channel type MISFET is abbreviated as pMIS. A wiring for supplying a power supply voltage is referred to as a power supply wiring, and a wiring for transmitting an electric signal is referred to as a signal wiring. A channel in a wiring is a wiring path in which the wiring is arranged. The channel direction is a direction in which the wiring extends. Further, an empty channel refers to a wiring path where no wiring is arranged.

(Embodiment 1) In Embodiment 1, a case where the present invention is applied to, for example, a gate array will be described. FIGS. 1A and 1B are plan views of a semiconductor chip 1 constituting a semiconductor integrated circuit device of the present invention. FIG. 1A schematically shows the arrangement of the basic cells 2 in the semiconductor chip 1, and FIG. 1B schematically shows a plan view of the semiconductor chip 1 after the arrangement and wiring process.
1A and 1B are the same semiconductor chip 1, but are shown separately for easy understanding of the drawing.

The semiconductor chip 1 is formed, for example, by using a small piece of silicon single crystal having a plane square shape as an element forming member.
In the center of the main surface (internal circuit area), a plurality of basic cells 2
Are paved regularly. That is, the gate array according to the present embodiment is a so-called full-surface type (Sea Of
Gate) or a gate array called a channelless type. However, the present invention is not limited to this, and the present invention is applied to a general gate array in which a plurality of basic cell rows in which a plurality of basic cells 2 are provided in a straight line are provided, and a wiring channel is provided therebetween. It is also possible.

The basic cell 2 is a unit area having one or a plurality of elements capable of forming a basic logic circuit (for example, an OR circuit, a NOR circuit, an AND circuit, a NAND circuit or an inverter circuit). . Semiconductor chip 1
In FIG. 1, a basic logic circuit or a relatively large logic circuit (the area indicated by hatching in FIG. 1) is formed by one or a plurality of basic cells 2, and a wiring 3 is provided between the logic circuits. (Hatched hatching in FIG. 1 (b)) and are electrically connected, for example, a microprocessor or the like.
A semiconductor integrated circuit device having a predetermined logic function is configured. The basic cell 2 mainly includes a pMIS formed in the n-type well region NWL and an nMIS formed in the p-type well region PWL. Hereinafter, the well region is simply referred to as a well. A specific configuration example of the basic cell 2 will be described later.

A plurality of I / O (Input / Output) cells 4 and bonding pads 5 are arranged on the outer periphery of the main surface of the semiconductor chip 1 (outer periphery of the internal circuit area) along each side of the semiconductor chip 1. . The I / O cell 4 is a unit area for configuring an input / output circuit such as an input circuit, an output circuit, or an input / output bidirectional circuit. The input circuit has a function of bringing a power supply voltage or an electric signal from outside the semiconductor chip 1 into a state suitable for a circuit inside the semiconductor chip 1, and the output circuit has an electric circuit formed inside the semiconductor chip 1. It has a function of transmitting a signal to a target electronic device through a transmission line outside the semiconductor chip 1 so as not to attenuate the signal. The bonding pad 5 is a portion to which a bonding wire is bonded, through which a power supply voltage and an electric signal between the inside and outside of the semiconductor chip 1 are input and output. Note that the bonding pads 5 are made of, for example, aluminum, aluminum alloy, or copper having a planar square shape, and are arranged for each I / O cell 4.

Next, a power supply configuration of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

In the semiconductor integrated circuit device of the first embodiment, in order to control the threshold voltage of the MISFET formed on the semiconductor chip 1, the operating power supply voltage of the semiconductor integrated circuit device is applied to the semiconductor substrate or the well. VDD, VSS
Power supply voltages VDBB, VSB for controlling the substrate potential different from
B can be supplied.

FIG. 2 is a circuit diagram showing the structure. Power supply wirings 3VDD1 and 3VS1 for supplying power supply voltages VDD and VSS, which are operating voltages of the semiconductor integrated circuit device, are connected to the basic cell 2
NMISQn and pMISQp are electrically connected to MISFEs for switches, respectively.
Power supply wiring 3VD2, 3VS2 through TQsp2, Qsn2
It is a structure that can be electrically connected to Power supply voltage VDD
Is, for example, about 1.5 V, and the power supply wiring VSS is, for example, about 0 V. The power supply generation circuit 6 is a circuit for generating the power supply voltages VDBB and VSBB for controlling the substrate potential.
The switching MISFETs Qsp1 and Qsn1 have a structure that can be electrically connected to the power supply wirings 3VD2 and 3VS2, respectively. The power supply wirings 3VD2 and 3VS2 are connected to a semiconductor substrate or a well (for example, PWL, NWL described later; see the connection state of nMISQn and pMISQp substrates or well power supply electrodes of the basic cell 2) at the time of inspection or standby of the semiconductor integrated circuit device. On the other hand, it is a power supply wiring for supplying the power supply voltages VDBB and VSBB for controlling the substrate potential and supplying the operation power supply voltages VDD and VSS during normal operation. The power supply voltage VDBB is, for example, about 3.0 V, and the power supply voltage VSBB is, for example, about -1.5 V. Thus, the power supply voltage VDBB has a higher potential than the power supply voltage VDD, and the power supply voltage VSBB has a lower potential than the power supply voltage VSS. Thus, the MIS for the switch
The FETs Qsp1, Qsn1, Qsp2, and Qsn2 are circuits for switching the potentials of the power supply wirings 3VD2 and 3VS2.
For example, the switch MISFETs Qsp1 and Qsn1 are turned on, and the switch MISFETs are set to Qsp2 and Qs
By turning off n2, the power supply lines 3VD2 and 3VS2
The power supply voltages VDBB and VSBB are applied, respectively, and the power supply wiring 3
Power supply voltages VDD and VSS can be applied to VDD1 and 3VS1, respectively. Further, for example, a MISFET Qsp1 for a switch
, Qsn1 are turned off, and the switch MISFETs are turned on, Qsp2 and Qsn2.
The power supply voltage VDD is applied to D1 and 3VD2, and the power supply wiring 3VS
The power supply voltage VSS can be applied to 1, 3VS2. As described above, the power supply voltages VDBB and VSBB are applied to the well or the semiconductor substrate via the power supply wirings 3VD2 and 3VS2 at the time of standby or during the inspection process. The switching cell SW1 has MISFETs Qsp1 and Qsn1 for switching and is composed of the basic cell 2. That is, the MISFE in the basic cell 2
MISFETs Qsp1 and Qsn for switches using T
1 is configured. The switching cell SW2 has switching MISFETs Qsp2 and Qsn2 and is composed of the basic cell 2. That is, the MISF in the basic cell 2
ET FETs Qsp2 and Qs for switches using ET
n2.

FIGS. 3A and 3B show an example of a basic logic circuit composed of nMISQn and pMISQP of the basic cell 2 of FIG. 2. FIG. 3A shows an inverter circuit INV. FIG. 3B shows the NAND circuit N
Is shown. However, the basic logic circuit formed in the basic cell 2 is not limited to these, and can be variously changed. For example, a NOR circuit and an AND circuit can be formed. Here, the MISFET is a gate electrode,
The description will be made assuming that the electrode has four electrodes: a first electrode, a second electrode, and a substrate or well power supply electrode (hereinafter, simply referred to as a substrate electrode). This first electrode is a MISFET
3 is an electrode on the upper side of the MISFET in FIG.
The second electrode is an electrode corresponding to the other of the source and drain electrodes of the MISFET.
It is the lower electrode of ET.

The inverter circuit INV shown in FIG.
PMISQp and one nMISQn are connected to the power supply wiring 3
It is configured to be connected in series between VD1 and 3VS1. p
The gate electrodes of MISQp and nMISQn are electrically connected to each other, and an input terminal IN is drawn from a wiring connecting the respective gate electrodes. The first of pMISQp
The electrode is electrically connected to the power supply wiring 3VD1. pM
The second electrode of ISQp is electrically connected to the first electrode of nMISQn, and an output terminal OUT is drawn from a wiring connecting the second electrode and the first electrode. Furthermore, pMIS
The substrate electrodes of Qp and nMISQn are electrically connected to power supply wirings 3VD2 and 3VS2, respectively.

The NAND circuit N shown in FIG. 3B is composed of two pMISQp connected in parallel with each other and two nMISQn connected in series with each other. pM
The gate electrodes of ISQp and Qp are nMISQ
The input terminals IN and IN are electrically connected to the gate electrodes n and Qn, respectively, and are connected to the gate electrodes n and Qn. That is, it is a two-input NAND circuit. pMIS
The first electrodes of Qp and Qp are electrically connected to the power supply wiring 3VD1. Further, each substrate electrode of pMISQp and Qp is electrically connected to the power supply wiring 3VD2.
Further, each second electrode of pMISQp and Qp is electrically connected to each other, and is also electrically connected to the first electrode of one nMISQn. And the pMISQ
An output terminal OUT is drawn from a wiring connecting the second electrode of p and the first electrode of nMISQn. The second electrode of nMISQn and the first electrode of nMISQn below (FIG. 3) are electrically connected to each other. NM below it
The second electrode of ISQn is electrically connected to the power supply wiring 3VS1. Further, each substrate electrode of nMISQn, Qn is electrically connected to the power supply wiring 3VS2.

Next, FIG. 4 shows a specific example of the power supply generating circuit 6 of FIG. CT indicates a control terminal for controlling the operation of the power generation circuit 6. The control terminal CT is connected to the pMI through inverter circuits INV1 and INV2, respectively.
It is electrically connected to the gate electrodes of SQp1 and nMISQn1, and is also electrically connected to the gate electrodes of pMISQp2 and nMISQn2 without going through the inverter circuits INV1 and INV2. Thereby, pMIS
Qp1, Qp2 and nMIS Qn1, Qn2 can be completely turned on / off (the gate potential of each MISFET does not become an intermediate potential between the source and drain potentials). When the potential of the control terminal CT is at the reference potential (for example, 0 V), pMISQp2 and nMISQn2 are turned on, and VDD (for example, 1.5 V) and VSS (for example, 0 V) are supplied to the substrate electrode of the MISFET, respectively, by the power supply wiring 3V.
Applied through D1, 3VS1. On the other hand, when the potential of the power supply voltage VDD (for example, 1.5 V) is applied to the control terminal CT, pMISQ
p1 and nMISQn1 are turned on, and the MISFET
The power supply voltage VDDQ (for example, 3.0
V) and VSSQ (for example, -1.5 V) are connected to the power supply wiring 3 respectively.
Applied through VDDQ, 3VSSQ. The power supply circuit is configured using, for example, a plurality of basic cells 2.

Next, the structure of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

FIGS. 5 to 8 are plan views of main parts of the main surface of the semiconductor substrate 1s constituting the semiconductor chip 1. The second layers for the power supply voltages VDD and VSS constituted by the second wiring layer are shown in FIGS. Power supply wiring 3VDD2, one pair of 3VSS2 and power supply voltage VDBB,
Second-layer power supply wiring for VSBB (third and fourth power supply wiring) 3
The area for one pair of VDBB2 and 3VSBB2 is shown. FIGS. 5 to 8 are plan views of the same region of the same semiconductor integrated circuit device, but are shown separately for easy understanding of each layer. The horizontal direction in FIGS. 5 to 8 is the X direction, and the vertical direction is the Y direction. The symbols CHX and CHY indicate wiring pitch lines (that is, channels), and are not formed on an actual product. The wiring pitch line CH
The cross point between X and CHY is marked with a cross. That is, CHX indicates a channel in the X direction (first direction),
A wiring extending in the X direction is arranged on CHX. Also,
CHY indicates a channel in the Y direction, and a wiring extending in the Y direction is arranged. For example, a first-layer power supply line 3VDD1 for the power supply voltage VDD, a first-layer power supply line 3VSS1 for the power supply voltage VSS1, and a third-layer wiring (third-layer power supply line 3VDD3, 3VSS3 and signal wiring)
Are arranged in the channel in the X direction, and the second-layer wirings (second-layer power supply wirings 3VDD2, 3VSS2, 3VBB2, 3SBB2
And signal wiring) are arranged in the channel in the Y direction. The first layer wiring is also used as a wiring in the basic cell, and extends in the X direction and the Y direction to extend the MIS in the basic cell.
The FETs are electrically connected. Further, a connection hole is arranged at a cross mark at the intersection of CHX and CHY. The connection holes electrically connect the wiring layers and electrically connect the semiconductor substrate and the wiring layers.

Semiconductor substrate 1s constituting semiconductor chip 1
Is composed of, for example, a p-type silicon single crystal, and has, on its main surface, a plurality of basic cells 2 defined in, for example, a planar rectangular shape.
Are arranged side by side along the width direction (X direction; first direction). Although not shown in FIGS.
As shown by, the basic cells 2 are also arranged side by side in the longitudinal direction (Y direction; second direction). in this case,
The patterns in the other upper and lower (Y direction) basic cells 2 adjacent to the basic cell 2 in FIGS.
Are arranged so as to be symmetrical with respect to the pattern in the figure with the adjacent boundary line of each basic cell 2 as a boundary. Each basic cell 2 has, for example, an 18 × 3 pitch (DA (Design Automation)
The wiring pitch is about the same as in n).
One pitch is, for example, about 0.5 μm. Also,
Second layer power supply wiring 3VDD2, 3V for power supply voltage VDD, VSS
The pair of SS2 and the pair of the second-layer power supply wirings 3VDBB2 and 3VSBB2 for the power supply voltages VDBB and VSBB are arranged, for example, at a ratio of one pair at 150 pitches.

In each basic cell 2, for example, two types of MISFETs having different gate widths are arranged. That is,
The MISFET QA having a relatively large gate width and the MISFET QB having a relatively small gate width are arranged. Of these, MISFETs with relatively large gate widths
QA is, for example, two pMISQAp and two nM
It has ISQAn. The MISFET QB having a relatively small gate width is, for example, two pMISQBp
And two nMISQBn. The reason why the MISFET QB having a small gate width is arranged in one basic cell 2 is that if the MISFET QB having a small gate width is separately provided as a different basic cell, the wiring length becomes longer and a wiring delay problem occurs. When stacked,
This is because the longitudinal dimension of the basic cell 2 is increased, and the degree of freedom in circuit design can be improved by providing MISFETs QA and QB having different gate widths in the same basic cell 2. The MISFET QB having a small gate width is suitable for forming a circuit having a small driving force (cannot flow a large current) and a light load. M
ISFETs QA and QB are formed in n-type well NWL and P-type well PWL. The inside of the basic cell 2 is mainly
The first and third wirings are connected between the basic cells 2.
The logic is formed by being connected by the wiring of the layer. The basic cell 2 will be described later in detail.

On the main surface of the semiconductor substrate 1s, well power supply regions (first and second power supply lines) 7PWA, 7PWB and 7NW for the power supply wirings 3VD2 and 3VS2 are arranged in the width direction of the basic cell 2 (X direction: 1 direction).
The well power supply regions 7PWA, 7PWB, and 7NW correspond to wells NWL and PW (described later) at locations corresponding to the substrate electrodes.
An area for supplying a predetermined voltage to L. That is, the well power supply regions 7PWA and 7PWB function as the power supply wiring 3VS2 and are formed of a p-type semiconductor region electrically connected to the p-type well PWL. The well power supply region 7NW functions as the power supply wiring 3VD2,
It is composed of an n-type semiconductor region electrically connected to the n-type well NWL. Well power supply area 7PWA, 7PWB, 7
The NW is formed by introducing predetermined impurities into the wells NWL and PWL of the semiconductor substrate 1, and the impurity concentration is set higher than the well. That is,
The well power supply areas 7PWA, 7PWB, and 7NW are MIS
The source and drain regions of the FETs QA and QB are formed in the same process. Therefore, the well power supply region 7
The resistances of PWA, 7PWB, and 7NW are lower than the resistance of the well (hereinafter simply referred to as well resistance). Also, as described later, well power supply areas 7PWA, 7PWB, 7PWB
On the surface layer of the NW, a silicide layer such as tungsten silicide is formed, for example, and the resistance is further reduced, and the wiring resistance is reduced. As described above, at the time of standby or inspection, the power supply voltage VSBB is applied to the well power supply regions 7PWA and 7PWB located at the top and bottom of the plane in FIGS. 5 to 8, and the MISFETs QA and QB
The power supply voltage VDBB is applied to the well power supply region 7NW located between
Is applied.

The well power supply areas 7PWA, 7PWB and 7NW for the power supply wirings 3VD2 and 3VS2 are arranged for the following reasons. That is, as described above, in the semiconductor integrated circuit device of the first embodiment, the threshold voltage of the MISFET is reduced and the leakage current is increased due to the miniaturization of the MISFET constituting the device and an increase in the operating speed. , Substrate potential (well potential) during standby of a semiconductor integrated circuit device or during an inspection process (test)
Must be set so that nMIS is lower and pMIS is higher than during normal operation, and the substrate potential needs to be controlled independently of the normal power supply voltage. In the semiconductor integrated circuit device studied by the present inventor to carry out the present invention, the well power supply regions are not formed so as to extend in the X direction, but are arranged at intervals of a predetermined number of basic cells in the X direction. I have. In this structure, power is supplied to the well by the second-layer power supply wiring. However, since the well resistance is very high, on the order of kΩ, the power supply interval in the width direction of the basic cell is narrowed. Increase the number of wirings (in the above pitch, the number of second-layer power wirings for power supply voltage VDD and VSS is 8
One pair is required for the pitch, and the second layer power supply wiring for the power supply voltages VDBB and VSBB is required to be two pairs for every 50 pitches. Otherwise, the well potential becomes unstable, so that the number of signal wirings that can be arranged in the second wiring layer is reduced, and thereby high integration cannot be achieved.

Therefore, the second power supply voltages VDBB and VSBB
In the first embodiment, in order to reduce the number of layer power wirings,
Well power supply area 7PW for power supply wiring 3VD2, 3VS2
A, 7PWB, and 7NW are connected between the basic cells 2 adjacent in the horizontal direction (X direction) in FIGS. (In the same direction). Well power supply area 7PWA, 7P
Since the diffusion resistance of WB and 7NW is about two orders of magnitude lower than the resistance of the well, the arrangement interval of the second-layer power supply wiring for the well power supply is larger than that in the structure in which the well power supply region is scattered in the longitudinal direction of the basic cell. (In terms of pitch, the pair of power supply lines for power supply voltages VDD and VSS and the pair of second-layer power supply lines for power supply voltages VDBB and VSBB are both 150.
One pair per pitch). Therefore, the number of second-layer power supply wires for well power supply can be reduced. The usage rate of the second-layer power supply wiring for the power supply voltages VDBB and VSBB can be reduced to about 3%. Therefore, the number of signal wires that can be arranged in the second wiring layer can be increased. Considering the difference in resistance between the well resistance and the resistance of the well power supply region, the pair spacing of the second-layer power supply wires for the power supply voltages VDBB and VSBB can be considerably increased. The power supply lines for the voltages VDD and VSS are arranged in accordance with the interval between pairs of the second-layer power supply lines. In addition, power supply wiring 3VD2, 3VS
By forming the well power supply regions 7PWA, 7PWB, and 7NW for the second semiconductor region, the well power supply region 7PW is formed.
A, 7PWB, and 7NW over the first-layer wiring formation region (first
Channel of the third layer wiring) or the third layer wiring formation region (third layer).
(A channel of a layer wiring), and the degree of freedom of arrangement of the first layer signal wiring and the third layer signal wiring can be improved.

On the main surface of such a semiconductor substrate 1s,
As shown in FIGS. 6, 7, and 8, the power supply voltages VSS and Vs
DD first layer power supply wiring (first power supply wiring) 3VDD1 (3
VD1) and 3VSS1 (3VS1). The first-layer power supply wirings 3VDD1 and 3VSS1 are composed of a first-layer wiring layer and are made of, for example, aluminum, aluminum alloy, or copper, and have a wiring width of, for example, 0.25 μm.
The length is about m (minimum line width) and extends in the X direction. The first-layer power supply wiring 3VSS1 at the uppermost plane (the uppermost part in FIGS. 6, 7 and 8) of FIGS. 6, 7 and 8 is arranged along the well power supply region 7PWB so as to overlap with the plane. However, as shown in FIG. 7, a part of the first-layer power supply wiring 3VSS1 on the uppermost right end of the plane of FIG. This corresponds to a second-layer wiring and a well power supply region 7W described later.
This is to enable connection with the PB. Other first
The layer power supply lines 3VDD1 and 3VSS1 are
It extends in the X direction so as to cross each of the pMIS and the nMIS of the ISFET QA.

On the main surface of the semiconductor substrate 1s, the second layer power supply wiring 3V for the power supply voltages VDD and VSS is located above the first layer power supply wirings 3VDD1 and 3VSS1, as shown in FIG.
DD2, 3VSS2 and the second for power supply voltage VDBB, VSBB
Layer power lines 3VDBB2 and 3VSBB2 are formed. Second
Layer power wiring 3VDD2, 3VSS2, 3VDBB2, 3VSBB2
Is composed of a second layer of wiring, for example, aluminum,
It is made of aluminum alloy or copper, and its wiring width is, for example, the first layer power supply wiring 3VDD1, 3VSS1, 3VDDB1, 3
It is about the same as VSBB1. This second layer power supply wiring 3VDD2
, 3VSS2, 3VDBB2, and 3VSBB2 are formed to extend in the direction (Y direction) intersecting the extending direction (X direction) of the first-layer power supply wirings 3VDD1, 3VSS1, 3VDBB1, and 3VSBB1. Each second layer power supply wiring 3VDD2, 3VSS2, 3
VDBB2 and 3VSBB2 are arranged on the center line in the width direction of each basic cell 2. The second layer wiring 3VDD2 is connected to the connection hole TH.
Through the first layer power supply wiring 3VDD1. The second-layer power supply wiring 3VSS2 is electrically connected to each of the two first-layer power supply wirings 3VSS1 and 3VSS1 through the connection hole TH. The second-layer power supply wiring 3VSBB2 is electrically connected to the well power supply region 7NW for the power supply wiring 3VD2 through the connection hole TH.
Are electrically connected to the well power supply regions 7PWA and 7PWB for the two power supply wires 3VS2 through the connection holes TH. The basic cells 2 under the second-layer power supply wirings 3VSBB2 and 3VDDB2 include the switching cells SW1 and S2 described above.
Used as W2. 5 to 8 show only the switch cell SW2. Normally, the second power supply wiring 3VSBB2
, 3VDBB2 The basic cell 2 in the lower layer cannot be used as a cell constituting a logic circuit, and is wasted.
In the first embodiment, by using the basic cell 2 as the switching cells SW1 and SW2, the basic cell 2 can be effectively used.

Further, on the main surface of the semiconductor substrate 1s, the third-layer power supply wires 3VDD3 and 3VSS3 for the power supply voltages VSS and VDD are provided above the second-layer power supply wires 3VDD2 and 3VSS2.
(Second power supply wiring). The third-layer power lines 3VDD3 and 3VSS3 are connected to the first-layer power lines 3VDD1 and 3V, respectively.
It is a wiring that reinforces SS1 and is composed of a third wiring layer.
For example, it is made of aluminum, an aluminum alloy or copper, and its line width is about three times or more of the first-layer power supply wiring, that is, for example, about 0.75 μm or more. The thickness of the third-layer power supply wiring is the same as or greater than that of the first-layer power supply wiring. Therefore, the third-layer power supply wiring has a low wiring resistance, and can sufficiently reinforce the power supply of the first-layer power supply wirings 3VDD1 and 3VSS1. This third layer power wiring 3VDD33
VSS3 extends in the same direction (X direction) as the first-layer power supply wirings 3VDD1 and 3VSS1. 3rd layer power supply wiring 3VDD3
, 3VSS3 are electrically connected to the first-layer power supply wirings 3VDD1 and 3VSS1 via connection holes THa formed in each channel of the second wiring layer where no signal wiring is formed. In addition, the third-layer power lines 3VDD3 and 3VSS3 are connected to the second-layer power lines 3VDD2 and 3VSS2 respectively with connection holes THa.
May be electrically connected to each other. In the third wiring layer, no reinforcement is provided for providing power supply lines on the well power supply regions 7PWA, 7PWB, and 7NW for the power supply lines 3VD2 and 3VS2. It is the MIS in the basic cell
Since the well consumes less (less) current than the FET, it is sufficient to reinforce the second-layer power supply wirings 3VDD2 and 3VSS2. As a result, the channel of the signal wiring in the second wiring layer can be secured, and the degree of freedom in designing the arrangement of the signal wiring can be improved. This third layer power supply wiring will be described later in detail using a specific circuit example.

Next, the basic cell 2 according to the first embodiment will be described in detail. 9 and 10 show the basic cell 2
2 shows an enlarged plan view of FIG. FIGS. 11 to 13 are sectional views taken along lines AA, BB, and CC of FIG. 10, respectively. Although FIG. 10 shows one basic cell 2 at the same location of the same semiconductor integrated circuit device, the figures are shown separately for easy understanding of each layer.

A p-well PWLA,
PWLB and n-well NWL are formed. For example, boron (B) or boron difluoride (BF2) is introduced into the p-wells PWLA and PWLB in the same step, and n-well NWL is introduced, for example, phosphorus (P) or arsenic (As). Become. Although not particularly limited, a buried n-well DNW is formed under the p-wells PWLA and PWLB.
LA and DWLB are formed. Embedded n-well DNW
L is, for example, phosphorus or arsenic introduced. The p-wells PWLA, PWLB are the embedded n-wells DNWLA,
It is electrically isolated from the semiconductor substrate 1s by being surrounded by the DWLB and the side n-well NWL.

In such a semiconductor substrate 1s, a trench-type isolation portion (trench isolation) 8 is formed. The groove-shaped separation portion 8 is formed by embedding a separation insulating film 8b made of, for example, a silicon oxide film in a separation groove 8a dug in the thickness direction of the semiconductor substrate 1s.
The active region L is defined in a plan view. And the above p
The active region L formed in the well PWLB has nMIS
QBn is formed. Here, this p-well PWL
In region B, two nMISQs in one basic cell 2
In addition to Bn, two nMISQBn and QBn of another basic cell 2 arranged in the upper part of FIGS. 9 and 10 are arranged. That is, the p-well PWLB is a region shared by nMISQBn and QBn of the basic cell 2 adjacent in the Y direction. Thereby, the nMISQBn,
Compared with the case where the p-well PWLB is provided for each QBn, the dimension between the basic cells 2 and 2 adjacent in the Y direction in FIGS. 9 and 10 can be reduced. And the top and bottom (Y
NMI of different basic cells 2, 2 adjacent to each other
Between the SQBn and QBn, the above-described well power supply region 7PWB defined by the groove type separation portion 8 is arranged, from which a predetermined potential is supplied to the p-well PWLB, and the different basic cells 2 and 2 Both nMISQBn, Q
The structure is such that the threshold voltage of Bn is adjusted. For example, boron or 2
Boron fluoride has been introduced. Since the well power supply region 7PWB for the power supply wiring 3VS2 is arranged at the center of the p well PWLB, the stability of the substrate potential of the p well PWLB can be improved.

In the active region L formed in the n-well NWL region, the pMISQB
p and QAp are formed. That is, n-well NW
L is an area shared by pMISQBp having a small gate width and pMISQAp having a large gate width. Thereby, the n-well NWL is provided for each of the pMISQBp and QAp.
Can be reduced in size in the Y direction of the basic cell 2 as compared with the case of providing. Then, both pMISQ
Between the adjacent Bp and QAp, the above-described well power supply region 7NW defined by the groove-shaped separation portion 8 is arranged, from which a predetermined potential is supplied to the n-well NWL, and The structure is such that the threshold voltages of both pMISQBp and QAp are adjusted. For example, phosphorus or arsenic is introduced into the well power supply region 7NW.

Further, nMISQAn is formed in the active region L formed in the p well PWLA.
Here, in addition to the two nMISs QAn and QAn in one basic cell 2, the region of the p-well
Also, two nMISs QAn and QAn of another basic cell 2 arranged in the lower stage of FIG. 10 are arranged. That is, the p-well PWLA is nM
This area is shared by ISQAn and QAn. As a result, the p-well PWL is provided for each of the nMISs QAn and QAn.
Compared with the case where B is provided, the dimension between the basic cells 2 and 2 adjacent in the Y direction in FIGS. 9 and 10 can be reduced. The above-described well power supply region 7PWA defined by the groove-shaped separation portion 8 is disposed between adjacent nMISs QAn and QAn of the different basic cells 2 and 2 adjacent to each other in the vertical direction (Y direction). From here p-well PW
A predetermined potential is supplied to the LA, and the threshold voltages of the nMISs QAn and QAn of the different basic cells 2 are adjusted. The well power supply area 7PWA includes:
For example, boron or boron difluoride has been introduced.
As described above, the power supply wiring 3V is connected to the center of the p-well PWLA.
Since the well power supply area 7PWA for S2 is arranged,
The stability of the substrate potential of the p-well PWLA can be improved.

The nMISQBn and pMISQBp having a small gate width are formed by the semiconductor regions 9Ba, 9Bb, 10Ba, and 10Bb for source and drain, and the semiconductor substrate 1
Has a gate insulating film 11i formed on the main surface of the substrate and a gate electrode 12Bg formed thereon. nMI
The semiconductor regions 9Ba and 9Bb of SQBn are p-well PW
For example, phosphorus or arsenic is introduced into the LB region. The central semiconductor region 9Bb is a region shared by the two nMISQBn. The semiconductor region of pMISQBp is formed by introducing, for example, boron or boron difluoride (BF ₂ ) into the region of the n-well NWL. Also in this case, the central semiconductor region 10Bb is a region shared by the two pMISQBp. Semiconductor regions 9Ba, 9Bb,
10Ba, 10Bb and well power supply area 7PWB, 7
In the upper part of NW and 7PWA (the surface layer of the semiconductor substrate 1s),
For example, a silicide layer 13 made of tungsten silicide (WSi) or the like is formed. Thereby, the contact resistance between the semiconductor regions 9Ba, 9Bb, 10Ba, 10Bb and the wiring can be reduced, so that the operation speed of the semiconductor integrated circuit device can be improved. Further, the wiring resistance as the power supply wirings 3VD2 and 3VS2 can be reduced, the resistance of the wells NWL, PWL, and PWLB can be reduced, and the stability of the substrate potential can be improved.

The gate insulating film 11i is made of, for example, a silicon oxide film. Further, the gate insulating film 11i may be formed by an oxynitride film (SiON film). Thus, the generation of interface states in the gate insulating film 11i can be suppressed, and at the same time, electron traps in the gate insulating film 11i can be reduced, so that the hot carrier resistance in the gate insulating film 11i is improved. It is possible to do. Therefore, nMIS and pMIS
Can be improved in operation reliability.

The gate electrode 12Bg is formed of, for example, a metal such as tungsten (W) on an n-type low-resistance polysilicon film via a barrier metal film such as titanium nitride (TiN) or tungsten nitride (WN). The films are formed by being sequentially deposited from the lower layer (a so-called polymetal structure). The barrier metal film is a film for preventing silicide from being formed at a contact portion by a heat treatment during a manufacturing process when a tungsten film is directly stacked on a low-resistance polysilicon film. By providing a metal film on part of the gate electrode 12Bg, the resistance of the gate electrode can be reduced, and the operation speed of the semiconductor integrated circuit device can be improved. However, the gate electrode 12Bg
Is not limited to a polymetal structure. For example, it can be formed of a single film of low-resistance polysilicon,
A so-called polycide structure, which is formed by depositing a silicide film such as tungsten silicide on a low resistance polysilicon film, can also be used. Gate electrode 12Bg
Has a gate length of, for example, about 0.14 μm, and a gate width of, for example, about 0.30 μm.

These gate electrodes 12Bg are made of nMIS.
On the boundary region between QBn and pMISQBp (on the separation part), they are integrally connected as a wide pattern 12Bg1. FIGS. 14 and 15 are diagrams for explaining the reason for such an integral structure. 14A and 14B are diagrams illustrating the first embodiment, in which FIG. 14A is a circuit diagram illustrating an inverter circuit INV as an example, and FIG. 14B is a layout diagram of FIG. FIG. 15 is a layout diagram in the case where the gate electrodes 50 and 50 are separated for comparison. In FIG.
A connection hole 54 connecting the input signal wiring 53 and the gate electrode 50 must be arranged on a straight line connecting the semiconductor region 51 of ISQBp and the semiconductor region 52 of nMISQBn. The signal wiring 55 for output must be bypassed.
However, there is a problem that the area occupied by the basic cell 2 is increased because it protrudes from the region of the basic cell 2. On the other hand, in the first embodiment, as shown in FIG. 14B, the degree of freedom of the arrangement position of the connection hole CONT connecting the input first-layer signal wiring 3S1a and the gate electrode 12Bg1 is limited. High, pMI
The connection hole TH can be arranged in a region other than on a straight line connecting the semiconductor region 10Ba of SQBp and the semiconductor region 9Ba of nMISQBn. can do. Therefore, the area occupied by the basic cell 2 can be reduced.

On the other hand, in FIGS. 9, 10 and 13, the nMISQAn and pMI
SQAp is a semiconductor region 9Aa for source and drain,
9Ab, 10Aa, and 10Ab, a gate insulating film 11i formed on the main surface of the semiconductor substrate 1s, and a gate electrode 12Ag formed thereon. nMISQA
In the n semiconductor regions 9Aa and 9Ab, for example, phosphorus or arsenic is introduced into the region of the p well PWLA, and the central semiconductor region 9Ab is a region shared by the two nMISQAns. Further, the semiconductor regions 10Aa and 10Ab of pMISQAp are formed by introducing, for example, boron or boron difluoride (BF ₂ ) into the region of the n-well NWL.
This area is shared by ISQAp. Semiconductor region 9A
a, 9Ab, 10Aa, and 10Ab (semiconductor substrate 1
nMISQBn and pMISQ
Similarly to Bp, a silicide layer 13 made of, for example, tungsten silicide is formed. Thereby, the contact resistance between the semiconductor regions 9Aa, 9Ab, 10Aa, 10Ab and the wiring can be reduced, so that the operation speed of the semiconductor integrated circuit device can be improved. For the materials of the gate insulating film 11i and the gate electrode 12Ag, the nMISQBn and pMISQ described above are used.
The description is omitted because it is the same as Bp. However, nMISQ
The gate electrodes 12Ag of each of An, QAn and pMISQAp, Qap are separated in a plane (that is, formed separately). This nMIS
The gate length of the gate electrode 12Ag of QAn and pMISQAp is, for example, about 0.14 μm, and the gate width is, for example, 1.
It is about 8 μm. Note that reference numeral 14a in FIGS.
Indicates an interlayer insulating film and is made of, for example, a silicon oxide film.

Next, a specific example of a basic logic circuit formed using such a basic cell 2 is shown in FIG.
FIG. 16A shows a logic circuit diagram, and FIG. 16B shows a layout plan view thereof. As shown in FIG. 16A, the input IN1 is electrically connected to the input of the NAND circuit N,
The input IN2 is connected to a NAND through an inverter circuit INV.
It is electrically connected to the input of the circuit N. This inverter circuit INV has the nMISQ having a small gate width as described above.
Bn and pMISQBp. Further, the NAND circuit N has the above-mentioned nM having a large gate width.
It is composed of ISQAn and pMISQAp. Thus, the inverter circuit INV and the two-input NA
Since the ND circuit N can be configured by one basic cell 2, the cell area can be reduced, and the delay can be reduced by reducing the input capacitance of the terminal IN2.

As shown in FIG. 16B, the upper first
The layer power supply wiring 3VSS1 is connected to the nMIS through the connection hole CONT.
It is electrically connected to the semiconductor region 9Ba of QBn.
The common semiconductor region 9Bb of nMISQBn is
It is electrically connected to the first layer signal wiring 3S1c through NT. This first layer signal wiring 3S1c is formed of pMISQBp
Semiconductor region 10Ba and pMIS having a large gate width
It is also electrically connected to the gate electrode 12Ag of QAp. The shared semiconductor region 10Bb of pMISQBp is electrically connected to the first layer signal wiring 3S1d through the connection hole CONT. The first layer power supply wiring 3VDD1 is connected to the connection hole CON.
Through T, it is electrically connected to the semiconductor region 10Aa of pMISQAp having a large gate width. This pMISQ
The semiconductor region 10Ab shared by Ap is the first-layer signal wiring 3S.
It is electrically connected to the semiconductor region 9Aa of nMISQAn through 1e. The gate electrode 12Ag of this pMISQAp is connected to the nMIS through the first-layer signal wiring 3S1f.
It is electrically connected to the gate electrode 12Ag of QAn. The first layer power supply line 3VSS1 is connected to the semiconductor region 9 of nMISQAn having a large gate width through the connection hole CONT.
It is electrically connected to Aa.

Next, FIG. 17 shows a state in which a logic circuit formed in a predetermined basic cell 2 and a logic circuit formed in another predetermined basic cell 2 are electrically connected through a signal wiring 3S. I have. MISFETQ schematically shows the MISFETs at the output and input of each logic circuit. 3S2 is the second layer signal wiring, 3S1 crossing it,
3S3 indicates a first layer signal wiring and a third layer signal wiring, respectively. Here, CHXA is a wiring pitch line (channel) for arranging the wiring for the power supply voltage VSBB, but in the first embodiment, the wiring pitch line (channel) Channel) CHXA, the first layer signal wiring 3S which is a part of the signal wiring 3S.
The first or third layer signal wiring 3S3 can be arranged. The crosses indicate connection holes for electrically connecting different wiring layers.

Next, a specific example of the power supply reinforcing technique of the semiconductor integrated circuit device of the present invention and the specific example of FIG. 17 will be described with reference to FIGS.
Explanation will be made using 0. Although FIG. 18 is a plan view, the same hatching is applied to the same layer for easy understanding of the drawing. FIGS. 19 and 20 show AA of FIG.
It is sectional drawing of a line and a BB line. Further, the second layer wiring is in the extending direction (X direction) of the first layer wiring and the third layer wiring.
Are extended in a direction (Y direction) intersecting with.

FIG. 18 illustrates the layout plane of FIG. 16A as an example. The gate electrodes 12Ag of pMISQAp and nMISQAn are electrically connected to the second-layer signal wiring (the signal wiring of the third wiring layer) 3S2a through the first-layer signal wiring 3S1g and the connection hole TH1. The other end of the second layer signal wiring 3S2a is connected to a connection hole T
PMISQBp with relatively small gate width via H1
And nMISQBn and is electrically connected to the first-layer signal wiring 3S1b for output of the inverter circuit INV. Shared semiconductor region 10 of pMISQAp
Ab is electrically connected to the first-layer signal wiring 3S1h through the connection hole CONT, and further electrically connected to the second-layer signal wiring (signal wiring of the third wiring layer) 3S2b through the connection hole TH1. The other end of the second layer signal wiring 3S2b is
It is electrically connected to the third layer signal wiring 3S3 through the connection hole TH2. The third layer signal wiring 3S3 is connected to the p-well supply region 7PW for supplying the power supply voltage VSBB as described above.
A is located immediately above A. The third layer signal wiring 3S3
Is connected to the other second layer signal wiring 3 through the connection hole TH2.
It is electrically connected to S2c. Since there is an empty space in the second wiring layer below the third-layer signal wiring 3S3,
A second-layer signal wiring 3S2 crossing the channel direction of the third-layer signal wiring 3S23 is arranged.

First-layer power supply wiring 3V for supplying power supply voltage VDD
DD1 and first-layer power supply wiring 3VSS for supplying power supply voltage VSS
1 extends on pMISQAp and nMISQAn in a direction (X direction) intersecting the extending direction (Y direction) of each gate electrode 12Ag. The first layer power supply wiring 3VDD1 is electrically connected to the shared semiconductor regions 10Ab and 10Ba of pMISQAp and pMISQBp through the connection hole CONT. The first-layer power supply wiring 3VSS1 is connected to the connection hole CONT.
Through the semiconductor region 9Aa of nMISQAn.

Immediately above the first-layer power supply wirings 3VDD1 and 3VSS1, the first-layer power supply wirings 3VDD1 and 3VSS are overlapped with the first-layer power supply wirings 3VDD1 and 3VSS1 in plan view.
Third-layer power supply wirings (second power supply wirings) 3VDD3 and 3VSS3 are arranged in parallel with SS1. The third-layer power supply wirings 3VDD3 and 3VSS3 are wirings that reinforce the power supply in the horizontal direction in FIG. 18 (that is, the power supply to the basic cell 2 or the basic logic circuit adjacent in the X direction). It is made of aluminum alloy or copper, and its width is, for example, about three times or more of the first-layer power supply wiring,
That is, it is about 0.75 μm or more. The thickness of the third-layer power supply wiring is equal to or greater than that of the first-layer power supply wiring. Therefore, the third-layer power lines 3VDD3 and 3VSS3 have lower resistance than the first-layer power lines 3VDD1 and 3VSS1. The third-layer power supply wirings 3VDD3 and 3VSS3 are connected to the connection holes TH.
19, only the second-layer power supply line 3VSS2 immediately below the third-layer power supply lines 3VDD3 and 3VSS3 (here, only the second-layer power supply line 3VSS2 shown in FIG. 19 is shown. Also has a second layer power supply wiring)
And further electrically connected to the first-layer power supply wirings 3VDD1 and 3VSS1 through the connection holes TH1. In this case, the connection hole TH2 and the second layer power supply wiring thereunder are:
The second layer signal wiring (the signal wiring of the third wiring layer) 3S2 in the second wiring layer is arranged so as not to block the arrangement. As will be described later, the connection hole TH2 and the second-layer power supply wiring are arranged in a region where the second-layer signal wiring 3S2 is not arranged (an empty channel of the second-layer wiring). Note that FIG.
Reference numerals 14b and 14c in FIG. 20 denote interlayer insulating films. The interlayer insulating films 14b and 14c are made of, for example, a silicon oxide film. In FIG. 19, the power supply voltage V
Although only the cross-sectional structure of the power supply wiring connection on the SS side is shown, the connection cross-sectional structure between the third-layer power supply wiring 3VDD3 and the first-layer power supply wiring 3VDD1 on the power supply voltage VDD side is the same.

Such third-layer power supply wirings 3VDD3, 3VSS
3 may be parallel to the first-layer power lines 3VDD1, 3VSS1, and is not necessarily the first-layer power lines 3VDD1, 3VSS1.
It is not necessary to dispose it immediately above so that it overlaps the plane. This is shown in FIG. 21 and FIG. In FIG. 21, pMISQBp and nMISQBn in FIG. 18 are omitted because they are the same as in FIG.
FIG. 22 is a sectional view taken along line BB of FIG. The cross section taken along the line AA in FIG. 21 is the same as that in FIG.

Here, the third-layer power supply wirings 3VDD3, 3VSS
3 are arranged in parallel with each other in a plane with respect to the first-layer power supply wirings 3VDD1 and 3VSS1 by one pitch (in a direction approaching each other) in a plane-parallel manner. Then, the third layer power lines 3VDD3, 3VSS3 and the first layer power lines 3VDD1, 3V
SS1 is electrically connected through the second-layer power supply lines 3VDD2 and 3VSS2. That is, it has the following structure. The third-layer power lines 3VDD3 and 3VSS3 are connected to one ends of the second-layer power lines 3VDD2 and 3VSS2 through the connection holes TH2. This second layer power supply wiring 3VDD2,3V
The other end of SS2 is partially connected to the first layer power supply wiring 3VDD1, 3V.
It extends so as to planarly overlap with SS1 (Y direction in FIG. 21,
22 (left direction in FIG. 22), the first-layer power supply wirings 3VDD1, 3VSS through the connection holes TH1 in the plane overlapping areas.
Electrically connected to 1. 3rd layer power supply wiring 3VDD3,
As a method of shifting 3VSS3, it may be shifted by 1/2 wiring pitch. Also, the first layer power supply wirings 3VDD1, 3VSS
1 (the direction in which the third-layer power lines 3VDD3 and 3VSS3 are separated from each other), and the third-layer power lines 3VDD3 and 3VSS3 can be translated in the same direction.

In the semiconductor integrated circuit device according to the first embodiment, the power supply is reinforced by the third-layer power supply lines 3VDD3 and 3VSS3 having a lower resistance than the first-layer power supply lines 3VDD1 and 3VSS1, whereby the second-layer power supply lines are provided. Even if the interval between 3VDD2 and 3VSS2 is widened, a direct current (DC) power supply voltage drop can be suppressed, and a local alternating current (AC) drop can also be greatly reduced. Further, since the power supply voltage is stabilized, gate delay can be reduced. FIGS. 23 and 24 show the change in power supply voltage and the inverter delay (gate delay) when the inverter (inter-buffer buffer) is operated, with and without the power supply reinforcement (FIG. 23) and without (FIG. 24), respectively.
It is shown. In the semiconductor integrated circuit device according to the first embodiment, the AC power supply drop ΔVDD can be reduced by about 90%, and the gate delay Tpd is reduced by about 1%.
It can be reduced by about 0%. Therefore, the power supply (AC) caused by the current flowing through the cell when the cell operates
Malfunction of the semiconductor integrated circuit device due to noise can be prevented. Further, since the gate delay Tpd can be reduced, the maximum operating frequency of the semiconductor integrated circuit device can be improved, and the operation speed of the semiconductor integrated circuit device can be improved. In addition, resistance to electromigration can be significantly improved by power supply reinforcement. Therefore, it is possible to improve the yield and reliability of the semiconductor integrated circuit device.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.
It will be explained by.

First, as shown in FIG. 25, after designing a logic function to be mounted on a semiconductor integrated circuit device and creating a logic circuit diagram (step 100), automatic placement using a computer is performed based on the logic circuit diagram. The wiring system (DA) automatically arranges and connects the logic circuits (step 10).
1). In this automatic placement and routing system, first, based on the logic circuit diagram, connection information (net file) that can be handled by the automatic placement and routing system is created, and the connection information is input to the automatic placement and routing system (step 101A). The base data of the automatic placement and routing system has information in which patterns of basic cells 2 on a semiconductor integrated circuit device that are virtually represented are arranged. FIG. 26 schematically shows this stage.

In FIG. 26, a plurality of basic cells 2 are laid out in the vertical and horizontal directions. Then, the first-layer power lines 3VDD1, 3VSS1 and the third-layer power lines 3VDD3, 3
VSS3 is arranged in each row of the plurality of basic cells 2 so as to extend in the X direction (the width direction of the basic cells 2) so as to cross the plurality of basic cells 2 on the row. 1st layer power supply wiring 3V
DD1, 3VSS1 and third-layer power supply wirings 3VDD3, 3VSS3 are arranged on the same channel so as to overlap in a plane. However, as described above, they may be arranged so as to be shifted so that they do not overlap with each other. At this stage, the third-layer power lines 3VDD3 and 3VSS3 and the first-layer power lines 3VDD1 and 3VSS
No connection hole connecting 1 is provided. In FIG. 26, the row of the second-stage basic cell 2 illustrates a region used as a wiring region. Therefore, no power supply wiring is arranged in that region.

Next, based on the connection information input to the automatic placement and routing system, the designed logic circuit is automatically placed (step 101B). Automatic placement of logic circuits is performed by automatically placing modules (logic function patterns) stored in an automatic placement and routing system along a basic cell pattern. As a result, the first-layer power supply wirings 3VDD1, 3VSS are added to the column including the basic cells 2 to be connected.
1 and third-layer power supply wirings 3VDD3 and 3VSS3 are arranged. Subsequently, based on the connection information, the automatically arranged logic circuits (modules) are automatically connected to complete the logic circuit information (step 101C). At this time, in the first embodiment, first, a first-layer wiring, a second-layer wiring, a third-layer wiring, and a connection hole for connecting these are arranged on a wiring pitch line (channel) CH shown in FIG. . As a result, the inside of the basic cell 2 and between the basic cells 2 are connected to form a logic circuit. FIG. 27 schematically shows the state after this step. FIG. 27 shows a logic circuit (shown by hatching), a first-layer signal wiring (not shown), a second-layer signal wiring 3S2, a third-layer signal wiring 3S3, and their second and third signal wirings. Are shown after the step of arranging the connection holes TH2 for electrically connecting. In this case, the first-layer signal wiring and the third-layer signal wiring 3S3 may be handled as one cell on the DA as a cell. Although not particularly limited, the first-layer power supply wires 3VSS1, 3VDD1 and the third-layer power supply wires 3VSS3, 3VDD3 extend from one end of the semiconductor chip to the other.

Thereafter, a connection hole for connecting the third-layer power supply wiring to the first-layer power supply wiring is arranged in an empty channel having no second-layer wiring. This is schematically shown in FIG. FIG. 28 shows third-layer power supply wirings 3VDD3 and 3VSS3.
After the step of arranging the connection holes TH for the power supply voltage connecting the power supply wirings 3VDD1 and 3VSS1 to the first layer power supply wirings 3VDD1 and 3VSS1 is shown. The connection hole TH for the power supply voltage is arranged in an empty channel where the second-layer signal wiring 3S2 is not arranged in the second wiring layer. Therefore, the connection hole TH is connected to the second layer signal wiring 3S2.
Can be arranged so as not to be restricted. That is, it is possible to improve the degree of freedom in the arrangement of the signal wiring. Also,
The connection holes TH are not fixed, but are dispersed in the semiconductor chip and are arranged substantially uniformly. Therefore, the power supply voltage can be reinforced almost uniformly in the semiconductor chip. Therefore, the operation stability of the semiconductor integrated circuit device can be improved. In FIG. 28, the connection holes TH are arranged in all the empty channel regions, but it is not necessary to arrange them in all of them.

Next, the logic circuit information completed by the automatic placement and routing system is converted into mask creation data based on the design rules in the automatic placement and routing system (step 101D). Step 1 of inputting the above connection information
Step 10 for converting from 01A to this mask making data
Up to 1D is automatically processed by the automatic placement and routing system. Thereafter, based on the mask creation data, a connection mask is formed by, for example, an electron beam (EB) drawing apparatus (step 102). Subsequently, a device process is performed using a connection mask (Step 10).
3) A semiconductor integrated circuit device having a predetermined logic function is completed (Step 104).

FIG. 29 is a diagram showing a technique studied by the present inventor for carrying out the present invention. In this technique, the first layer power supply wirings 60VDD1, 60VSS1 and the third layer power supply wiring 60VDD3,
, 60VSS3 are already arranged before the second-layer signal wiring 60S2 is arranged.
Further, the plane position of the connection hole 61TH is also predetermined, and is substantially at the center of the semiconductor chip. Further, the basic cell 62a at the position where the connection hole 61TH is arranged is not used. In the case of this technology, the second layer signal wiring 6
Before arranging 0S2, the connection hole 61TH is arranged. Therefore, when arranging the second-layer signal wiring 60S2,
It must be arranged avoiding the connection hole 61TH.
That is, as shown in the center of FIG. 28, after the second-layer signal wiring 60S2 is connected to the first-layer signal wiring 60S1,
The connection is made to the layer signal wiring 60S2, further to the first layer signal wiring 60S1, and then to the second layer signal wiring 60S2 again.

Therefore, in the first embodiment, after arranging the second-layer signal wiring 3S2, the first-layer power supply wiring 3VDD1,3
A connection hole TH for connecting VSS1 to the third-layer power supply wirings 3VDD3 and 3VSS3 is arranged. Thereby, the second layer signal wiring 3
The path of S2 can be facilitated without complicating it, and the increase in size due to the complicated wiring path can be suppressed.

FIGS. 30 and 31 show the power supply line length ML of the first-layer power supply line having no free channel in the second wiring layer.
FIG. 1 in 40 pitches even after placement and routing
It can be seen that the power supply voltage connection holes TH can be arranged in the individual components, and that the power supply can be reinforced by the third-layer power supply wires 3VDD3 and 3VSS3. In addition, even after the placement and routing, the empty channels of the second wiring layer exist almost uniformly in the semiconductor chip, and the arrangement positions of the connection holes TH for the power supply voltage are not fixed but dispersed and exist uniformly in the semiconductor chip. , First
The third layer power lines 3VDD3, 3VDD3
With 3VSS3, it can be reinforced sufficiently and almost evenly.

(Embodiment 2) FIG. 32 is a plan view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.
3 is a sectional view taken along line AA of FIG.

In the second embodiment, as shown in FIGS. 32 and 33, well power supply regions 7PWA, 7N
The power supply lines 3VSBBL and 3V are connected in parallel to W and 7PWB and in contact with the upper surface thereof (electrically connected state).
DBBL is formed. This power supply wiring 3VSBBL, 3VDB
BL can be formed by etching the deposited conductor film using a normal photolithography technique before forming the interlayer insulating film 14a. Also, the well power supply region 7
After forming a photoresist film so that only PWA, 7NW and 7PWB are exposed, a tungsten film or the like is deposited,
Further, it can be formed also by using a lift-off method of forming a wiring by removing the photoresist film. Further, the following can be performed. First, after forming the interlayer insulating film 14a, the well power supply region 7 is formed on the interlayer insulating film 14a.
A groove is formed so that PWA, 7NW, and 7PWB are exposed. Subsequently, after a tungsten film or the like is deposited in the trench and on the interlayer insulating film 14a, it is subjected to CMP (Chemical
Etching back is performed by the mechanical polishing method to form power supply wirings 3VSBBL and 3VDBBL in the trench. After that, an insulating film is deposited on the interlayer insulating film 14a. Structures other than this, such as reinforcing the first-layer power supply lines VDD1 and VSS1 with the third-layer power supply lines, are the same as those in the first embodiment, and will not be described.

The power supply lines 3VSBBL and 3VDBBL are made of a high melting point metal such as tungsten. Therefore, in the second embodiment, the well power supply region 7PW
A, 7NW, and 7PWB can be further reduced in resistance.
B, the pair spacing of the second-layer power supply wiring for VSBB can be further widened, and the number of power supply wirings in the second wiring layer can be reduced.

(Embodiment 3) FIG. 34 is a plan view of a principal part of a semiconductor integrated circuit device according to still another embodiment of the present invention, and FIG. 35 is a sectional view taken along line AA of FIG.

In the third embodiment, as shown in FIG. 34 and FIG.
It is composed of only ISFET QA. Then, similarly to the second embodiment, the well power supply regions 7PWA, 7N
Power supply wirings 3VSBBL and 3VDBBL are formed in parallel with W and 7PWB and in contact with the upper surfaces thereof. The power supply wirings 3VSBBL and 3VDBBL are formed, for example, in a first wiring layer. Note that the power supply lines 3VSBBL and 3VDBBL may be formed in the same manner as in the second embodiment. The other structure, for example, the first-layer power supply lines VDD1 and VSS1 are reinforced by the third-layer power supply lines is the same as that of the first embodiment, and the description is omitted.

In the third embodiment, the same effects as in the first and second embodiments can be obtained.

(Embodiment 4) FIG. 36 is a plan view of a principal part of a semiconductor integrated circuit device according to still another embodiment of the present invention, and FIG. 37 is a sectional view taken along line AA of FIG.

In the fourth embodiment, the power supply wiring 3VSBBL,
The difference from the third embodiment is that VDBBL is formed in the first wiring layer.

In the fourth embodiment, as shown in FIGS. 36 and 37, the basic cell 2 is formed only of the MISFET QA having a large gate width similarly to the third embodiment, and the well power supply regions 7PWA, 7NW, The power supply wirings 3VSBBL and 3VDBBL formed in parallel with the 7PWB are formed, for example, in the first wiring layer. The power supply wires 3VSBBL and 3VDBBL are connected to the well power supply regions 7PWA and 7N through connection holes 15 formed in the interlayer insulating film 14a.
W, 7PWB are directly contacted and electrically connected.
That is, the well power supply areas 7PWA, 7NW, 7PWB
The power supply wiring 3VSBB formed in the first wiring layer
A predetermined power supply voltage is supplied through L and 3VDBBL. The first-layer wiring is made of a low-resistance material such as aluminum, an aluminum alloy, copper, or a copper alloy, as described in the first embodiment.
Structures other than this, such as reinforcing the first-layer power supply lines VDD1 and VSS1 with the third-layer power supply lines, are the same as those in the first embodiment, and will not be described.

In the fourth embodiment, the same effects as in the first, second, and third embodiments can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say,

For example, in the first to third embodiments,
The case where the first-layer power supply wiring is reinforced by the third-layer power supply wiring has been described. However, the present invention is not limited to this. The power supply reinforcement may be performed in the same wiring direction. It can be reinforced with five-layer power wiring. Also,
Reinforcing the second layer power wiring with the fourth layer power wiring,
The layer power supply wiring can be reinforced by the fifth layer power supply wiring.
The second-layer and fourth-layer power supply wirings are configured to extend in, for example, the Y direction, and the third-layer and fifth-layer power supply wirings are configured to extend in the X direction intersecting the same.

In the first to third embodiments,
Although the structure has been described in which the external terminals of the semiconductor chip are led out through the bonding wires, the present invention is not limited to this. For example, the structure may be such that the external terminals of the semiconductor chip are drawn out through bump electrodes (so-called bump electrodes).

Although the description has been made using the gate array as the ASIC, an ASIC or a DRAM (Dyna) having a macro cell adopting the gate array system such as a cell-based IC.
micRandom Access Memory), SRAM (Static Random)
Of course, it can be applied to logic with memory such as Access Memory.

In the above description, the invention made mainly by the present inventor has been described based on the field of application of MIS,
The case where the present invention is applied to a semiconductor integrated circuit device technology having an FET has been described. However, the present invention is not limited thereto.
For example, the present invention can be applied to a semiconductor integrated circuit device technology having another semiconductor integrated circuit element such as a bipolar transistor. Of course, DRAM or flash memory (E
EPROM (Electrically Erasable Programmable RO
M)) etc. can be applied to semiconductor memory products.

[0086]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1). According to the present invention, after arranging a wiring in a channel and forming a logic circuit, a vacant channel is provided with a connection hole for power supply reinforcement for electrically connecting different wiring layers, thereby forming a logic circuit. The arrangement of the wiring is not limited by the connection hole for power supply reinforcement, and the power supply wiring of different wiring layers can be efficiently reinforced.

(2) According to the present invention, after wiring is arranged in a channel and a logic circuit is formed, a connection hole for power supply reinforcement for electrically connecting different wiring layers is arranged in an empty channel. Accordingly, since the connection holes are not fixed, it is possible to substantially evenly reinforce the power supply within the main surface of the semiconductor substrate.

(3) According to the present invention, a power supply connection hole for electrically connecting the first power supply wiring and the second power supply wiring after arranging the signal wiring of the third wiring layer. Is arranged, the arrangement of the signal wiring is not limited by the connection hole, and the first power supply wiring can be efficiently reinforced by the second power supply wiring.

(4) According to the present invention, the DC power supply voltage drop can be suppressed by making the sectional area of the second power supply wiring larger than that of the first power supply wiring. Also,
Local AC drop can also be greatly reduced. For this reason,
Since the power supply voltage can be stabilized, the delay time of the logic circuit can be reduced.

(5) According to the present invention, since the silicide layer is provided on the surface of the power supply region, the resistance of the power supply region can be reduced. The number of wirings for supplying the substrate potential to be supplied can be reduced, and accordingly, the number of channels on which signal wirings can be arranged can be increased.

(6) According to the present invention, by providing the metal film on the power supply region, the resistance of the power supply region can be further reduced. The number of wirings for supplying the substrate potential to be supplied can be reduced, and accordingly, the number of channels on which signal wirings can be arranged can be increased.

(7) According to the present invention, a plurality of p-channel field effect transistors and a plurality of n
The respective gate electrodes of the channel-type field-effect transistors are formed integrally with the wide pattern and electrically connected to each other, so that when the wiring in the basic cell is arranged, the wiring protrudes from the area of the basic cell. Can be placed without
It is possible to suppress an increase in the basic cell size due to the wiring in the basic cell.

(8) According to the present invention, each of two types of field effect transistors having different gate widths in the basic cell has the same channel conductivity type field effect transistor adjacent to each other in plan view, and the same Since the semiconductor region and the power supply region to the semiconductor region can be shared, the basic cell size can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are plan views of a semiconductor chip constituting a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a main part of the semiconductor integrated circuit device of FIG. 1;

FIGS. 3A and 3B are circuit diagrams of basic logic circuits formed in the semiconductor integrated circuit device of FIG. 1;

FIG. 4 is a circuit diagram of a power supply generation circuit of the semiconductor integrated circuit device of FIG. 1;

FIG. 5 is an enlarged plan view of a main part of the semiconductor integrated circuit device of FIG. 1;

FIG. 6 is an enlarged plan view of a main part of the semiconductor integrated circuit device of FIG. 1;

FIG. 7 is an enlarged plan view of a main part of the semiconductor integrated circuit device of FIG. 1;

FIG. 8 is an enlarged plan view of a main part of the semiconductor integrated circuit device of FIG. 1;

9 is an enlarged plan view of a basic cell of the semiconductor integrated circuit device of FIG.

FIG. 10 is an enlarged plan view of a basic cell of the semiconductor integrated circuit device of FIG. 1;

FIG. 11 is a sectional view taken along line AA of FIG. 10;

FIG. 12 is a sectional view taken along line BB of FIG. 10;

FIG. 13 is a sectional view taken along line CC of FIG. 10;

14A is a logic circuit diagram of the semiconductor integrated circuit device of FIG. 1, and FIG. 14B is a plan view showing the element arrangement of FIG.

FIG. 15 is a plan view showing a device arrangement for comparison with FIG. 14, which is a technique that the present inventor has compared with the present invention.

16A is a logic circuit diagram of the semiconductor integrated circuit device of FIG. 1, and FIG. 16B is a plan view showing the element arrangement of FIG.

FIG. 17 is a plan view schematically showing a main part plane of the semiconductor integrated circuit device of FIG. 1;

FIG. 18 is a plan view showing a layout plane of a main part of the semiconductor integrated circuit device of FIG. 1;

FIG. 19 is a sectional view taken along line AA of FIG. 18;

FIG. 20 is a sectional view taken along line BB of FIG. 18;

FIG. 21 is a plan view showing a modification of FIG. 18;

FIG. 22 is a sectional view taken along line BB of FIG. 21;

23A is a simulation circuit diagram when inspecting an inter-block buffer operation, and FIG. 23B is an explanatory diagram showing a result of a power supply voltage fluctuation width during an inter-block buffer operation.

FIG. 24 is an explanatory diagram showing a result of a power supply voltage fluctuation width during an inter-block buffer operation in a technique compared with the present invention by the present inventors.

FIG. 25 is a flowchart showing a manufacturing process of the semiconductor integrated circuit device of FIG. 1;

26 is an explanatory diagram of the semiconductor integrated circuit device of FIG. 1 in an automatic placement and routing step.

27 is an automatic placement and routing step following FIG. 26, and FIG.
FIG. 5 is an explanatory diagram of the semiconductor integrated circuit device during an automatic placement and routing step.

28 is an automatic placement and routing step following FIG. 27 and is similar to FIG.
FIG. 5 is an explanatory diagram of the semiconductor integrated circuit device during an automatic placement and routing step.

FIG. 29 is a partial plan view of a semiconductor integrated circuit device, which is a technique compared with the present invention by the present inventors.

FIG. 30 is an explanatory diagram for describing a relationship between a power supply line length and a signal wiring arrangement in the semiconductor integrated circuit device of FIG. 1;

FIG. 31 is an explanatory diagram illustrating a relationship between a power supply line length and a signal wiring arrangement in the semiconductor integrated circuit device of FIG. 1;

FIG. 32 is a plan view of a basic cell of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 33 is a sectional view taken along line AA of FIG. 32;

FIG. 34 is a plan view of a basic cell of a semiconductor integrated circuit device according to still another embodiment of the present invention.

FIG. 35 is a sectional view taken along line AA of FIG. 34;

FIG. 36 is a plan view of a basic cell of a semiconductor integrated circuit device according to still another embodiment of the present invention.

FIG. 37 is a sectional view taken along line AA of FIG. 36.

[Explanation of symbols]

Reference Signs List 1 semiconductor chip 1s semiconductor substrate 2 basic cell 3 wiring 3VDD1 power supply wiring 3VDD2 power supply wiring 3VDD1 first layer power supply wiring (first power supply wiring) 3VDD2 second layer power supply wiring 3VDD3 third layer power supply wiring (second power supply wiring) 3VS1 Power supply wiring 3VS2 Power supply wiring 3VSS1 First layer power supply wiring 3VSS2 Second layer power supply wiring 3VSS3 Third layer power supply wiring 3VDDQ power supply wiring 3VSSQ power supply wiring 3VDBBL power supply wiring 3VSBBL power supply wiring 3S1a, 3S1b, 3S1c, 3S1d, 3S1d, 3S1e, 3S1e
S1g, 3S1h First layer signal wiring 3S2, 3S2a, 3S2b Second layer signal wiring (signal wiring of third wiring layer) 4 I / O cell 5 Bonding pad 6 Power generation circuit 7PWA, 7PWB, 7NW Well power supply area 8 Isolation Part 8a Isolation trench 8b Isolation insulating film 9na, 9nb, 9pa, 9pb Semiconductor region 11i Gate insulating film 12Ag, 12Bg Gate electrode 13 Silicide layers 14a to 14c Interlayer insulating film 15 Connection hole VDD power supply voltage VSS power supply voltage VDBB power supply voltage VSSB power supply Voltage Qsp1, Qsn1, Qsp2, MISF for Qsn2 switch
ET INV Inverter circuit N NAND circuit TH, TH1, TH2 Connection hole CONT Connection hole L Active area SW1, SW2 Switch cell 50 Gate electrode 51, 52 Semiconductor area 53 Signal wiring 54 Connection hole 55 Signal wiring 60VDD1, 60VSS1 First layer power supply Wiring 60VDD3, 60VSS3 Third layer power supply wiring 60S1 First layer signal wiring 60S2 Second layer signal wiring

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuto Nagashima 3-16, Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. 5F033 HH08 HH09 HH11 KK08 KK09 KK11 KK28 NN38 QQ48 VV04 VV05 XX08 XX36 5F064 AA03 BB13 BB14 BB15 DD10 DD12 EE03 EE06 EE09 EE16 EE23 EE26 EE27 EE35 EE47 EE52 FF36

Claims (29)

[Claims] 1. A method of designing a semiconductor device having a multi-layer wiring, comprising: (a) a step of arranging a plurality of basic cells; (b) a step of arranging wiring in a channel to form a logic circuit; And (b) after the step (b), arranging a connection hole for power supply reinforcement for electrically connecting different wirings to the empty channel. 2. A method of designing a semiconductor device having a multi-layer wiring, comprising: (a) a step of arranging a plurality of basic cells; and (b) a first wiring layer having a channel in a first direction.
A first power supply wiring is arranged, and a channel in a second direction intersecting with the first direction is provided in the second wiring layer above the first wiring layer to connect the inside of the basic cell and between the basic cells. A wiring to be connected is arranged, and a third wiring above the second wiring layer is provided.
(C) arranging a second power supply line that reinforces the first power supply line in the channel in the first direction, in the wiring layer, (c) after the step (b), the second power supply line Arranging a connection hole for electrically connecting the semiconductor device and a first power supply wiring. 3. The method of designing a semiconductor device according to claim 2, wherein, in the step (c), the connection hole is formed in an empty channel in which a wiring connecting the inside of the basic cell and between the basic cells is not arranged. A method for designing a semiconductor device, wherein the semiconductor device is arranged. 4. A semiconductor device having a multi-layer wiring, wherein field-effect transistors of a plurality of basic cells are formed in a first region of a semiconductor substrate, and a first potential for supplying a predetermined potential to the first region is provided. And a first power supply line electrically connected to a source of a field-effect transistor of the plurality of basic cells extends in the first direction. The second power supply wiring and the first wiring are disposed in a second wiring layer above the first power supply wiring and the first power supply wiring.
The second power supply line is formed above the first power supply line, and is electrically connected to the first power supply line; An upper portion is a wiring channel region, and the first wiring which is not electrically connected to the first power supply wiring is arranged in the wiring channel region. 5. A semiconductor device having a multi-layer wiring, wherein field-effect transistors of a plurality of basic cells are formed in a first region of a semiconductor substrate, and a first potential for supplying a predetermined potential to the first region is provided. A first power supply line electrically connected to a source of a field effect transistor of the plurality of basic cells, and a first power supply line; In a second wiring layer above the first power supply wiring, a wiring channel region is provided above the first power supply wiring, and the wiring channel region includes:
A semiconductor device, wherein a first wiring that is not electrically connected to the first power supply wiring is arranged to extend in the first direction. 6. The semiconductor device according to claim 4, wherein the first wiring is a wiring for electrically connecting different basic cells. 7. The semiconductor device according to claim 4, wherein a third wiring layer between the first power supply wiring and the first power supply wiring, and the second wiring layer, A second wiring extending in a second direction intersecting the first direction is formed, and different basic cells are electrically connected by the first and second wirings. Semiconductor device. 8. The semiconductor device according to claim 4, 5 or 6, wherein the first power supply wiring and the first power supply wiring;
A second power supply line electrically connected to the first power supply line and the first power supply line are provided on a third wiring layer between the second power supply line and the third wiring layer.
And a second power supply line electrically connected to the power supply line of the first aspect extends in a second direction intersecting the first direction. 9. The semiconductor device according to claim 8, wherein a switch for converting a potential for supplying a basic cell disposed below the second power supply wiring or the second power supply wiring to the first region is provided. A semiconductor device which is used as a cell for forming an element. 10. The semiconductor device according to claim 4, wherein said first power supply wiring is formed of a silicide layer formed on a surface of a semiconductor substrate. Semiconductor device. 11. The semiconductor device according to claim 4, wherein the first power supply wiring and the first power supply wiring are formed in the same wiring layer. A semiconductor device, comprising: 12. The semiconductor device according to claim 5, wherein
The semiconductor device according to claim 1, wherein the first power supply wiring extends in the first direction. 13. A semiconductor device having a multi-layer wiring, wherein field effect transistors of a plurality of basic cells are formed in a first region of a semiconductor substrate, and wherein a first potential for supplying a predetermined potential to the first region is provided. And a first power supply line electrically connected to a source of a field effect transistor of the plurality of basic cells extends in the first direction. A second wiring layer disposed above the first power supply wiring and the first power supply wiring and electrically connected to the first power supply wiring;
A second power supply line electrically connected to the first power supply line or the second power supply line intersecting with the first direction.
A cell for forming a switching element for converting a potential supplied to the first region from a basic cell arranged below the second power supply wiring or the second power supply wiring, the cell being arranged so as to extend in a direction. A semiconductor device characterized by being used as a semiconductor device. 14. The semiconductor device according to claim 13, wherein in a third wiring layer above the second wiring layer,
A wiring channel region is provided above the first power supply wiring, and a first wiring that is not electrically connected to the first power supply wiring extends in the first direction in the wiring channel region. A semiconductor device, wherein the semiconductor device is arranged in a manner as described above. 15. The semiconductor device according to claim 13, wherein the second power supply wiring and the first wiring are provided in a third wiring layer above the second wiring layer in the first direction. The second power supply wiring is formed above the first power supply wiring, and is electrically connected to the first power supply wiring; And a wiring channel region, wherein the first wiring that is not electrically connected to the first power supply wiring is disposed in the wiring channel region. 16. The semiconductor device according to claim 14, wherein the first wiring is a wiring for electrically connecting different basic cells. 17. The semiconductor device according to claim 13, 14, 15 or 16, wherein said first power supply wiring is formed of a silicide layer formed on a surface of a semiconductor substrate. 18. The semiconductor device according to claim 13, 14, 15, or 16, wherein the first power supply wiring and the first power supply wiring are formed by the same wiring layer. Semiconductor device. 19. The semiconductor device according to claim 4, wherein said basic cells are arranged in a second direction intersecting said first direction and have different gate widths. Out of the two types of field effect transistors having different gate widths, a field effect transistor having a relatively small gate width includes a plurality of p-channel type field effect transistors and a plurality of n-channel field effect transistors. , And each gate electrode is integrated with a wide pattern disposed in a region between the plurality of p-channel field-effect transistors and the plurality of n-channel field-effect transistors. A semiconductor device characterized by being formed and electrically connected to each other. 20. In the semiconductor device, the plurality of basic cells are composed of two types of field effect transistors having different gate widths arranged side by side in the first direction. The field-effect transistor having a relatively small gate width includes a plurality of p-channel field-effect transistors and a plurality of n-channel field-effect transistors, each having a gate electrode formed of the plurality of p-channel field-effect transistors. A semiconductor device, which is formed integrally with a wide pattern disposed in a region between a channel type field effect transistor and a plurality of n-channel type field effect transistors and is electrically connected to each other. 21. A semiconductor device having a multilayer wiring, comprising: a plurality of basic cells formed on a semiconductor substrate; and a first field effect transistor formed on the semiconductor substrate, wherein the field effect transistors of the plurality of basic cells are arranged. A region, a first power supply line for supplying a predetermined potential to the first region, a first power supply line electrically connected to a source of the field-effect transistor, and a first power supply line and a power supply line In the upper wiring layer, a wiring channel region is provided above the first power supply wiring, and the wiring channel region is not electrically connected to the first power supply wiring. A semiconductor device, wherein a first wiring for electrically connecting between the first and second wirings is provided. 22. A semiconductor device having a multi-layer wiring, comprising: a plurality of basic cells formed on a semiconductor substrate; A first region of a conductivity type; a second region of a second conductivity type formed on the semiconductor substrate, wherein a second field-effect transistor of the basic cell is arranged; A first power supply line extending along a first direction in which the plurality of basic cells are arranged, and a power supply supplying a predetermined potential to the second region. A second power supply wiring extending along the first direction in which the plurality of basic cells are arranged side by side; and supplying a first operating voltage of an element formed in the basic cell. Power supply wiring, which extends along the first direction. An extended power supply line, a power supply line for supplying a second operating voltage of an element formed in the basic cell, wherein the power supply line extends along the first direction; A third power supply line for supplying a predetermined potential to the power supply line, the third power supply line being formed above the first power supply line and extending in a second direction intersecting the first direction; A power supply line for supplying a predetermined potential to the second power supply line, the power supply line being formed in a layer above the second power supply line, and extending in the second direction intersecting the first direction; A fourth power supply wiring, and a potential supplied to a basic cell disposed immediately below at least one of the third power supply wiring and the fourth power supply wiring to the first region or the second region. For use as a cell for forming a switch element for Semiconductor device. 23. A semiconductor device having a multilayer wiring, comprising: a plurality of basic cells formed on a semiconductor substrate; a semiconductor region formed on the semiconductor substrate; and a region for supplying a voltage of a predetermined potential to the semiconductor region. A power supply region formed of the same conductivity type as the semiconductor region and having an impurity concentration higher than the impurity concentration of the semiconductor region, and extending along a first direction of the basic cell; A first power supply line for supplying an operating voltage of an element formed in a cell, the first power supply line being arranged in a first wiring layer above the semiconductor substrate and extending along a first direction of the basic cell. A power supply wiring for supplying an operating voltage of an element formed in the basic cell, the power supply wiring being disposed in a second wiring layer above the first wiring layer, and extending in a first direction of the basic cell. A second power line extending along A wiring, a connection hole for electrically connecting the first power supply wiring and the second power supply wiring, and a wiring layer between the first wiring layer and the second wiring layer, A signal wiring disposed in a third wiring layer having a second direction crossing the direction as a channel direction. 24. The semiconductor device according to claim 4, further comprising switching means for switching a voltage applied to said semiconductor region to an operation voltage or a substrate voltage. 25. A method of manufacturing a semiconductor device having a multilayer wiring, comprising: (a) a step of arranging a plurality of basic cells on a main surface of a semiconductor substrate; and (b) a first wiring layer in a channel in a first direction. Arranging a first power supply wiring composed of:
(C) in the second wiring layer above the first wiring layer, the first channel is formed in a channel parallel to the first direction.
Arranging a second power supply line for reinforcing the power supply line, and (d) in a third wiring layer between the first wiring layer and the second wiring layer in the first direction. Arranging a signal line in a channel in a second direction crossing the signal line;
(E) after the step (d), arranging a connection hole for electrically connecting the first power supply wiring and the second power supply wiring. 26. The method of manufacturing a semiconductor device according to claim 25, wherein a cross-sectional area of said second power supply wiring is equal to said first power supply wiring.
A method of manufacturing a semiconductor device, wherein the cross-sectional area is larger than the power supply wiring. 27. The method of manufacturing a semiconductor device according to claim 25, wherein the basic cell is formed in a semiconductor region formed on the semiconductor substrate, and extends in the semiconductor region along a first direction of the basic cell. And a step of arranging a power supply region formed of the same conductivity type as that of the semiconductor region and having an impurity concentration higher than that of the semiconductor region. 28. The method for manufacturing a semiconductor device according to claim 27, further comprising a step of forming a silicide layer on a surface layer of said power supply region. 29. The method of manufacturing a semiconductor device according to claim 27, wherein the power supply region is directly contacted with the power supply region,
A method for manufacturing a semiconductor device, comprising a step of forming a metal film extending along the extending direction.