JPS59163836A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a semiconductor integrated circuit from generation of the latch-up phenomenon by a method wherein electric power source lines are arranged to the fundamental cells of CMOS structure as to contact with the substrate layers of respective regions in the neighborhood of the boundary between the n-channel element region and the p-channel element region. CONSTITUTION:A p<+> type layer 34 and an n<+> type layer 36 to connect a p-well 32 and an n type Si substrate 31 to electric power source lines VSS, VDD are provided in the neighborhood of the boundary between respective element regions. When a transistor Tn is made to ON according to an outside noise current, the collector current thereof flows in the n type Si substrate 31, while the current thereof is fed effectively from the n<+> type layer 36 provided adjoining to the p-well 32. Accordingly, a voltage drop according to laterally directional resistance Rn is small, and forward bias to a transistor Tp is small. Therefore, because the positive feedback gain of a parasitic transistor circuit is small, the latch-up phenomenon is hard to be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a master slice type semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which a gate array is constructed using a basic cell arrangement of a CMO8 structure.

[Technical background of the invention and its problems]

Semiconductor integrated circuit (LSI) technology has made remarkable progress in recent years, and logic LSIs, such as memories and microcomputers, are rapidly increasing in scale. As a result, the use of LSI in various electronic equipment systems is progressing, resulting in higher performance, lower cost, lighter weight, smaller size, and higher reliability of electronic equipment systems.

The demand for LSI in various equipment systems is increasing, and in order to meet this demand, it is not only necessary to increase the scale of general-purpose products such as memory and microcontrollers, but also to increase the scale of LSI of electronic circuit parts with functions specific to various equipment systems. At the same time, compatibility is also becoming important. It goes without saying that such an electronic circuit section specific to a device system is difficult to implement using a general-purpose LSI, and even if it could be implemented, it would be difficult to demonstrate the advantages of an LSI. Therefore, in order to develop the equipment system industry, there was a strong demand for LSI parts to be used exclusively for systems, and it was an important role for semiconductor companies to respond to this demand.

However, as is well known, the cost of semiconductor devices, especially LSIs, can be reduced through mass production. The conversion of specific parts of various device systems into LSIs naturally makes it necessary to produce a wide variety of products in small quantities.
As a result of paying for the SI, the price of the dedicated LSI increased.

A gate array based on the so-called master slice method was born under these circumstances.

The gate array manufacturing process is divided into two processes: a master process and a personalization process.

FIG. 1 is a schematic diagram showing the surface of a semiconductor tip (master tip) after completing one mastering process.

In the center of the chip, there are a plurality of cell rows 1 ('I+12+...
, In) are arranged in an array, which are the main elements constituting the logic circuit. Each cell column 1 consists of an array of a plurality of basic cells. Between each cell row 1, a wiring region 2 is provided where wiring is provided for specializing the circuit in a later personalization step. In addition, around the step, 1710 cells 3, which constitute an input circuit for receiving an input signal from the outside and an output circuit for outputting an output signal to the outside, are arranged so as to surround the cell row 1, and further outside the cell row 1. Bonding pads 4 are formed in an array.

The basic cells constituting the cell row 1 are also composed of a plurality of elements, and there are several ways to configure them. 0
A pattern example of the basic cell 9 using the MO8 structure is shown in FIG. 2, and its equivalent circuit is shown in FIG. This basic cell consists of p
n+ffAl21-123 and polyS1 in well 11
Gate electrode 13. ．． Two n-channels consisting of 13□/
L/MO8FET-Qnl, Qn2 are formed, and p4- layers 14° to 143 and poly-Si are formed adjacent to p-well 11.
Gate electrode 15. ．． 152 color TR 2 pieces pf
Y* #MO8FET-QP+ +Qp2 is formed. As is clear from the figure, the basic cell does not perform a specific logical function as it is, but serves as a base for realizing the logical function.

Using the semiconductor wafer that has completed the above master process,
The process of specializing the LSI circuit by applying metal wiring thereon is the personalization process.

For gate arrays, the only production period after receiving a customer's order is this generalization process, which leads to a reduction in the LSI development period. Another important thing in this case is that the design period is short. For this purpose, the following method is adopted.0 Various gates (e.g., NOR, NA, ND, F/F, etc., which are basic 50 to 150 types of circuits) are designed, and the data is registered in a computer as a library. In the case of a gate array, this prepared gate is called a macrocell. Once the customer's requirements are determined, the entire circuit is designed using macro cells, they are automatically placed using a CAD system, and wiring is provided between the macro cells. A wiring area 2 shown in FIG. 1 is provided for this wiring. Current typical gate arrays use two layers of metal wiring. Since the functions requested by the customer are designed using this method, the design period can be shortened.

To configure a macro cell using basic cells, usually
Multiple basic cells are used. In this case, it is common to use a plurality of basic cells arranged in the vertical direction of cell column 1 in FIG. As a basic example, FIGS. 4 and 5 show an example in which a two-manpower NOR gate is designed using one basic cell of the 0MO8 structure shown in FIGS. 2 and 3.

16, to 164 are first layer metal wirings, 16□,
VTID where 162 is the power line (usually positive power supply)
line, Vss (normal ground) line, 16, . 16.
is the intra-cell wiring. 17. and 122 are second-layer metal wirings each serving as a signal input terminal. The reason why two-layer metal wiring is used is that a large number of first-layer metal wirings are provided in the wiring area 2 outside the cell row 1, and a large number of first-layer metal wirings are provided in the wiring area 2 outside the cell row 1, and the terminals of each cell and the metal wiring in the wiring area 2 are used for connection between cells. This is because the connection with the first layer metal wiring is made by the second layer metal wiring. Note that in FIG. 4, black circles indicate contact positions. The same applies to the drawings below.

As mentioned above, gate arrays can produce large quantities of master chips, which are semi-finished products but can be used as general-purpose products, in one master process, and in the finalization process, a CAD system is used to create logic circuits that meet customer requirements. This can be achieved in a short design period. For this reason, it is attracting attention as a means of supplying dedicated LSIs for various electronic equipment systems with short delivery times and at low cost.

However, the trend toward LSI device systems is becoming stronger (as a result, gate arrays are required to be even larger in scale, higher in performance, and lower in price.
Gate arrays using basic cells with an MO3 structure are becoming mainstream, but in order to meet the above requirements, the first major problem that must be solved is the latch-up phenomenon that accompanies miniaturization of elements. Second, there is wiring technology for high integration.

As is well known, the latte-up phenomenon is a parasitic transistor effect in 0MO8. This phenomenon will be briefly explained. As shown in FIG. 6, a p-well 22 is formed in an n-type S1 substrate 2), and an n-channel MO
8FET and an adjacent n-type S] p-channel MO3FET are respectively formed on the substrate to obtain 0MO8. In the figure, the n+ layer 23. which becomes the source. Only the p+ layer 25 is shown. At this time, each element region has a p+ layer 24°n+
A layer 26 is provided to provide voltages (L'j, Vss,
Connect to Vl)D. In such 0MO8, the transistors pnp) and npn) are connected as shown.
The transistor Tn is parasitic. Rp and Rn indicate the lateral resistance within the p-well 22 and the n-type substrate 21, respectively. This parasitic transistor circuit can be expressed as a circuit as shown in FIG. 7. Now, node A in Fig. 7,
That is, when a noise current is injected into the p-well 22 and the transistor Tn is turned on, the collector current causes a voltage drop across the resistor Rn, which acts in the direction of turning on the transistor Tp. When the transistor Tp is turned on and collector current flows, a voltage drop occurs across the resistor Rp, which is caused by the transistor Tp.
It works in the direction of turning on n. As a result of this positive feedback, if the feedback gain is 1 or more, both transistors Tp and Tn are turned on and the power supply VDD is turned on.

A large current flows between VssO and this large current is maintained even after the noise current disappears, leading to destruction of 0MO8. An example of an external noise current that causes such a latch-up phenomenon is the n-channel MO8FE in the p-well 22.
There is a hole current flowing into the p-well 22 from near the drain of T.

This becomes a problem as the device becomes finer and the electric field near the drain becomes stronger.

The second problem in terms of wiring technology is that, as explained in FIG. The problem is that even higher integration is being hindered.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a master slice type semiconductor integrated circuit having an 0MO8 structure, which achieves even larger scale integration and higher performance.

[Summary of the invention]

In the present invention, in order to prevent the latch-up phenomenon, firstly, when disposing a power supply line (including a ground line) in a basic cell with an 0MO8 structure, this It is arranged in the cell column direction across the center of the basic cell so as to contact the substrate layer of each region near the boundary of the channel element region. Furthermore, in the present invention, for large-scale integration, the basic cells are arranged symmetrically between adjacent cell rows, and a plurality of cell rows are densely arranged without leaving any wiring area between the cell rows. . The wiring, including the power supply line, is arranged on the cell column in a multilayer structure of three or more layers.

〔Effect of the invention〕

According to the present invention, when the parasitic transistor is turned on, the collector current does not flow along a long path in the lateral direction within each element region, but instead flows out to the power supply line, which reduces the amount of positive feedback, resulting in a fine Even in the 0MO8 structure, the hitch-up phenomenon can be effectively prevented. In addition, by placing adjacent basic cells back to back, eliminating the conventional wiring area and creating a multilayer wiring structure of three or more layers, a significantly higher degree of integration can be achieved than in the past. In this case, sharing the n-well or n-well between the basic cells arranged back to back also contributes to high integration. In addition, by arranging the basic cells back to back, only one of the two power supply lines of the cell row can be arranged continuously in the direction of the cell row, and the power supply line of the adjacent cell row can be connected in a direction perpendicular to the cell row. The derived branch wiring can be used as the other power supply line, which also contributes to higher integration.

Therefore, according to the present invention, it is possible to realize a gate array with higher performance and higher integration than the conventional gate array.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 8 shows the CMOS structure in the basic cell of one embodiment. An n-well 32 is formed on the n iu Si substrate 3, and an n-channel MO8F is formed in the n-well 32.
It is no different from the conventional method that a p-channel MO8FET is formed adjacent to the ET in the n-type S1 substrate 31. In the figure, the n+ layer 33 and p
+ Only the layer 35 is shown. What is different from the conventional FIG. 6 is that the p+ layer 34 and the r layer 36 for connecting the n-well 32 and the n-type S1 substrate 3 to the power supply line VSS and VDD are respectively constructed as shown in the figure. It is provided near the boundary of the element region.

The reason why this OMO8 structure effectively prevents the latch-up phenomenon is as follows.

As shown in the figure, parasitic transistors Tn and Tp are generated and lateral resistances Rp and Rn are inserted into their respective bases, as in the conventional case. Now, the transistor Tn
When turned on by an external noise current, its collector current flows in the n-type St 2 substrate 31, but this current is effectively supplied from the n4 layer 36 provided adjacent to the n-well 32. Therefore, compared to the case shown in FIG. 6, the voltage drop due to the lateral resistance Rn is smaller, and the transistor Tp
The forward bias to is small. Similarly, transistor T
When p is turned on, its collector current flows in the n-well 32, but is absorbed by the p'' layer 34 near the p-channel device region, so that the voltage drop across the lateral resistor Rp is small and the collector current flows to the transistor Tn. Since the positive feedback gain of the parasitic transistor circuit is small because the bias is small and is greater than 0, the latch-up phenomenon is less likely to occur.

Next, the basic cell arrangement and wiring structure will be explained. FIG. 9 shows a cell row 41 (41,,41□) of basic cells in the conventional structure.
,...) are arranged with the wiring areas between them packed together. That is, the basic cells of each cell column 4 are, for example, the second
The CP, ff OS structure is as shown in the figure, and the n-
ch and p-Ch indicate an n-channel device region and a p-channel device region, respectively. The same applies to the following figures.

Vss power line 42 (42,,4,?□, -・) and vDD power line 43 (43,,43,,・) are arranged in the cell column direction in contact with each substrate layer on both sides of the basic cell. are doing. Just by narrowing the spaces between cell rows in this way, a certain effect on higher integration can be expected. If this concept is applied to the cell structure of this embodiment, the result will be as shown in FIG. 10.

V ss for cell row 51 (51,,512,...)
The power supply line 52 (52112y"') and the vnD power supply line 53 (53, 532, ...) are connected to each other near the boundary (indicated by a broken line) between the n-channel element region and the p-channel element region of the basic cell. It is placed in contact with the substrate layer and across the center of the basic cell.

However, this alone is still not sufficient for high integration. Therefore, in this embodiment, as shown in FIG.
(611H6'2 +...) are densely arranged in a symmetrical arrangement with adjacent ones back to back. VSS power line 6
2 (62+t 62t+...) and VDT- power supply line 63 (631, 632, -.-) are the same as in Fig. 10.
Arranged across the center of the basic cell.

Regarding a concrete example in which the structure shown in FIGS. 2 and 3 is used as a basic cell, the structure of two adjacent basic cell parts of cell rows 61□ and 613 in FIG. As shown in the figure.

Adjacent elementary cells share one p-well 64, and four n-channel MO8FETs are formed in this p-well 64, and two p-channel MO8FETs are formed on each side of the p-well 64.
Two circuits shown in FIG. 3 are arranged back to back to form a FET. Further, FIG. 12 shows the wiring of an example in which the basic cell on the right constitutes a macro cell corresponding to the two-man power NOR gate explained with reference to FIGS. 4 and 5. For example, the wiring 65 connecting the power supply lines 62, 63 and the gate electrode in the cell is the first layer metal wiring, the wiring 66 serving as the output end, the wiring 67 serving as the input end, . 67, the second
Layer metal wiring. Then, wiring between such macro cells is performed using metal wiring from the third layer onwards. Thereby, a desired logic function can be realized by directly using the cell column as a wiring area.

As explained above, according to this embodiment, by improving the power supply line contact position in the basic cell of 0MO8 structure, latch-up phenomenon can be effectively prevented even when the element is miniaturized. Furthermore, by improving the arrangement of basic cells and applying three or more metal wiring layers, it is possible to achieve higher performance and higher integration of the gate array.

Note that the arrangement pattern of the power supply lines 62 and 63 shown in FIG. 11 can be further improved. For example, as shown in FIG. 13, each cell column has one power supply line running in the cell column direction. In other words, cell row 151 HH613+ "' has VDI
I side power supply line 63. .

63B, . . . and the cell rows 61 . ．． 61. ,... has Vss side power line 622゜6
24, . . . run in the direction of the cell columns, and branch wirings led out laterally from these power supply lines supply power to the necessary basic cells in the respective adjacent cell columns. Fig. 14 is a further modification of Fig. 13, in which branch wirings led out in the horizontal direction are made to run over the boundaries of the basic cells adjacent above and below the cell column, and one branch wiring simultaneously supplies power to the upper and lower basic cells. It is designed to supply If this is further developed, it is also possible to reduce the number of branch wirings led out in the horizontal direction by half, as shown in FIG.

In addition, in the above explanation, the p-well type CMO8 was exclusively illustrated, but the present invention also applies to the n-well type or twin-tub type CMO8.
The same can be applied to the case where MO8 is used.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a schematic pattern of a master step in a conventional gate array, Fig. 2 is a diagram showing a configuration example of a basic cell using CMO3, Fig. 3 is an equivalent circuit diagram of the basic cell, and Fig. 4 is also a two-person NO using that basic cell.
A diagram showing the wiring of the macrocell that constitutes the R gate, Figure 5 is an equivalent circuit diagram of the macrocell, Figure 6 is a diagram showing the CMO3 structure in the conventional basic cell, and Figure @7 is the latch-up phenomenon of the 0MO8 structure. 8 is a diagram showing a 0MO8 structure in a base A cell according to an embodiment of the present invention, and FIG. 9 is a diagram showing a conventional basic cell structure in which the spacing between cell columns is narrowed. A diagram showing the arrangement of cell rows. FIG. 10 is a diagram showing the arrangement of cell rows in which the spaces between cell rows are narrowed in a basic cell structure used in an embodiment of the present invention. FIG. 11 is a diagram showing the arrangement of cell rows in an embodiment of the present invention. FIG. 12 is a diagram showing a specific pattern example of two basic cell parts between adjacent cell rows, and FIGS. 13 to 15 are implementations in which the power supply wiring in FIG. 11 is modified. It is a figure which shows an example. 31 =-n-type Sr substrate, 32-/p well, 33
...n+ layer (source), 34...p+ layer (power line contact region), 35...p4- layer (source), 3
6...n layer (power line contact area), 61 (61
1+2+ ・)・Cell column, 62 (62,. 1 622 , =−)−・・Power supply line (Vss), 63 (6
3. 63□, ・') ・, Power line (VDD)'+6
4-p '7 L, 65... 1st layer metal wiring, 66.
...Second layer metal wiring, 67, . 67,...Third layer metal wiring. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure TS2 Figure 5 Figure Vss VD. ■o u Figure 6 Figure 7 Figure 8

Claims (2)

[Claims] (1) A master chip is formed by forming a plurality of cell rows each consisting of a plurality of basic cells with a CMO8 structure on a semiconductor substrate;
In a semiconductor integrated circuit that configures a desired functional circuit by applying the necessary wiring, is it possible to form multiple cell rows with basic cells in a symmetrical pattern between adjacent cell rows? The power supply lines are arranged in a dense manner and extend in the direction of the cell column across the center of the basic cell so as to contact the substrate layer of each region near the boundary between the n-channel device region and the p-channel device region of the basic cell. What is claimed is: 1. A semiconductor integrated circuit characterized in that the wiring layers including the power supply line are arranged in a multi-layered pattern of three or more layers. (2) Basic cells between adjacent cell rows are p-well or n-well
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit shares a well.