JPH073863B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a master slice type semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that forms a gate array using a basic cell array of CMOS structure.

[Technical Background of the Invention and its Problems] Recent advances in semiconductor integrated circuit (LSI) technology are remarkable,
Logic LSIs typified by memories and microcomputers are rapidly increasing in scale. As a result, various electronic device systems
As LSIs are advanced, high performance, low price, light weight and small size, and high reliability of electronic equipment systems are brought about. There is an ever-increasing demand for LSIs for various device systems.To meet this demand, not only are general-purpose products such as memories and microcomputers scaled up, but also LSIs for electronic circuits that have functions unique to various device systems. At the same time, becoming more important.
The electronic circuit section peculiar to such a device system is naturally difficult to realize with a general-purpose LSI, and even if it can be realized, it is difficult to exert the advantages of the LSI. For this reason, in order to develop the equipment system industry, there is a strong demand for the LSI to be a part dedicated to the system, and it has been an important role for semiconductor companies to meet this demand.

However, as is well known, semiconductor devices, particularly LSIs, can be manufactured at low cost by mass production. As a matter of course, making the parts specific to various equipment systems into LSIs will lead to the production of high-mix, low-volume products. I was invited.

A gate array based on the so-called master slice method was born in such a situation. The gate array manufacturing process is divided into a master process and a personalization process.

FIG. 1 is a schematic view showing the surface of a semiconductor chip (master chip) that has completed the master process. A plurality of cell rows 1 (1 ₁ , 1 ₂ , ..., 1 _n ) are arranged and formed in the central portion of the chip, and this is the main element constituting the logic circuit. Each cell row 1 is composed of an array of a plurality of basic cells. Between each cell row 1, a wiring region 2 is provided in which wiring for specializing a circuit in a later personalization step is provided. Further, around the chip, I / O cells 3 forming an input circuit for receiving an input signal from the outside and an output circuit for outputting an output signal to the outside are arrayed and formed so as to surround the cell row 1, and further outside thereof. Bonding pads 4 are formed in an array.

The basic cell that constitutes the cell array 1 is also composed of a plurality of elements, and there are several methods for constructing the basic cell. cm
Figure 2 shows an example of a basic cell pattern using the OS structure.
The equivalent circuit is shown in FIG. This basic cell consists of n-type Si
Two n-channel MOS FET-Qs consisting of n ⁺ layers 12 _{1 to} 12 ₃ and poly-Si gate electrodes 13 ₁ and 13 ₂ in a p-well 11 formed on a substrate.
n ₁ and Qn ₂ are formed, and p ⁺ layers 14 _{1 to} 14 ₃ are formed adjacent to the p well 11
And two p-channels consisting of poly-Si gate electrodes 15 ₁ and 15 ₂
It is configured by forming MOS FET-Qp ₁ and Qp ₂ . As is apparent from the figure, the basic cell does not perform a specific logical function as it is, but serves as a base for realizing the logical function.

A personalization process is a process of using a semiconductor wafer that has undergone the above master process and providing metal wiring on it to specialize an LSI circuit. In the gate array, the manufacturing period after receiving the customer's order is only the personalization process, which leads to the shortening of the LSI development period. In this case, another important thing is that the design period is short. For this purpose, the following method is adopted. Various gates required to configure a logic circuit using the above-mentioned basic cell (for example, a unit logic circuit which is a basic logic circuit including a NOR circuit and a NAND circuit, or an F / F combining unit logic circuits) Basic circuit such as circuit About 1
50 species) were designed, and the data is registered as a library in the computer. In the case of a gate array, this prepared gate is called a macro cell. When the customer's requirements are decided, the whole circuit is designed by using macro cells, they are automatically arranged by using CAD system, and wiring between macro cells is performed. The wiring region 2 shown in FIG. 1 is provided for this wiring. The current general gate array uses two layers of metal wiring. Since the function requested by the customer is designed by such a method, the design period can be shortened.

To configure a macro cell using basic cells,
A plurality of basic cells are used. In this case, it is usual to use a plurality of basic cells arranged in the vertical direction of the cell row 1 in FIG. As a simple example, FIGS. 4 and 5 show an example in which a 2-input NOR gate is designed by using one basic cell having the CMOS structure shown in FIGS. 2 and 3. 16 _{1 to} 16 ₄ are first-layer metal wirings, and 16 ₁ and 16 ₂ are power supply lines V _DD (normal positive power supply) line and V _SS (normal ground) line, respectively.
₃ and 16 ₄ are the wiring in the cell. Reference numerals 17 ₁ and 17 ₂ denote second-layer metal wirings that serve as signal input terminals, respectively. The two-layer metal wiring is used because a large number of first-layer metal wirings are provided in the wiring area 2 outside the cell row 1 and the terminals of each cell and the wiring area 2 are provided for inter-cell connection. This is because the second layer metal wiring is used for connection with the first layer metal wiring. In FIG. 4, black circles indicate contact positions. The same applies to the following drawings.

As described above, a gate array can produce a large number of master chips, which are semi-finished products in the master process, but are so-called general-purpose products. It can be realized in the design period. For this reason, attention has been paid to the fact that dedicated LSIs for various electronic device systems can be supplied at low cost with a short delivery time.

However, as the trend toward LSI for device systems further increases, there is a demand for further large scale, high performance, and low cost of gate arrays.

For example, as shown in FIG. 1, in the conventional gate array, the area of the basic cell row 1 and the wiring area 2 are almost the same area, and the occupied area of the wiring portion is very large for an LSI. The elements in the basic cell are also large. This is for the following reasons. In a normal logic LSI, various sizes of transistors are used due to the characteristics and demand for reduction of the chip area. On the other hand, in the gate array, since the transistors in the basic cell need to have the same size, an intermediate size is adopted.

Due to these two reasons, that is, the area of the wiring portion is large and the size of the transistor is large, the scale of the gate array is suppressed to about 1/5 of that of a normal logic LSI.
In this way, the scale required by the customer
At present, we are not fully satisfied due to technical restrictions.
In order to increase the scale of the gate array, it is especially important to increase the density of the cell array portion including the wiring region.

As described above, the gate array using the CMOS structure is becoming the mainstream. In this case, the first problem is to solve the large-scale problem in order to meet the demand for large scale. There is a latch-up phenomenon, and secondly, there is a wiring technique for high integration.

As is well known, the latch-up phenomenon is a parasitic transistor effect in CMOS. This phenomenon will be briefly described. As shown in FIG. 6, a p-well 22 is formed in an n-type Si substrate 21, an n-channel MOS FET is formed in the p-well 22, and a p-channel MOS FET is formed in an n-type Si substrate adjacent thereto. And CMOS can be obtained. In the figure, the source n ⁺ layer 23, P ⁺
Only layer 25 is shown. At this time, the P ⁺ layer 24, n is
^{A +} layer 26 is provided and connected to the power supplies V _SS and V _DD , respectively. In such a CMOS, as shown in the figure, the pnp transistor Tp
And npn transistor Tn are parasitic. Rp and Rn are p
The lateral resistance in the well 22 and the n-type substrate 21 is shown. The equivalent circuit of this parasitic transistor circuit is
It becomes like the figure. Now, assuming that the noise current is injected into the node A in FIG. 7, that is, the p-well 22 and the transistor Tn is turned on, a voltage drop occurs in the resistor Rn due to the collector current thereof, which turns on the transistor Tp. work. As a result, when the transistor Tp is turned on and a collector current flows, a voltage drop occurs in the resistor Rp, which acts to turn on the transistor Tn. As a result of the positive feedback, if the feedback gain is 1 or more, both the transistors Tp and Tn are turned on and a large current flows between the power supplies V _DD and V _SS , and this large current is generated even after the noise current disappears. As it is maintained, CMOS is destroyed. An external noise current that causes such a latch-up phenomenon is, for example, a hole current flowing into the p-well 22 from the vicinity of the drain of the n-channel MOS FET in the p-well 22. This becomes a problem as the device becomes finer and the electric field near the drain becomes stronger.

The second problem in the wiring technology is that the wiring region 2 is provided between the cell rows 1 in the same area as the cell rows 1 as described with reference to FIG. The reason is that further integration is hindered.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a master slice type semiconductor integrated circuit having a CMOS structure, in which the degree of freedom in design is increased to achieve further large-scale integration and high performance. And

[Structure of Invention]

A master cell is formed by forming a plurality of basic cells having a CMOS structure composed of PMOS transistors and NMOS transistors on a semiconductor substrate to form a cell row, and forming a plurality of cell rows in a direction orthogonal to the extending direction of the cell row. In a semiconductor integrated circuit in which a chip is provided with necessary wirings to form a desired functional circuit, the CMOS is formed so that transistors of the same conductivity type are arranged in one cell row in the extending direction of the cell row.
Forming a structure, between adjacent cell columns in a direction orthogonal to the extending direction of the cell columns densely and without providing a wiring region, a CMOS structure of one cell column and a CMOS structure of the other cell column Of the cell array so that
Forming a structure, the wiring layer provided above the wiring layer for forming the gate electrode of the transistor of the basic cell is a multilayer structure of three or more layers, the power supply line is an NMOS region in which the NMOS transistors are arranged in the cell row and Lined up PMOS transistors
A ground line is formed on the side of the PMOS region near the boundary of the PMOS region, on the side of the NMOS region near the boundary in the direction in which the cell columns extend, and the functional circuit is formed by combining any of the basic cells. It is characterized in that a unit logic circuit which is a constituent element of the above is constructed.

〔The invention's effect〕

According to the present invention, adjacent basic cells as back to back,
By eliminating the conventional wiring region and using a multi-layered wiring structure of three layers or more, it is possible to achieve a significantly higher degree of integration than in the past.
In this case, sharing the p well or n well between the back-to-back basic cells also contributes to high integration. Further, according to the present invention, there is no wiring region between the cell columns, and the inclusion of the macro cell in which the basic cells are combined between the adjacent cell columns increases the degree of freedom in design as compared with the conventional one, which also contributes to high integration. To do.

Therefore, according to the present invention, the performance is significantly improved as compared with the conventional one,
It is possible to realize a highly integrated gate array. In addition, if the power supply line is wired across the central portion, the collector current when the parasitic transistor turns on does not flow in a laterally long path in each element region and flows out to the power supply line, so the positive feedback amount is small. Therefore, even in the miniaturized CMOS structure, the latch-up phenomenon is effectively prevented. Also, by arranging the basic cells back to back, only one of the two power supply lines of the cell row is continuously arranged in the cell row direction, and the power supply line of the adjacent cell row is arranged in the direction orthogonal to the cell row. The derived branch wiring can be used as the other power supply line, which also contributes to high integration.

Example of Invention

 Examples of the present invention will be described below.

FIG. 8 shows the CMOS structure in the basic cell of one embodiment. A p-well 32 is formed on the n-type Si substrate 31, and the p-well 32 is formed.
N-channel MOS FET inside, n-type Si substrate 3 adjacent to this
Forming each n-channel MOS FET in 1 is no different from the conventional method. In the figure, n ⁺ layer 33 and p ⁺ that are the respective sources
Only layer 35 is shown. The difference from the conventional FIG. 6 is that p
The p ⁺ layer 34 and the n ⁺ layer 36 for connecting the well 32 and the n-type Si substrate 31 to the power supply lines V _SS and V _DD , respectively, are provided in the vicinity of the boundary of each element region as shown in the drawing. .

The reason why the CMOS structure effectively prevents the latch-up phenomenon is as follows. As shown in the figure, parasitic transistors Tn and Tp are generated, and lateral resistances Rp and Rn enter the respective bases, as in the conventional case. Now, when the transistor Tn is turned on by an external noise current, its collector current flows in the n-type Si substrate 31, but this current is effectively supplied from the n ⁺ layer 36 provided adjacent to the p well 32. It Therefore, compared to the case of FIG. 6, the voltage drop due to the lateral resistance Rn is small and the forward bias to the transistor Tp is small. Similarly, when the transistor Tp is turned on, its collector current flows in the p well 32, but is absorbed by the p ⁺ layer 34 close to the p channel element region, and as a result, the voltage drop at the lateral resistance Rp is small, and The forward bias on Tn is small. For the above reason, since the positive feedback gain of the parasitic transistor circuit is small, the latch-up phenomenon hardly occurs.

Next, the basic cell array and the wiring structure will be described. FIG. 9 shows a state in which the cell rows 41 (41 ₁ , 41 ₂ , ...) Of the basic cells of the conventional structure are arranged with the wiring region between them being filled. That is, the basic cell of each cell row 41 is, for example, a CMOS as shown in FIG.
This is a structure, and n-ch and p-ch in the figure represent an n-channel element region and a p-channel element region, respectively. The same applies to the following figures. The V _SS power supply line 42 (42 ₁ , 42 ₂ , ...) And the V _DD power supply line 43 (43 ₁ , 43 ₂ , ...) Are arranged in the cell column direction by contacting each substrate layer at both ends of the basic cell. ing. As described above, a certain effect can be expected for high integration simply by filling the space between the cell rows. When this idea is applied to the case where the cell structure of this embodiment is used, it becomes as shown in FIG. V _SS power supply line 52 (52 ₁ , 52) for the cell row 51 (51 ₁ , 51 ₂ , ...)
₂ , ...) and V _DD power supply lines 53 (53 ₁ , 53 ₂ , ...) Contact the respective substrate layers in the vicinity of the boundary (indicated by a broken line) between the n-channel element region and the p-channel element region of the basic cell,
It is arranged so as to cross the central portion of the basic cell.

However, this alone is not enough for high integration. Therefore, in this embodiment, as shown in FIG.
_1, 61 _2, ...) is adjacent ones of the densely arranged as symmetrically disposed back to back. The V _SS power supply line 62 (62 ₁ , 62 ₂ , ...) And the V _DD power supply line 63 (63 ₁ , 63 ₂ , ...) Are arranged so as to cross the central portion of the basic cell as in FIG.

For a more specific embodiment in which the structure shown in FIGS. 2 and 3 is used as the basic cell, the cell row of FIG.
The structure of two adjacent basic cell portions of 61 ₂ and 61 ₃ is shown in FIG. Adjacent basic cells share one p-well 64, four n-channel MOS FETs are formed in this p-well 64, and two p-channel MOS FETs are formed on each side of the n-channel MOS FETs.
And two circuits shown in FIG. 3 are arranged back to back. Also, in FIG. 12, in the basic cell on the right side,
The wiring of the example which comprises the macrocell equivalent to the 2-input NOR gate demonstrated by FIG. 5 and FIG. 5 is shown. For example,
Wiring 6 that connects the power supply lines 62 and 63 and the gate electrode in the cell
5 is the first layer metal wiring, and the wiring 66 serving as the output terminal and the wirings 67 ₁ and 67 _{2 serving} as the input terminals are the second layer metal wirings. Then, the wiring between such macro cells is performed by the metal wiring of the third layer or more. As a result, a desired logical function can be realized by using the cell row as it is as a wiring area.

Next, the constituent parts of the macro cell using two or more basic cells in this embodiment will be described. As mentioned previously,
Since there is a wiring region between cell columns, when the macrocell circuit is large, two or more basic cells in one cell column are used to configure the macrocell. However, in the present invention, since the cell rows are densely arranged as shown in FIG. 11, it is possible to configure a macro cell by using a plurality of basic cells between adjacent cell rows. That is, when the same circuit is designed using the same number of basic cells, the degree of freedom in combining the basic cells is high. This idea can be further developed. For example, in a macro cell using 6 basic cells, when 6 basic cells are used in the column direction, 6 in the row direction.
In addition to the case of using one basic cell, there is also a case of using two columns and three rows or three columns and two rows of basic cells. Furthermore, there are the following cases. The two-input NOR gate shown in FIGS. 4 and 5 uses four transistors in one basic cell. In this case, the two n-channel MOS transistors are connected in parallel and the two p-channel MOS transistors are directly connected. Therefore, the resistance of the p-channel MOS transistor connected in series becomes high, and as a result, the speed at which the output voltage rises to a high level becomes slow. In order to avoid this, there is a method of using four n-channel MOS transistors as shown in FIG. That is, p-channel MOS transistors Qp ₁₁ and Qp ₁₂ are connected in parallel, Qp ₂₁ and Qp ₂₂ are connected in parallel, and these are connected in series. When such a NOR gate is constructed by using the basic cell structure shown in FIG. 2 and using two basic cells in one cell row, it becomes as shown in FIG. The transistor representation in FIG. 14 corresponds to that in FIG. In this case, in FIG. 14, MOS transistors Qn ₁₂ , Q
n ₂₂ is unused.

On the other hand, FIG. 15 shows an embodiment of the present invention in which a similar NOR gate is constructed by using two basic cells in adjacent cell rows. Again, the transistor display corresponds to that in FIG. Also in the embodiment shown in FIG. 15, the n-channel MOS transistors Qn ₁₂ and Qn ₂₂ remain unused.

The layout relationships between the used transistors and the unused transistors in the macrocell configurations of FIGS. 14 and 15 are shown in FIGS. 16 and 17, respectively, for easy understanding. Fig. 16 and
In FIG. 17, the shaded portions of the n-channel MOS transistors Qn ₁₂ and Qn ₂₂ are unused. Comparing these, in the case of FIG. 16 according to the conventional method in which a macro cell is formed in one cell row, the n-channel MOS transistor Qn ₁₂ is no longer useful. However, in the configuration of FIG. 17 according to this embodiment, both the unused transistors Qn ₁₂ and Qn ₂₂ can be effectively used for the configuration of another macro cell. For example, consider the case of configuring a 2-input NAND gate. In general, two-input NAND gates have two n-channel MOS transistors connected in series and two p-channel MOS transistors connected in parallel. In this case, in order to avoid an increase in resistance due to the serial connection of two n-channel MOS transistors, four n-channel MOS transistors are used according to the same concept as the NOR gate in FIG. If an attempt is made to construct such a NAND gate with two adjacent basic cells, the inner two n-channel MOS transistors are unused, symmetrically with the case of the NOR gate shown in FIG. So this 2-input NAND gate and the previous 2
When the input NOR gates are brought into contact with each other and arranged using basic cells of 2 columns and 2 rows, as shown in FIG. 18, NOR gates G ₁ and NAN are arranged.
It becomes possible to design the D gate G ₂ and the basic cell area for three basic cells without waste while maintaining the square shape.

As described above, according to this embodiment, by improving the power supply line contact position in the basic cell having the CMOS structure, it is possible to effectively prevent the latch-up phenomenon even when the device is miniaturized. Further, by improving the arrangement of the basic cells and providing three or more metal wiring layers, it is possible to achieve high performance and high integration of the gate array.

Further, according to this embodiment, the conventional wiring area is eliminated and the macro cell is formed by combining the basic cells of the adjacent cell rows, so that the degree of freedom in design can be increased and the basic cells can be efficiently used. This is possible and can greatly contribute to the scale-up of the gate array.

The arrangement pattern of the power supply lines 62, 63 shown in FIG. 11 can be further improved. For example, as shown in FIG. 19, there is one power supply line running in the cell column direction for each cell column. That is,
V _DD side power supply lines 63 ₁ , 63 ₃ , ... Are connected to the cell columns 61 ₁ , 61 ₃ ,.
A V in the cell rows 61 ₂ , 61 ₄ , ...
_SS power line 62 _2, 62 _4, run ... to cell column direction, and supplies power to the required basic cells of the cell column adjacent each by a branch wiring is led out laterally from these power lines. FIG. 20 is a modification of FIG. 19, in which the branch lines that are derived in the horizontal direction are placed on the boundaries of the basic cells that are adjacent to each other in the upper and lower parts of the cell row, and one branch line simultaneously supplies power to the upper and lower basic cells. Is to be supplied. If this is further developed, it is possible to reduce the number of branch wirings extending in the horizontal direction to half as shown in FIG.

Further, in the above description, the p-well type CMOS is exclusively exemplified, but the present invention can be similarly applied to the case of using the n-well type or twin-tab type CMOS.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic pattern of a master chip in a conventional gate array, FIG. 2 is a diagram showing a configuration example of a basic cell using CMOS, FIG. 3 is an equivalent circuit diagram of the basic cell, and FIG. Is a diagram showing the wiring of a macro cell in which a 2-input NOR gate is also constructed using the basic cell, FIG. 5 is an equivalent circuit diagram of the macro cell, and FIG. 6 is a diagram showing a CMOS structure in a conventional basic cell. FIG. 7 is a diagram showing a parasitic transistor circuit for explaining the latch-up phenomenon of the CMOS structure, and FIG. 8 is a CMOS in a basic cell of one embodiment of the present invention.
FIG. 9 is a diagram showing the structure, FIG. 9 is a diagram showing the arrangement of cell rows in which the cell rows are packed in the conventional basic cell structure, and FIG. 10 is a basic cell structure used in the embodiment of the present invention in which the cell rows are packed. FIG. 11 is a diagram showing the arrangement of cell columns, FIG. 11 is a diagram showing the arrangement of cell columns in one embodiment of the present invention, and FIG. 12 is a specific pattern example of two basic cell parts between adjacent cell columns. FIG. 13 is an equivalent circuit diagram of a 2-input NOR gate used in this embodiment,
FIG. 14 is a diagram showing a pattern in which this NOR gate is constructed by a conventional method, FIG. 15 is a diagram showing a pattern constructed in this embodiment, and FIGS. 16 and 17 are the same as FIGS. 14 and 15 above. FIG. 18 is a diagram showing a distribution of used transistors, FIG. 18 is a diagram showing a distribution of used transistors when a NOR gate and a NAND gate according to this embodiment are arranged adjacent to each other, and FIGS. 19 to 21 are modified power supply wirings of FIG. It is a figure which shows an Example. 31 ... n type Si substrate, 32 ... p well, 33 ... n ⁺ layer (source),
34 ... p ⁺ layer (power line contact area), 35 ... p ⁺ layer (source), 36 ... n ⁺ layer (power line contact area), 61 (61 ₁ , 6)
1 ₂ , ...) ... Cell row, 62 (62 ₁ , 62 ₂ , ...) ... Power line (V _SS ), 63 (63 ₁ , 63 ₂ , ...) ... Power line (V _DD ), 64 ... p
Well, 65 ... First layer metal wiring, 66 ... Second layer metal wiring, 67
₁ , 67 ₂ … Third layer metal wiring.

Claims (1)

[Claims] 1. A plurality of basic cells having a CMOS structure composed of a PMOS transistor and an NMOS transistor are formed on a semiconductor substrate to form a cell row, and the plurality of cell rows are arranged in a direction orthogonal to the extending direction of the cell row. In a semiconductor integrated circuit in which columns are formed into a master chip and necessary wirings are formed to form a desired functional circuit, transistors of the same conductivity type are arranged in one cell column so that they are arranged in the extending direction of the cell column. A CMOS structure is formed, and a CMOS structure of one cell column and a CMOS structure of the other cell column are densely formed without providing a wiring region between adjacent cell columns in a direction orthogonal to the extending direction of the cell column. Forming a CMOS structure of the cell row so that and are in a mirror image relationship, and providing three or more wiring layers provided above the wiring layer for forming the gate electrode of the transistor of the basic cell. The power supply line has a PM structure near the boundary between the NMOS region in which the NMOS transistors are arranged and the PMOS region in which the PMOS transistors are arranged in the cell line.
A unit forming a ground line on the OS region side on the NMOS region side near the boundary in the extending direction of the cell column and combining any of the basic cells to be a constituent element of the functional circuit. A semiconductor integrated circuit comprising a logic circuit.