JP2002026298A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be adapted to a change in specification more easily than the conventional device by only changing the masks of partial wiring layers even when many wiring layers exist. SOLUTION: This semiconductor device is provided with a semiconductor substrate 10 having first and second regions, a plurality of gate electrodes 31 and 32, impurity diffusion regions 11-16, and N layers of wiring layers containing (M-1)-th wiring 51-56 electrically connected to the gate electrode of prescribed transistors or impurity diffusion regions formed in the first and second regions and M-th wiring 71-72 electrically connected to the gate electrodes of prescribed transistors or impurity diffusion regions formed in the first region only (N and M are integers meeting the relation of 2<=M<=N).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device such as a gate array, an embedded array, and a standard cell including a logic circuit portion designed in accordance with specifications of a supplier.

[0002]

2. Description of the Related Art In a semiconductor device such as a gate array including a logic circuit portion designed in accordance with the specifications of a supplier, if the specifications are changed in the supplier, the design is changed immediately in response to the change. There must be. Orders for such specification changes are subject to engineering change
Called order (ECO).

[0003]

In order to cope with ECO, for example, when one inverter must be added, it is necessary to change the design in all layers of the semiconductor device. As a result, there is a problem that a period (TAT) required from the start of the design to the completion of the product is extended and a development cost is increased. In order to avoid such a problem, the following measures have been proposed.

Japanese Patent Application Publication (JP-A) Hei 3-2
No. 03371 discloses that an extra delay circuit is previously formed in a wiring region in a semiconductor gate array device in which a cell region and a wiring region are separated from each other. However, when the newly required circuit is not a delay circuit but an inverter, a large-scale design change cannot be avoided. Further, in order to newly connect a circuit, a signal line at the initial stage of design is cut by etching, and a wiring is changed by adding a new signal line, thereby increasing the number of manufacturing steps.

On the other hand, in Japanese Patent Application Laid-Open No. Hei 4-7857, when an input / output cell group and a standard cell group are laid out on a semiconductor substrate, a pattern in which a transistor can be constituted only by wiring is laid out in a wiring channel portion. It is described that in a manufacturing process, a process before a wiring process of a pattern capable of forming the transistor is completed together with a manufacturing process of an input / output cell group and a standard cell group. The ECO is dealt with by correcting the wiring mask. Similarly, JP-A-4-1518
No. 68 and Japanese Patent Laid-Open No. 5-15733 disclose that a spare basic cell that is not connected in advance is dispersedly arranged in a semiconductor chip. However, if there are a number of wiring layers, all of these wiring layers must be changed in order to cope with ECO.

[0006] In view of the above, an object of the present invention is to provide a simpler ECO than in the past by changing only the masks of some of the wiring layers even when there are many wiring layers. The object of the present invention is to provide a semiconductor device which can cope with the above.

[0007]

In order to solve the above problems, a semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate having a first region and a second region, and first and second semiconductor substrates. A plurality of gate electrodes formed on the second region with a gate insulating film interposed therebetween, and a plurality of transistors formed in the semiconductor substrate on both sides of each gate electrode to form a plurality of transistors in the first and second regions An impurity diffusion region;
An N-layer wiring layer formed on a semiconductor substrate with an interlayer insulating film interposed therebetween, and a predetermined one of a plurality of transistor gate electrodes and impurity diffusion regions formed in the first and second regions. A plurality of wirings of the (M-1) th layer electrically connected to each other through the opening, and a predetermined one of a plurality of gate electrodes and impurity diffusion regions of the plurality of transistors formed only in the first region Including a plurality of wirings of an Mth layer electrically connected to each other through the opening.
(N and M are integers having a relation of 2 ≦ M ≦ N).

Here, at least one of the wiring layers from the first layer to the (M-1) th layer sets the source of at least one transistor formed in the second region to the power supply potential or the ground potential. You may comprise so that the wiring electrically connected may be included. The M-th wiring layer electrically connects a drain of at least one transistor formed in the first region to a gate electrode of at least one other transistor formed in the first region. It may be configured so as to include wiring to be performed.

A semiconductor device according to a second aspect of the present invention includes a semiconductor substrate having a first region in which a transistor constituting a predetermined circuit is formed and a second region in which a spare transistor is formed. A multi-layer wiring layer formed on a semiconductor substrate via an interlayer insulating film, wherein the multi-layer wiring layer is formed in at least one wiring layer, and is provided in a predetermined one of a gate electrode and an impurity diffusion region of a spare transistor. The multilayer wiring layer including a plurality of connection terminals electrically connected to each other through the opening.

According to the semiconductor device of the present invention having the above structure, a spare transistor is formed in the second region of the semiconductor substrate, and its wiring is drawn out to at least the (M-1) th wiring layer. By doing so, it is possible to add the second region transistor to the circuit by changing only the mask of the M-th wiring layer. In addition, the first of the semiconductor substrate
It is possible to change only the mask of the M-th wiring layer and change the wiring of the transistor in the first region by drawing out the wiring of the transistor formed in the region of the M-th wiring layer to the M-th wiring layer. is there. Therefore, when there are many wiring layers, it is possible to cope with ECO more easily than before.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same elements are denoted by the same reference numerals and description thereof is omitted. FIG. 1 is a plan view of the semiconductor device according to the first embodiment of the present invention. This semiconductor device has first regions 2, 5, and 8 prepared for forming basic cells for forming a circuit of the semiconductor device at the beginning of design, and spare basic cells around the first region. (Empty basic cells) are included in the second regions 1, 3, 4, 6, and 7. Each basic cell has a predetermined number of transistors.

When a transistor has to be added to the circuit of the semiconductor device due to a design change, a transistor of a basic cell formed in the second region is used. As a result, part of the second area is incorporated into the first area. Conversely, when the transistor of the basic cell formed in the first region is separated from the circuit of the semiconductor device, that part is incorporated in the second region.

FIG. 2 is an enlarged plan view showing a part of the second region of the semiconductor device of FIG. 1, and FIG.
It is sectional drawing in A '. In order to form a spare transistor in the second region, a gate electrode 31 and a gate electrode 31 are formed on the semiconductor substrate 10 via gate insulating films 21 and 22.
32 are formed. In the semiconductor substrate 10 on both sides of the gate electrodes 31 and 32, P-type impurity diffusion regions 11, 1
2, 13 and N-type impurity diffusion regions 14, 15, 16 are formed. These impurity diffusion regions correspond to A in FIG.
Although not present on the -A 'section, the impurity diffusion regions 11, 12, and 13 are shown by dotted lines in FIG.

A first interlayer insulating film 40 is formed on the semiconductor substrate on which the gate insulating film and the gate electrode are formed, and the first interlayer insulating film 40 is formed at a plurality of predetermined positions.
Are provided with openings (contact holes). First wiring layers 51 to 56 are formed on first interlayer insulating film 40 and are connected to a gate electrode and an impurity diffusion region through a contact hole. In FIG. 2, the contact hole is indicated by a single circle with a dotted line.

The wiring 51 included in the first wiring layer is connected to the common gate electrode 31 of the transistors Q1 and Q3,
The wiring 52 is connected to the common gate electrode 32 of the transistors Q2 and Q4. The wiring 53 is connected to the transistor Q1
The drain 11 of the transistor Q3 and the drain 14 of the transistor Q3 are interconnected, and the wiring 54 interconnects the drain 13 of the transistor Q2 and the drain 16 of the transistor Q4. The wiring 55 is a wiring for supplying a high-potential-side power supply voltage _VDD to the P-type impurity diffusion region 12 serving as a common source of the transistors Q1 and Q2. The wiring 56 is a wiring for supplying the low-potential-side power supply voltage V _SS to the N-type impurity diffusion region 15 serving as a common source of the transistors Q3 and Q4. In general, one of the high-potential-side power supply voltage V _DD and the low-potential-side power supply voltage V _SS is set to the ground potential.

On the semiconductor substrate on which the first interlayer insulating film and the first wiring layer are formed, a second interlayer insulating film 60 is formed, and the second interlayer insulating film is formed at a plurality of predetermined positions. An opening (via hole) is provided in 60. Second wiring layers 71 and 72 are formed on the second interlayer insulating film 60, and are connected to the first wiring layer through via holes. In FIG. 2, via holes are indicated by double circles indicated by dotted lines.

At the beginning of the design, the transistors formed in the second region are spare, and the second wiring layers are not connected like the transistors Q1 and Q3. However,
When actually manufacturing a semiconductor device and checking the operation, the circuit that should work in the simulation does not work well or the specification is changed later,
A circuit may need to be added due to a design change. In such a case, the transistor Q2
If the second wiring layers 71 and 72 are connected as shown in Q4 and Q4, they can be used as a part of a circuit.

The wiring 71 included in the second wiring layer connects the wiring 52 connected to the common gate electrode 32 of the transistors Q2 and Q4 to the wiring of the input signal V _IN . The wiring 72 connects the wiring 54 interconnecting the drains of the transistors Q2 and Q4 to the wiring to which the output signal V _OUT is to be supplied. As a result, the transistors Q2 and Q4 form an inverter circuit as shown in FIG. 4, and become part of the circuit of the semiconductor device and are incorporated from the second region into the first region. In the case where the inverter circuit is configured in this manner, the respective sources of the spare transistors are also connected to the high potential side power supply voltage V in the first wiring layer.
It is more convenient to connect in advance to _DD and the power supply voltage V _SS on the low potential side.

As described above, in the second region, if the wiring of the gate electrode of the transistor and the wiring of the impurity diffusion region are extended to at least the first wiring layer, the mask of the second wiring layer which is the upper layer is formed. By changing only one, it is possible to respond to a design change. In this embodiment, the case where the number of wiring layers is two has been described.
The same applies to the case of more than one layer. In general, in consideration of the case where the N wiring layers are present, if the gate electrode of the transistor and the wiring of the impurity diffusion region are led out to at least the (M-1) th wiring layer in the second region, the upper layer is formed. The design change can be dealt with by changing only the mask of the M-th wiring layer. Here, N and M are 2 ≦ M ≦ N
And the M-th layer need not be the uppermost layer.

FIG. 5 is an enlarged plan view showing a part of the first region of the semiconductor device according to the second embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the line BB 'of FIG. FIG. To form a transistor in the first region, gate electrodes 33 and 34 are formed on the semiconductor substrate 10 with gate insulating films 23 and 24 interposed therebetween. Gate electrode 3
In the semiconductor substrate 10 on both sides of the N-type impurity diffusion regions 11, 12 and 13,
4, 15, and 16 are formed. These impurity diffusion regions do not exist on the BB 'section of FIG.
, The impurity diffusion regions 11, 12, and 13 are indicated by dotted lines.

On the semiconductor substrate on which the gate insulating film and the gate electrode are formed, a first interlayer insulating film 40 is formed, and the first interlayer insulating film 40 is formed at a plurality of predetermined positions.
Are provided with openings (contact holes). First wiring layers 55 to 59 are formed on first interlayer insulating film 40, and are connected to gate electrodes and impurity diffusion regions through contact holes. In FIG. 5, the contact hole is indicated by a single circle with a dotted line.

The wiring 57 included in the first wiring layer interconnects the drain 11 of the transistor Q5 and the drain 14 of the transistor Q7. The wiring 58 is connected to the common gate electrode 34 of the transistors Q6 and Q8. The wiring 59 interconnects the drain 13 of the transistor Q6 and the drain 16 of the transistor Q8.
The wiring 55 is connected to the high-potential-side power supply voltage V _{DD through the} P-type impurity diffusion
This is the wiring for supplying The wiring 56 is an N-type impurity diffusion region 1 serving as a common source of the transistors Q7 and Q8.
5 is a wiring for supplying a low potential side power supply voltage V _SS .

On the semiconductor substrate on which the first interlayer insulating film and the first wiring layer are formed, a second interlayer insulating film 60 is formed, and the second interlayer insulating film is formed at a plurality of predetermined positions. An opening (via hole) is provided in 60. Second wiring layers 73 to 75 are formed on the second interlayer insulating film 60, and are connected to the first wiring layer through via holes. In FIG. 6, via holes are indicated by double circles indicated by dotted lines.

The wiring 73 included in the second wiring layer transmits the signal V1 to the common gate electrode 33 of the transistors Q5 and Q7.
Connected to the wiring connected to The wiring 74 connects the wiring 57 (signal V2) connected to the drain 11 of the transistor Q5 and the drain 14 of the transistor Q7 to the wiring 58 connected to the common gate electrode 34 of the transistors Q6 and Q8. The wiring 75 is connected to the transistor Q6
The wiring 59 connected to the drain 13 of the transistor Q8 and the drain 16 of the transistor Q8 is connected to the wiring to which the signal V3 is to be supplied.

At the beginning of the design, it is assumed that the two-stage inverter circuits INV1 and INV2 as shown in FIG. 7 are configured by using all of the transistors Q5 to Q8 formed in the first region. Therefore, transistors Q5 to Q5
8 was connected to the second wiring layer. However, for example, two-stage inverter circuits INV1 and INV2
May need to be deleted later.

When deleting the inverter circuit INV1, the wiring related to the transistors Q5 and Q7 is cut off in the second wiring layer. Instead, the wiring to which the signal V1 is applied is connected to the wiring 58 connected to the common gate electrode 34 of the transistors Q6 and Q8 forming the inverter circuit INV2. Thereby, the transistor Q5
And Q7 are separated from the circuit of the semiconductor device and incorporated from the first region into the second region.

On the other hand, when the inverter circuit INV2 is deleted later, the wiring related to the transistors Q6 and Q8 is cut off in the second wiring layer. Instead, the drain 11 of the transistor Q5 and the transistor Q5
7 (signal V2) connected to the drain 14 of the gate 7
To the wiring to which the signal V3 is to be supplied. As a result, the transistors Q6 and Q8 are separated from the circuit of the semiconductor device, and are incorporated from the first region to the second region.

Therefore, if the gate electrode of the transistor and the wiring of the impurity diffusion region are drawn out to the second wiring layer in the first region, the design can be made by changing only the mask of the second wiring layer. Can respond to changes. In addition,
In the present embodiment, the case where the number of wiring layers is two has been described, but the same applies to the case where the number of wiring layers is three or more. Generally, in the first region, if the gate electrode of the transistor and the wiring of the impurity diffusion region are drawn out to the M-th wiring layer (M is an integer of 2 or more), the mask of the M-th wiring layer is formed. By changing only one, it is possible to respond to a design change.

[0029]

As described above, according to the present invention, even if there are many wiring layers, the specification can be made easier by changing only the masks of some of the wiring layers. Can respond to changes. Therefore, it is possible to shorten the product development period and reduce the development cost.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a part of a second region of the semiconductor device of FIG. 1;

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a circuit diagram showing a circuit configuration of a portion shown in FIGS. 2 and 3;

FIG. 5 is an enlarged plan view showing a part of a first region of a semiconductor device according to a second embodiment of the present invention.

6 is a sectional view taken along line B-B 'of FIG.

FIG. 7 is a circuit diagram showing a circuit configuration of a portion shown in FIGS. 5 and 6;

[Explanation of symbols]

 1, 3, 4, 6, 7 Second region of semiconductor device 2, 5, 8 First region of semiconductor device 10 Semiconductor substrate 11 to 16 Impurity diffusion region 21 to 24 Gate insulating film 31 to 34 Gate electrode 40 1st interlayer insulation film 51-59 1st wiring layer 60 2nd interlayer insulation film 71-75 2nd wiring layer Q1-Q8 Transistor

Claims (4)

[Claims] A semiconductor substrate having a first region and a second region; a plurality of gate electrodes formed on the first and second regions of the semiconductor substrate via respective gate insulating films; An impurity diffusion region formed in the semiconductor substrate on both sides of the gate electrode and forming a plurality of transistors in the first and second regions; and an N layer formed on the semiconductor substrate via an interlayer insulating film. A (M-1) th wiring layer electrically connected to predetermined ones of gate electrodes and impurity diffusion regions of the plurality of transistors formed in the first and second regions through the openings, respectively; A plurality of wirings of a layer and a plurality of layers of an Mth layer electrically connected through openings to predetermined ones of gate electrodes and impurity diffusion regions of a plurality of transistors formed only in the first region. A semiconductor device comprising: the N wiring layers including a number of wirings (N and M are integers having a relationship of 2 ≦ M ≦ N). 2. The method according to claim 1, wherein at least one of the wiring layers from the first layer to the (M-1) th layer electrically connects a source of at least one transistor formed in the second region to a power supply potential or a ground potential. The semiconductor device according to claim 1, further comprising a wiring that is electrically connected. 3. The M-th wiring layer includes a drain of at least one transistor formed in the first region and at least one other transistor formed in the first region.
2. The semiconductor device according to claim 1, further comprising a wiring electrically connected to a gate electrode of the one transistor. 4. A semiconductor substrate having a first region in which a transistor constituting a predetermined circuit is formed and a second region in which a spare transistor is formed, and an interlayer insulating film on the semiconductor substrate. A plurality of wiring layers formed, the plurality of wiring layers being formed in at least one wiring layer and electrically connected to predetermined ones of a gate electrode and an impurity diffusion region of the spare transistor through respective openings. A multi-layered wiring layer including the connection terminal of (1).