JP3019764B2 - Semiconductor integrated circuit device and multi-stage connection structure of its circuit cells - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a multi-stage connection structure of the circuit cells, and more particularly to a standard cell and a gate array type semiconductor integrated circuit device in which circuit cells are arranged and connected between circuit cells. In doing so, the signal input terminal (hereinafter referred to as the input terminal) in the circuit cell
And a signal output terminal (hereinafter, referred to as an output terminal) are formed in different layers on a boundary region between adjacent circuit cells, and are arranged at positions symmetrical with respect to the center line of the circuit cell. The present invention relates to a semiconductor integrated circuit device in which wiring efficiency is improved and delay time is reduced by connecting respective terminals with through holes in a state where the terminals are connected, and a multistage connection structure of circuit cells thereof.

[0002]

2. Description of the Related Art As the miniaturization technology of semiconductor elements advances, the scale of circuits integrated in semiconductor integrated circuit devices of the standard cell and gate array type has been increasing and the operating frequency thereof has also been increasing.

In general, the gate array system is also called a master slice system, in which circuit elements such as transistors constituting logic gates are regularly arranged, and a semiconductor wafer which has been completed up to the official diffusion level is prepared in advance and requested by a user. Thus, a custom semiconductor integrated circuit device is completed through a metal wiring process for configuring the desired circuit function.

Referring to FIGS. 5A and 5B showing an example of the layout outline of the gate array system, an input / output buffer 51 is arranged on a semiconductor chip 50 in a column along the periphery thereof. A peripheral area 52 in which the input / output buffers 56 are arranged in a row along the periphery of the semiconductor chip 55 and a spread type in which an internal area 54 in which the circuit cells 53 are spread all over is provided. When,
There is a continuous column array type in which a plurality of circuit cells 58 are arranged in a row, and an internal area 60 used as a wiring area 59 exists between each row.

[0005] To improve the efficiency of wiring connecting between circuit cells arranged inside these semiconductor path devices;
Various methods have been proposed for reducing the delay in signal propagation between circuit cells. FIG. 6A shows a plan view of the arrangement of input / output terminals of a circuit cell in one example, and FIG. 6A shows a plan view of a state where input / output terminals are connected when the circuit cells are arranged adjacently. Referring to b), in the circuit cell 61, an input terminal 62 and an output terminal 63 are arranged side by side in the horizontal direction near the center of the cell.

On the other hand, a plurality of circuit blocks 61a in which the input terminal 62a and the output terminal 63a are arranged and a plurality of circuit blocks 61b in which the input terminal 62b and the output terminal 63b are arranged, two in FIG. Output terminal 63b and input terminal 62b
The spaces are connected by wiring 64.

[0007]

[SUMMARY OF THE INVENTION In the conventional semiconductor device described above, as shown in FIG. 6 (a) and 6 (b),
Input terminals 62 , 62a , 62b and output terminals 63 , 63
a, 63 b are circuit cells 61 and 61a, are arranged in the interior of 61b, adjacent circuit cells 61a, when connecting a 61b, it is necessary to connect with a wire, the delay time due to the increase in wiring load There is a drawback that the number increases and the wiring efficiency between other circuit cells decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device with improved wiring efficiency and reduced delay time, and a multi-stage connection structure of the circuit cells thereof, in view of the above-mentioned disadvantages. is there.

[0009]

A feature of the semiconductor integrated circuit device of the present invention is that it has a plurality of rectangular circuit cells whose lengths in the Y-axis direction on a plane are equal to each other, and that these circuit cells are In a semiconductor integrated circuit device including a cell row arranged in an array, a signal input terminal and a signal output terminal in the circuit cell are connected to a polycrystalline silicon layer, a first metal layer, and a second metal layer. Formed on at least two of the layers , and on opposite sides of the circuit cell.
At each center, make sure that the edge and the center of the terminal
The cell row is constituted by the arranged circuit cells .

In addition, a plurality of the circuit cells are adjacent to each other.
The signal input terminal and the signal output arranged and adjacent to each other
Overlap the terminals and connect them as one input / output terminal
When operating, each terminal is connected to the first and second terminals.
The through hole connection if the metal layer, or the if the polycrystalline silicon layer and said first or second metal layer contact connection, or the signal input terminal and before
Even if the signal output terminals are overlapped,
If you want to make the contact
Select whether to connect or not depending on the individual status.
Ru can have selective connection means for connecting.

[0011] Features of the multi-stage connection structure of circuit cells of the present invention has a plurality of circuit cells length in the Y-axis direction on the plane it consists of mutually equal square, the Katsuko these circuit cells in an array in multi-stage connection structure arranged and with is composed of cell column comprising these times <br/> path circuit cells connected to the signal input terminal and the signal output terminal between cells, the signal input terminal in the circuit cell and said signal output terminal, a polycrystalline silicon layer, little of the first metal layer and second metal layer
At least two layers and other adjacent layers
Each of the circuit cells on the boundary area with the circuit cell.
At the center of each of the opposite sides of the
Arrange so that the cores are almost coincident with each other.
Superimposing the signal input terminal and the signal output terminal
When operating as a single input / output terminal
If each terminal is the first and second metal layers
The through-hole connection is made with the polycrystalline silicon layer and the
For the first or second metal layer, make contact connection
Or the signal input terminal and the signal output terminal
Before operating individually without interconnecting even when superimposed
Whether there is neither through-hole connection nor the above-mentioned contact connection
So that they can be selected and connected according to individual conditions.
It is to have the structure which was made.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a plan view of an arrangement of input / output terminals of a circuit cell showing a first embodiment of a semiconductor integrated circuit device of the present invention, and FIG. FIG. 3 is a plan view showing a state where input / output terminals are connected with circuit cells adjacent to each other.

Referring to FIG. 1 (a), input terminals 2 and 2 are provided at substantially the center of two opposing sides of a circuit cell 1, respectively.
The output terminal 3 is arranged. The terminals are arranged such that the edges of the circuit cell 1 coincide with the centers of these terminals.

As the circuit cell 1, for example, an inverter 10
Referring to FIG. 2 showing a layout of No. 0, this layout is an example in which the positions of input terminals and output terminals for applying the present invention to the layout example of the known art are changed. In the example of the n-type substrate, a power supply potential line composed of the first metal layer 11a, a ground potential line composed of the second metal layer 11b,
P ⁺ forming the source electrode of a p-channel transistor
Contact 17 connecting diffusion layer to first metal layer 11b
And a contact 16 for connecting the first metal layer 11b to the substrate via an n ⁺ diffusion layer, a P-channel type and a Pw
A contact connecting the polycrystalline silicon layer 13 forming the gate electrode of each n-channel transistor formed in the cell region 14 to the input terminal 2, a p ⁺ diffusion layer forming the drain electrode of the p-channel transistor, and n The contacts 18 and 20 connect the n ⁺ diffusion layers forming the drain electrode of the channel type transistor to the first metal layer 11c, respectively, and connect the first metal layer 11c to the second metal layer 12 and lead to the contact of the output terminal 3. And a contact 21 for connecting the n ⁺ diffusion layer forming the source electrode of the n-channel transistor to the first metal layer 11a and the first metal layer 11a
⁺ Contact 2 connected to P-well via diffusion layer
And 2.

On the other hand, referring to FIG. 1B, for example, circuit cells 1a and 1b as shown in FIG. 1A are arranged adjacent to each other in the X-axis direction. The output terminal 3a of the circuit cell 1a and the input terminal 2b of the circuit cell 1b form an input / output terminal at the center of the adjacent side of the adjacently disposed circuit cell. A contact hole 4 connecting the output terminal 3a and the input terminal 2b is formed at the center.

A feature of the present invention is that, in FIG. 1 , input terminals 2a and 2b in circuit cells 1a and 1b are provided.
When the output terminal 3a, and 3b, circuit cells 1a adjacent to the X-axis direction and 1b of the boundary region to form the input terminal 3a and an output terminal 2b in different layers, it passes through the center of the circuit cell X
This is because it is arranged at a substantially central portion on each of the left and right sides facing each other on the axis .

The circuit cells 1a and 1a adjacently arranged in the X-axis direction
b, the output terminal 3a of the circuit cell 1a and the input terminal 2b of the circuit cell 1b are arranged at the same position in different layers, respectively. 1a and 1b can be connected.

For example, the inverter 100 shown in FIG.
Referring to FIG. 3 which shows a cross-sectional view taken along a cutting line AA when the inverters 100a are arranged adjacent to each other in the axial direction.
And 100b, a polycrystalline silicon layer 13 is formed on a substrate via an oxide film SiO ₂ , and a gate electrode is led to input terminals 2a and 2b.

A first metal layer 11 is formed above the polycrystalline silicon layer 13 via an oxide film SiO ₂ , and a drain electrode is connected to a second metal layer 18 formed thereabove via a through hole 19. I do.

An oxide film Si is formed on the first metal layer 11.
The second metal layer 18 formed via O ₂ is connected to the output terminal 3a.
And 3b respectively.

These inverters 100a and 100
b is arranged adjacent to the output terminal 3 of the inverter 100a.
When connecting a to the input terminal 2b of the inverter 100b, the contact hole 4 is formed to connect the polycrystalline silicon layer 13 derived from the gate electrode of the inverter 100b to the second metal layer 18.

On the other hand, the inverter 100c arranged adjacent to the inverter 100b is an example in which the input terminal 2c is not connected to the output terminal 3b of the inverter 100b. That is, although arranged adjacently, the above-described contact hole 4 is not formed, so that the polysilicon layer 13 and the second metal layer 18 are not connected.

In the above-described example, the input terminal is formed of polycrystalline silicon and the output terminal is formed of the second metal layer. However, by partially changing the layout of the circuit cell, the input terminal is formed of polycrystalline silicon. Obviously, it can be realized by one metal layer or a combination of the first metal layer and the second metal layer.

In the conventional circuit cell, if the input terminal and the output terminal in the circuit cell are located near the center of the circuit cell, the wiring required for connecting the adjacently arranged circuit cells is at least as small as possible. Wiring that is (1/2) × 2 times the size of the circuit cell in the X-axis direction is required, but the present invention does not require it at all.

Therefore, the wiring area required for connecting the circuit cells adjacent in the X-axis direction, which has been required in the related art, is not required, and can be used for connection between other circuit cells.

At the same time, wiring for connection between adjacent cells is no longer necessary, so that a delay time caused by this wiring can be reduced.

On the other hand, regarding connection with other circuit cells,
The connection is made possible by drawing out a wiring formed in the same layer as the output terminal 3a of the circuit cell 1a. When adjacent cells are not connected to each other, the layers forming the input terminal and the output terminal are different from each other.

FIG. 4 (a) shows a circuit cell Le in the second embodiment of the present invention, FIG. 4 (b) circuit adjacent to the Y-axis direction using a circuit cell in the second embodiment This is a semiconductor device to which cells are connected.

Referring to FIG. 4 (a), the circuit cell 5,
Input terminal 6 is a respective central portion to the left side on the two opposite sides in the X axis direction, the input terminal 8 is disposed on the right side, two sides each of the central portion opposite the Y-axis direction input terminal 7 to the upper side there is, the output terminal 9 on the lower side
Is arranged.

On the other hand, referring to FIG. 4 (b), for example, circuit cells 5a and 5b as shown in FIG. 3 are arranged adjacent to the Y-axis direction. At the center of the adjacent side of the adjacently arranged circuit cells 5a and 5b, an output terminal 9a of the circuit cell 5a and an input terminal 7b of the circuit cell 5b are arranged so as to form one input / output terminal. A contact hole 10 for connecting the output terminal 9a and the input terminal 7b is formed at the center.

[0031] It is a feature of the present invention, FIGS. 4 (a)
In FIG. 4 , the input terminal 7 and the output terminal 9 are provided, and in FIG. 4B , the input terminals 7a and 7b and the output terminals 9a and 9b are provided.

In FIG. 4B , by providing input terminals 7a and 7b and output terminals 9a and 9b,
Not only connection of the circuit cells arranged adjacent in the X-axis direction but also connection of the circuit cells 5a and 5b arranged adjacent in the Y-axis direction can be performed only through the through hole 10.

If the input terminal and the output terminal in the circuit cell of the conventional example are located near the center of the circuit cell, the wiring required to connect the adjacently arranged circuit cells is as follows: In the present invention, a wiring length that is at least (1/2) × 2 times the size of the circuit cell in the Y-axis direction is required.

Therefore, similarly to the first embodiment, the wiring area required for connecting the adjacent circuit cells in the Y-axis direction, which is conventionally required, is not required, and the connection between other circuit cells is not required. Can be used for At the same time, it is possible to reduce a signal propagation delay time caused by wiring for connecting cells arranged adjacent to each other.

With respect to connection with another circuit cell, connection can be made by drawing a wiring in the same layer as the output terminal 9a of the circuit cell 5a. When adjacent cells are not connected to each other, the layers forming the input terminals and the output terminals are different from each other.

[0036]

As described above, according to the semiconductor device of the present invention, the input terminal and the output terminal in the circuit cell are formed in different layers on the boundary region between the adjacent circuit cells. Are disposed on two opposite edges on the center line in the X-axis direction and two opposite edges on the center line in the Y-axis direction, and the respective terminals are connected by through holes. This eliminates the need for connection wiring, which has been required in the past, so that high integration can be achieved by improving wiring efficiency, and the signal propagation delay time due to the wiring for connection between circuit cells can be reduced and the speed can be increased. .

[Brief description of the drawings]

FIG. 1A is a plan view showing an arrangement of input / output terminals of a circuit cell according to a first embodiment of the present invention. FIG. 2B is a plan view of a main part in a state where input / output terminals of circuit cells adjacent in the X-axis direction are connected using the circuit cell shown in FIG.

FIG. 2 is a plan view showing an example of a layout of a circuit cell.

FIG. 3 is a cross-sectional view schematically showing a connection state and a non-connection state of an input terminal and an output terminal when circuit cells are arranged adjacent to each other.

FIG. 4A is a plan view showing a circuit cell according to a second embodiment of the present invention. FIG. 5B is a plan view of a main part of the semiconductor integrated circuit device in which adjacent circuit cells in the Y- axis direction are connected using the circuit cell shown in FIG.

FIG. 5A is a plan view of a continuous column array type gate array. (B) It is a top view of a spread type gate array.

FIG. 6A is a plan view showing an example of a conventional circuit cell. (B) is a plan view showing an example of a main part of a circuit cell of a semiconductor integrated circuit device in which circuit cells adjacent in the X-axis direction are connected using conventional circuit cells.

[Explanation of symbols]

1, 1a, 1b, 5, 5a, 5b, 61, 61b Circuit cell 2, 2a, 2b, 6, 6a, 6b, 7, 7a, 7b, 6
2, 62a, 62b input terminals 3, 3a, 3b, 8, 8a, 8b, 9, 9a, 9b, 6
3, 63a, 63b output terminal 4 Contact for connecting metal layer and polycrystalline silicon layer 19 Through hole for connecting metal layer 14 Wiring for connecting circuit cell 50 Gate array of continuous column array type 51, 56 Input / output buffer 52 , 57 Peripheral area 53, 58 Circuit cell 54, 60 Internal area 100 Inverter 100a, 100b, 100c Inverter shown in a schematic sectional view

Claims (3)

(57) [Claims] 1. A semiconductor integrated circuit comprising a plurality of rectangular circuit cells having the same length in the Y-axis direction on a plane, and a cell column in which these circuit cells are arranged in an array. in the circuit device, a signal input terminal and a signal output terminal in the circuit cell, a polycrystalline silicon layer, as well as the form <br/> formed at least two layers of the first metal layer and second metal layer , It on both opposing sides of the circuit cell
At each center, make sure that the edge and the center of the terminal
A semiconductor integrated circuit device , wherein the cell row is constituted by the arranged circuit cells . 2. A plurality of circuit cells are arranged adjacent to each other.
And the adjacent signal input terminal and the signal output terminal
Operate by interconnecting them as one input / output terminal
Is case of the through hole connection if each of terminals said first and second metal layers, the contact connection if the polycrystalline silicon layer and said first or second metal layer, or the Signal input terminal and the signal
Signal output terminals can be operated individually without
If the connection is made, the through hole connection is also the contact connection
Select whether or not to connect according to the individual status
The semiconductor integrated circuit device according to claim 1, wherein the chromatic selection connecting means for. 3. A having a plurality of circuit cells length in the Y-axis direction on the plane consists of mutually equal square, while being constituted by a cell row formed by arranging Katsuko these circuit cells in an array in multi-stage connection structure for a circuit cells connected to the signal input terminal and the signal output terminal between these circuits cells, said signal input terminal and the signal output terminal in the circuit cell,
The polycrystalline silicon layer, the first metal layer and the second metal layer
And forming at least two layers of the inner, adjacent distribution
On the boundary area with other circuit cells
Sides at each center on opposite sides of the circuit cell
Arranged so that the end and the center of the terminal substantially match, and
Each of the signal input terminal and the signal output terminal
Operated by interconnecting as one input / output terminal
When each terminal is connected to the first and second metal
If the layer is a through-hole connection, the polysilicon layer
A contact if the first or second metal layer
Make a connection or the signal input terminal and the signal
Even if output terminals are overlapped,
If you are also the through-hole connections even before Symbol contact connection
Select whether to connect or not depending on the individual status.
A multi-stage connection structure for circuit cells, having a structure as described above .