JPS63311740A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive the improvement of a per area logical integration degree by a method wherein the constitution of a basic cell is composed as a constitu tion consisting of 4 pieces of N-channel MOS transistors sharing a source region or a drain region and 4 pieces of P-channel MOS transistors sharing a source region or a drain region. CONSTITUTION:A basic cell consists of 4 pieces of P-channel MOS transistors 1-4 and 4 pieces of N-channel MOS transistors 5-8. The respective two pieces of transistors out of the respective 4 pieces of the transistors of the same chan nel share the source or both of the source and the drain with the transistors of the other same channel and the respective 2 pieces of the residual transistors share the source or one of the source and the drain with the transistors of the other same channel. By combining efficiently the basic logical element of this logical circuit block in every 8 transistor unit, which is the constitution unit of the element, to form into a circuit pattern, it becomes possible to utilize effectively the transistors being comprised in this basic cell without almost leaving. Thereby, the cell constitution area can be lessened significantly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device, and particularly to a master slice type MOS type semiconductor integrated circuit device typified by a gate array.

2. Description of the Related Art A typical basic element set (hereinafter referred to as basic cell) pattern of a conventional master slice type MOS type semiconductor integrated circuit device, for example, a gate array, has a configuration as shown in FIG. In FIG. 15, 29 and 30 are gate electrodes, 9.10 and 11 are P+ type regions,
14.15 and 16 are N+ type regions, 19 is an N type substrate or N type island region, 20 is a P type island region or P type substrate, 2
1 is an N ten-shaped region, 24 is a P umbrella-shaped region, 28-a to 28-
d is each grid position through which the second layer metal wiring wired vertically in FIG. 15 can pass. In the conventional example basic cell shown in FIG. The repetition pitch width of the basic cell was set to be four grids. (For example, Japanese Patent Publication No. 59-25381) Problems to be Solved by the Invention In this conventional basic cell, the density of transistors with respect to the wiring grid is low, so that The area uniquely depends on the number of transistors constituting the logic circuit. Therefore, when constructing a logic circuit with a large number of transistors, it requires a much larger area than a custom-designed logic circuit with a high transistor density. This was one of the main reasons for the increased area compared to custom-designed chips.

FIG. 16 shows an example of a pattern in which a conventional basic cell is used to improve transistor density.

The basic cell shown in FIG. 16 has a shortened configuration from the basic cell shown in FIG. 15 by removing the N medium size region 21 and the P raw type region 24. In the configuration of the basic cell shown in FIG.
Compared to the basic cell configuration shown in the figure, the transistor density is 4/
It has tripled. However, on the other hand, with the basic cell configuration shown in FIG. 16, automatic placement and wiring of logic circuits may become difficult. Two-person NAND and two-person NAND are the basic logic gates most frequently used in general logic circuits.
Although there is an OR, these logic circuits can be constructed with one basic cell as shown in FIG. However, two-man powered NAND gates and two-man powered NOR gates each have a total of three input/output terminals, two inputs and one output, and in order to automatically wire these, it is necessary to 3 with second layer metal wiring
It is necessary to form a terminal. On the other hand, in the basic cell shown in FIG. 6, one basic cell width is three grids of second-layer metal wiring, and when a two-manpower NAND gate or a two-manpower NOR gate is formed with one basic cell, All the grids that can be wired in the second layer metal wiring will be used up for the logic circuit gate self-excitation line, which is necessary when wiring between logic circuits using automatic wiring, because it passes over the same logic circuit. Since there is no empty space (feed-through area) for automatic wiring, automatic wiring becomes difficult when these logic circuit gates are arranged consecutively. Due to these drawbacks, the basic cell shown in FIG. 16, in which the transistor density is improved while maintaining the conventional basic cell configuration, has problems in practical use.

The present invention is intended to solve these problems, and aims to provide a master slice type basic cell that enables an increase in logic integration per area and is easy to apply automatic wiring.

Means for Solving the Problem In order to solve this problem, the present invention changes the structure of the basic cell to four cells sharing a source region or a drain region.
N-channel MOS transistors and four P-channel MOS transistors that share the source or drain region
This is a transistor.

Effect: With this configuration, when realizing a logic circuit with a gate array, the logic integration degree is improved and mask patterning becomes possible with a smaller area.

Embodiment FIG. 1 is an equivalent circuit configuration diagram of a basic cell of a master slice type semiconductor integrated circuit device according to an embodiment of the present invention. This basic cell consists of four P-channel type MO8 transistors and four N-channel type MOS transistors. Of the four co-channel type transistors, two of each transistor share both their sources or drains with other co-channel type transistors, and the remaining two transistors each share their sources or drains with other co-channel type transistors. One of the drains is shared with another same channel type transistor. In addition, four N-channel type M
The gate electrode of the OS transistor and each of the gate electrodes of the four P-channel type MOS transistors are connected to each other.
be independent.

FIG. 2 is a plan view of an impurity implantation region pattern and a gate electrode pattern that realize the basic cell shown in FIG. 3 is a sectional view taken along line AA' in FIG. 2, and FIG. 4 is a sectional view taken along line BB' in FIG. 2.

In Figures 1, 2, 3 and 4, 1.2
．． 3 and 4 are gate electrodes of P-channel type MOS transistors, and 5.6.7 and 8 are gate electrodes of N-channel type MOS l-transistors. Also, 9.
10.11. ．． Reference numerals 12 and 13 indicate P medium-sized regions, which serve as the source and drain of the P-channel MOS transistor, and 14°, 15, 16, 17, and 18 indicate N+-type regions, which serve as the source and drain regions of the N-channel MOS transistor. 19 is the P-channel type MOS
N-type substrate or N-type island region (
20 is the N-channel type MOS
A P-type island region (P-well) or a P-type substrate in which a transistor is formed.

Further, 21 and 22 are N+ type regions formed in the N type substrate or the N type island region 19, and 23 and 2
4 is a P-type island region or a P-medium region formed within the P-type substrate 20; These are formed with the main purpose of preventing latch-up due to the P0N PN0 parasitic thyristor existing between the source of the P-channel MOS transistor and the source of the N-channel MOS transistor. By connecting the regions 21 and 22 to the VOO potential and the P+ type regions 23 and 24 to the Vss potential, the substrate potential of each substrate or island region is stabilized and serves as latch-up prevention means. 25 is a gate insulating film made of silicon dioxide 5i02, for example, and 26 is a field P! made of silicon dioxide as well. It is the lamina.

Further, 27 is an N-type or P-type silicon substrate.

This basic cell is arranged regularly on - semiconductor chips.
They are arranged in a so-called array. FIG. 5 shows a state in which two basic cells are arranged and lined up in the X direction of the paper, and in FIG.
28-d and 28-e indicate grid positions through which the second layer metal wiring, which is routed in the Y direction of the paper, can pass. As is clear from the figure, this basic cell
The width of the repeated arrangement of basic cells is set to be five wiring grids of layered metal wiring. The transistor density per wiring grid of the second layer metal wiring is '-”-= 1, 6
(transistor/wiring grid), and the transistor density in the typical basic 2+2 cell configuration of the conventional example shown in FIG. It has doubled. Therefore, the transistor integration degree per unit area can be improved by a maximum of 1.6 times. The features of this basic cell will be explained below using specific examples.

This basic cell exhibits its superiority particularly when forming a logic circuit pattern into a logic block having a large number of constituent transistor elements. When patterning a logic block, the following various combinations of basic logic elements can be realized with one unit of this basic cell.

1) Combination of two of the two-man powered NAND gate and two-man powered NOR gate and inverter. (In addition to the inverter with the minimum number of elements, you can also select one in which two sets of the minimum number of elements are configured in parallel.) 2) Combination of 3-man power NAND or 3-man power N0R and 1 inverter. .

3) One 4-person NAND or 4-person NOR.

4) 3 inverters. (One of the three can also be configured with two parallel configurations of the minimum number of elements.

) 5) Two clocked inverters.

6) Four sets of transfer gates that share each other's sources or drains.

FIGS. 6 to 13 show representative examples of transistor circuit configurations among the combinations of the above-mentioned basic logic elements.

FIG. 6 shows an example of the configuration of two NANDs powered by two people. Figure 7 shows one two-man NAND and two with the minimum number of elements.
This is a configuration example of a combination of one inverter configured in III parallel configuration. FIG. 8 shows a configuration example of a combination of one two-man powered NAND and one two-man powered N0R. FIG. 9 is a configuration example of a combination of one three-man power NAND and one inverter. FIG. 10 shows a configuration example of a four-person NAND. FIG. 11 shows a configuration example of a combination of two inverters with the minimum number of elements and one inverter in which two sets of the minimum number of elements are configured in parallel. This is an example of a configuration. FIG. 13 shows an example of the configuration of four sets of transfer gates that share a mutual source or drain.

When patterning a logic block, by skillfully selecting the combination of basic logic elements that can be configured in one basic cell, it is possible to effectively utilize almost all the transistors included in the basic cell. The degree of integration is dramatically improved compared to the case where logic cells are formed using typical basic cells of the conventional example as shown in FIG. -For example,
An example of circuit patterning of a D-flip 70 tube (hereinafter abbreviated as D-F, F) will be explained in detail. In Figure 14,
An example of the circuit configuration of DF and F with buffer output is shown. This D-F, F is composed of a total of 30 transistors. If this is configured with the basic cells of the conventional example,
7.5 basic cells were required, and the basic cell configuration area was equivalent to 7.5×4=30 grids in the number of second-layer metal wiring grids. This flip-flop (F, F
, ) is formed into a circuit pattern using the basic cells of this embodiment, each set of basic logic elements within the frame surrounded by the dotted line in FIG. 14 can be configured with one basic cell. More specifically, two circuits shown in FIG. 11 and one circuit each shown in FIGS. 12 and 13 may be combined to form a circuit pattern. Therefore, in the basic cell of this example, the number of metal wiring grids for the second WJ is 2 for 4 cells.
It is possible to form a circuit pattern with an area corresponding to 0 grids. This means that the cell area has been reduced to 2/3 (=20/30) compared to the conventional one, and in terms of the degree of integration, it has been improved by 1.5 times.

In this way, by skillfully combining the basic logic elements of the logic circuit block in units of 8 transistors, which are the constituent units of the basic cell of this embodiment, to form a circuit pattern,
It is possible to effectively utilize almost all of the transistors included in this basic cell, and the cell configuration area can be significantly reduced compared to the conventional example. Generally, the larger the scale of the logic circuit, the higher the usage rate of F, F, and there is a tendency to use large-scale logic circuit blocks in MSI, megacell, etc. more frequently. Even in master slice type semi-custom LSIs such as gate arrays, it will become increasingly important to support circuits with higher logic integration scale.

Therefore, the basic cell of the present invention, which allows large-scale logic circuits to be realized in a smaller area among F, F, MSI, etc., is
It is thought that its superiority over conventional examples will increase even more significantly in the future.

Furthermore, when using the basic cell of the embodiment of the present invention, the first
There is no shortage of feedthrough for automatic wiring, which was a problem with the conventional cell configuration shown in FIG. When a logic circuit is formed using the basic cells of the embodiments of the present invention, the number of feedthroughs is significantly reduced due to F, F, MSI, etc.
These logic circuits have a small number of people and outputs compared to the number of constituent transistors, and even if the number of feedthroughs is reduced in these logic circuits, the number of feedthroughs necessary for automatic wiring can still be sufficiently secured. On the other hand, two-man NAND and two-man NOR, which are the most commonly used logic circuits and have the largest number of output terminals relative to the number of constituent transistors, are made into logic circuits using the basic cells of the embodiments of the present invention. In this case, two feedthroughs are ensured per one logic circuit.When considering automatic wiring at the one-chip level, the total number of feedthroughs required for automatic wiring depends on the total number of lines in the chip.Experience So, the feedthrough actually used in automatic wiring is around 0.5 wires per wire, and the average feedthrough per chip is 1 wire.
If one or more feedthroughs per wire exist almost evenly within the chip, no unwired wires will occur due to insufficient feedthroughs, and there will be little increase in wire length due to failure detours.

The total number of wires in one chip is approximately equal to the number of input terminals of all the logic circuits included in the chip, so in various logic circuits, there are at least as many feedthroughs as the number of input terminals of each logic circuit. It can be said that a condition for application of automatic wiring is that a large number of secured logic circuits are used within a chip. If the basic cell of the embodiment of the present invention is used, the two-manpower logic gate, which is used most frequently on logic circuits, will optimally satisfy this condition. Furthermore, when various logic circuits created using the basic cells of the embodiments of the present invention are used at the statistical rate of general logic circuits, the chip average feedthrough is around 2 wires per wire, and the automatic wiring fully meet the necessary conditions.

As described above, by using the basic cell of the embodiment of the present invention, the degree of integration of mask patterning for the entire logic circuit can be improved without impairing the degree of freedom of automatic wiring, and LSI can be realized with a smaller chip area than before. It becomes possible.

Effects of the Invention As described above, according to the present invention, a master slice type semi-custom LSI can be realized with a smaller chip area than before, and logic circuits with higher logic integration can be integrated into an LSI with an appropriate chip size. As a result, an effect such as cost reduction can be obtained.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit configuration diagram of a basic cell of a master slice type semiconductor integrated circuit device according to an embodiment of the present invention, and FIG.
The figure is a plan view of the basic cell pattern, Figures 3 and 4 are cross-sectional views taken along lines AA' and B-B' in Figure 2, and Figure 5 is the basics of the embodiment of the present invention. The patterns illustrating the arrangement of cells: Heisei-shigo, SaiU-Ko+9n/Ko-Nao+0Ko-Haikuso-Ko-HalflIJ diagram, FIGS. 11, 12, and 13 are the unit basic cells of the embodiment of the present invention. Typical examples of combinations of basic logic elements that can be formed and their circuit configuration diagrams. Figure 14 is a circuit diagram of D-F and F with output buffers. Figures 15 and 16 are representative of conventional gate arrays. FIG. 2 is a plan view showing a basic cell configuration. 1.2, 3.4... Gate electrode of P channel transistor, 5.6, 7.8... Gate electrode of N channel transistor, 9, 10.11, 12゜1.
3...P+ type region that becomes the source or drain of the P channel transistor, 14, 15.16° 17.
18...N+ type region that will become the source or drain of the N-channel transistor 19...N-type substrate or N-type island region forming the P-channel transistor, 20...N P-type island region or P-type substrate forming channel transistor, 21.22...N
The N+ type region formed within the type substrate or N type island region is
3.24...P type island region or P+ type region formed in the P type substrate, 25... Gate insulating film,
26...Field insulating film, 28°28-a,
28-b, 28-c, 28-d, 28-e...
Vertical wiring grid position of second layer metal wiring, 29.3
0...Gate electrode. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 3 Figure 6 + a) c-26 2) Figure 9 (Figure 1 Figure 11 Figure 14N (b)

Claims (3)

[Claims] (1) The basic element set constituting the desired logic circuit gate consists of four N-channel MOS transistors that share a source region or drain region and four P-channel MOS transistors that share a source region or drain region. A semiconductor integrated circuit device comprising: (2) The semiconductor integrated circuit device according to claim (1), wherein the gate electrode of the N-channel MOS transistor and the gate electrode of the P-channel MOS transistor constituting the basic element set are electrically independent. . (3) A P-type substrate that forms an N-channel MOS transistor in the basic element set, or an N-type substrate or an N-type island that has a P^+ type region within a P-type island region and forms a P-channel MOS transistor. The region has an N^+ type region, and the P^+ type region and the N^+ type region are located between the N channel MOS transistor and the P channel MOS transistor in the basic element set, or between the N channel MOS transistor and the N channel MOS transistor. Next to the terminal outlet of the gate electrode and P
A semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed near a terminal outlet of a gate electrode of a channel MOS transistor.