JP2540222B2 - Integrated circuit - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to a basic cell and an array structure of basic cells,
In particular, the present invention relates to an integrated circuit suitable for increasing the degree of freedom in circuit design and realizing circuit miniaturization (compactness) when realizing an SOG (Sea Of Gates) type large-scale integrated circuit (LSI).

[Prior art]

Conventionally, in the SOG type semiconductor device, a technique relating to basic cells arranged on a master chip is disclosed in, for example, Japanese Patent Laid-Open No.
There is one disclosed in Japanese Patent Publication No. 44859. In the basic cell in this publication, as shown in FIGS. 9A and 9B, the gate electrodes 10 and 12 are separated from each other,
P-channel MOS (hereinafter abbreviated as PMOS) type transistors 14A and 14B of the first conductivity type transistor group (first basic cell) 16 and N-channel MOS (hereinafter abbreviated as NMOS) type transistor A second conductivity type transistor group (second basic cell) 20 composed of 18A and 18B is formed, and the first and second basic cells 16 and 20 are connected to the source region 22.
The structure has a bilaterally symmetrical shape with center lines A and B crossing A, 22B, the gate electrodes 10, 12 and the drain regions 24A, 24B as the center. Further, the basic cell has the same structure as the basic cells 16 and 20 shown in FIGS. 9A and 9B as shown in FIGS.
The basic cells 32, 34 composed of PMOS type and NMOS type transistors having a bilaterally symmetrical structure about lines A, B crossing the source regions 26A, 26B, the gate electrodes 28A, 28B and the drain regions 30A, 30B. It has been known. The basic cells 16, 20, 32, 34 are arranged on a chip with each one of the basic cells 16, 32 made of PMOS type transistors and the basic cells 20, 34 made of NMOS type transistors as a constituent unit. . When arranging this basic cell in SOG,
For example, as shown in FIG. 11, basic cells of the same type are arranged in the vertical direction to form basic cell rows 36A and 36B.
36A and 36B were arranged alternately in the lateral direction with no space. In FIG. 11, reference numeral 39 is a chip. When wiring the basic cell columns arranged on the chip as described above in a channel-free arrangement to form a logic gate or a logic block, as shown by reference numeral 38 in FIG. 11, the basic cell columns 36A, 36B are formed. In the vertical direction, wiring was carried out with a pitch for one basic cell.

[Problems to be achieved by the invention]

However, in the conventional chip, like the basic cell row 36A, 36B, since the cell row is formed by arranging basic cells symmetrical only in the left-right direction, with respect to the arrangement direction of the cell row, It is impossible to construct the same logic gate or logic block in the vertical direction of the cell row. Therefore, some of the basic cells in the cell row are not used,
There is a problem that the space on the chip is wasted. Furthermore, in the configuration of the logical block on the chip, if the available area on the chip assigned to the logical block is restricted in shape, if the logical block can be configured in the direction perpendicular to the cell row arrangement direction. Although it is feasible on the utilization area, there is a case where the configuration of the logic block becomes impossible due to the limitation on the shape. The present invention has been made in view of the above conventional problems, and by providing a basic cell that can be used vertically and horizontally symmetrically, it is possible to reduce the number of unused basic cells and achieve high integration. An object of the present invention is to provide an integrated circuit capable of increasing the degree of freedom in circuit design.

[Means for achieving the object]

The present invention is directed to a diffusion region having a vertically and horizontally symmetrical shape, and a gate formed on the diffusion region along a radiation centered on a center point of a gate formation surface of the diffusion region, and in the vicinity of the center point. An electrode, each section of the diffusion region separated by the gate electrode has a plurality of basic cells alternately serving as a source region and a drain region, and a plurality of P channels and N channels are provided. The above problem is achieved by arranging the basic cells so that the basic cells of the P-channel and the N-channel are alternately located above and below and to the left and right.

Actions and effects of the present invention

In the present invention, the diffusion region is vertically and horizontally symmetrically formed, and the gate electrode is formed on the radiation centered on the center point of the diffusion region with the vicinity of the center point being removed, and separated by the gate. Each section of the diffusion area is alternated with the source area,
The drain region is used. Therefore, it is possible to obtain the above-mentioned effects, and further, depending on how the gates are selected and how they are combined, the transistors and the like formed in the basic cell can be configured in parallel and series,
For example, 7-input NAND or NOR can be configured with one basic cell pair. Therefore, it is possible to obtain an excellent effect that the degree of integration is increased and the degree of freedom of design is further expanded. Further, in the present invention, in the basic cell array structure, the basic cells of vertically and horizontally symmetrical P-channel and N-channel are arrayed so that the P-channel and N-channel are alternately located vertically and horizontally. Therefore, the same logic gate and logic block symmetrically configured in the left-right direction or the up-down direction are provided in the vertical direction,
It can be arranged vertically or vertically. Therefore, the degree of freedom in circuit design is increased, the unused area of the gate is reduced, and the circuit can be downsized. As a result, the chip area can be reduced and the degree of integration of the semiconductor device can be increased. Further, if the direction is changed to a right angle direction, a logic block which can be configured on a predetermined chip area can be realized, and an excellent effect that the cost at the time of installing and manufacturing a semiconductor device can be reduced can be obtained.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the first embodiment will be described. This first embodiment shows the basic idea of the present invention, and is a comparatively basic content of the present invention.
In this embodiment, as shown in FIGS. 1 and 2, a basic cell 40, N consisting of a P-channel MOS (PMOS) type transistor is used.
A basic cell 42 composed of a channel MOS (NMOS) type transistor, which is a diffusion region 44, 46 having a vertically and horizontally symmetrical shape.
And the center lines A1, A2, B1, which are vertically and horizontally symmetrical with respect to the diffusion area,
The gate electrodes 48 and 50 formed on B2, and the diffusion regions 44 and 46 divided by the gate electrodes 48 and 50 are alternately divided into source regions 52A and 52B and drain regions 54A and 54B.
It is a basic cell that is said to be. The diffusion regions 44 and 46 have a square shape, and the gate electrodes 48 and 50 on the center lines of the diffusion regions 44 and 46 have the same length in the longitudinal direction. Therefore, the basic cell according to the first embodiment constitutes PMOS type and NMOS type transistors in the vertical and horizontal directions of the gate formation surface of the diffusion region. Therefore, the basic cell
Since 40 and 42 can be used vertically and horizontally symmetrically, the degree of freedom in circuit design is increased and the unused area of the gate is increased as compared with the conventional basic cell in which the logic gate can be formed only in the vertical direction of the cell column. It is possible to reduce the size and make the circuit compact. Next, a second embodiment will be described. In this second embodiment, as shown in FIG. 3, a basic cell 40 consisting of the PMOS transistor of the first embodiment and a basic cell 42 consisting of an NMOS transistor are arranged on the chip in the vertical and horizontal directions. It has an array structure in which they are arrayed alternately. When a logic block is formed by using the above-mentioned chip, for example, six basic cells, broken lines 56A, 5A in FIG.
As shown in 6B, the logic block can be configured in both horizontal and vertical directions. Therefore, it is understood that the degree of freedom in circuit design is increased, the unused area of the basic cell is reduced, and the circuit can be miniaturized. As described above, from the six basic cells, for example, a 3-input NAND gate can be configured. In the first and second embodiments, the diffusion regions 44 and 46 of the basic cells 40 and 42 are formed in a square shape, but the shape of the diffusion region when implementing the present invention is limited to a square shape. However, the diffusion regions can be formed in other shapes as long as they are vertically and horizontally symmetrical. For example, the diffusion area can be formed in a circular shape. Next, a third embodiment will be described. The third embodiment is a basic cell 60 composed of a PMOS type transistor and a basic cell 62 composed of an NMOS type transistor as shown in FIGS. The diffusion regions 64 and 66 are formed on the diffusion regions 64 and 66 along the radiation 1 centered on the center point Q of the gate formation surface of the diffusion regions 64 and 66, and in the vicinity of the center point Q. And the gate electrodes 68 and 70,
Each of the diffusion regions separated by 70 is alternately a source region (denoted by a symbol S) and a drain region (denoted by a symbol D).
It is a basic cell that is said to be. In the embodiment, the diffusion regions 64 and 66 have an octagonal shape as shown in FIGS. 5 (A) and 5 (B). The gate electrodes 68 and 70 have the same length in the longitudinal direction. Therefore, the basic cells 60 and 62 according to the third embodiment sandwich the gate electrodes 68 and 70 to form PMOS type transistors and NMOS type transistors in the circumferential direction, respectively. Therefore, since the basic cells 60 and 62 can be used vertically and horizontally symmetrically, the degree of freedom in circuit design is increased and the unused area of the gate is reduced as in the first embodiment. At the same time, depending on the selection and combination of the gate electrodes 68 and 70 to be connected, parallel and series connection of the transistors which cannot be formed in the first embodiment can be formed. For example, in the following fourth embodiment, it becomes possible to construct a relatively complicated circuit as shown in FIGS. 6 and 7. As a result, the degree of integration is increased and the degree of freedom in design is further increased as compared with the first embodiment. Next, a fourth embodiment will be described. In the fourth embodiment, the basic cell 60 composed of the PMOS type transistor of the third embodiment and the basic cell 62 composed of the NMOS type transistor are arranged on the chip in the vertical direction as shown in FIG. And an array structure in which they are arrayed alternately in the left-right direction. FIGS. 6 and 7 show an example of a circuit using the chips having the above-described arrangement structure, for example, each including two basic cells as a pair. FIG. 6 shows a pair of basic PMOS transistor cells 60.
And an inverter circuit constituted by a basic cell 62 of an NMOS type transistor. As shown in FIG. 6, this inverter circuit has an input Input1 connected to the gate electrodes 68 and 70 of a pair of basic cells 60 and 62 arranged in the horizontal direction, and an output Outp.
ut1 is connected to the drain D adjacent to the gate electrodes 68 and 70. Further, this inverter circuit is not limited to being composed of the basic cell pair 60 and 62 in the vertical direction, and is also composed of a pair of basic cells 60 and 62 arranged in the horizontal direction as shown by the broken line in FIG. can do. Note that no matter which basic cell pair 60 and 62 arranged in the vertical direction or the horizontal direction is selected, the output Outp will be output for each input Input1 and Input2.
ut1 and 2 indicate equivalent inverter outputs. Further, as shown in FIG. 7, a pair of basic cells 60, 62
The input NOR can be configured. As shown in FIG. 7, the NOR circuit includes gate electrodes 68 and 7 of each basic cell 60 and 62.
7 of 0 become input terminals Input1 to 7, and the drain D next to Input7 of the PMOS transistor basic cell 60 is Outp.
A wiring 72 connected to ut and having all drains D of the NMOS type transistor basic cell 62 made of, for example, aluminum.
Is connected to the output Output, and the power supplies Vdd and Vss of the circuit are applied to the source S adjacent to Input1. It should be noted that the 7-input NOR can be configured by selecting any of the basic cell pairs 60 and 62 arranged in the vertical direction and the horizontal direction. From the above, in the basic cell structure according to the fourth embodiment, the basic cells 60 and 62 used in the basic cell structure are laterally arranged,
Since the gate electrodes 68 and 70 are extended not only in the vertical direction but also in the oblique direction, it is understood that the degree of freedom in circuit design is further increased as compared with the second embodiment. In addition, in the second embodiment, for example, 3 inputs are made with 6 basic cells.
Although it was possible to configure the NAND gate, in contrast to this, the fourth
In the embodiment, it is possible to configure up to 7-input NOR with a pair of (2) basic cells. Therefore, the fourth embodiment is the same as the second embodiment.
The degree of freedom in design is further increased as compared with the embodiment, and the miniaturization and integration of the semiconductor integrated circuit chip structure can be improved. In the third and fourth embodiments, eight gate electrodes 68 and 70 provided in the basic cells 60 and 62 are formed around the center point O as shown in FIG. The gate in the case of performing is not limited to this, and any number of gates may be used as long as they are arranged along the radiation 1 centered on the center point. For example, as shown in FIGS. 8 (A) and 8 (B), a basic cell 78 of a PMOS transistor, an NMOS having four gates 74 and 76 excluding the central junction point of the gate electrode of the first embodiment. A basic cell 80 of a type transistor can be formed. In FIG. 8, reference numerals 82 and 84 are diffusion areas. In addition, in the third to fourth embodiments, the diffusion regions 64 and 66 of the basic cells 60 and 62 are formed in an octagonal shape, but the diffusion region shape when the present invention is implemented is as follows. The diffusion region is not limited to the octagonal shape, and the diffusion region can be formed in any other shape as long as it is vertically and horizontally symmetrical. For example, the diffusion region can be formed in a square shape, a regular hexagonal shape, or a circular shape.

[Brief description of drawings]

1 and 2 are plan views showing the configuration of a basic cell according to the first embodiment of the present invention, and FIG. 3 is a plan view showing an array structure of the basic cell according to the second embodiment of the present invention. FIG. 4 is a plan view showing an example of forming a logic block on a chip for explaining the operation of the second embodiment, and FIG. 5 shows a basic cell according to the third embodiment of the present invention. FIG. 6 is a plan view showing a configuration, FIG. 6 is a plan view showing an example of a logic circuit formed by a basic cell pair according to a fourth embodiment of the present invention, and FIG. 7 is a plan view showing another example of a logic circuit. FIG. 8 is a plan view showing a configuration example of another basic cell embodying the present invention, FIGS. 9 (A) and (B) are plan views showing a configuration example of a conventional basic cell, FIG. (A), (B) is a plan view showing another configuration example of a conventional basic cell, FIG. 11 is a plan view showing an arrangement state of the conventional basic cell. 40 …… Basic cell consisting of PMOS transistor, 42 …… Basic cell consisting of NMOS transistor, 44,46 …… Diffusion region, 48,50 …… Gate electrode, 52A, 52B …… Source region, 54A, 54B …… Drain Area, 56A, 56B ... Logic block, 60, 78 ... Basic cell of PMOS transistor, 62, 80 ... Basic cell of NMOS transistor, 64, 66 ... Diffusion area, 68, 70, 74, 76 ... … Gate electrodes, 72… wiring.

Front page continuation (72) Inventor Takahiro Yamamoto 2-3 2-3 Uchisaiwaicho, Chiyoda-ku, Tokyo Kawasaki Steel Co., Ltd. (56) Reference JP-A-57-35367 (JP, A) JP-A-64-89537 (JP, A) Actual Kaihei 1-160859 (JP, U)

Claims (1)

(57) [Claims] 1. Vertically and horizontally symmetrical diffusion regions, and radiation regions centered on the center point of the gate formation surface of the diffusion region, and formed on the diffusion region in the previous period excluding the vicinity of the center point. A gate electrode, and each partition of the diffusion region partitioned by the gate electrode,
A plurality of basic cells alternately serving as a source region and a drain region are provided, and a plurality of the basic cells of P channel and N channel are provided.
An integrated circuit in which basic cells of the P-channel and N-channel are arranged alternately in the upper, lower, left and right directions.