JPH02181949A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form an SRAM by using one basic cell and to enhance a usable efficiency of a basic cell by a method wherein an n-channel transistor region is added to the basic cell. CONSTITUTION:Another n-channel transistor region 3 provided with newly added n-channel transistors n3, n4 is formed at a side-end part of an n-channel transistor region 2. A prescribed Al wiring operation is executed by using this basic cell and an SRAM is formed; then, six latch circuits 62 are constituted of a p-channel transistor region 1 and the n-channel transistor region 2; switches TN1, TN2 are formed individually of the two n-channel transistors n3, n4 which are situated at the side-end part of the n-channel transistor region 2. Accordingly, one SRAM unit can be formed of one basic cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit manufactured by applying a mask slicing method consisting only of basic cells.

[Conventional technology]

Conventionally, there has been a method called a mask slicing method in producing semiconductor integrated circuits.

This mask slicing method creates a cell block (basic cell row) by arranging multiple basic cells consisting of multiple transistors in one semiconductor chip, and then uses a wiring mask created according to the product type. The aim is to complete an LSI that achieves the desired operation by performing processing to connect transistors of basic cells.

FIG. 2 shows a plan view of a chip representing a general LSI pattern created by applying this mask slicing method.

In FIG. 2, a bonding pad 17 area and an ElO cell 18 area are present in the periphery of the tube 16, and basic cell rows 50 formed by connecting basic cells 19 are arranged at regular intervals inside the chip. has been done. The space between these cells is used as a wiring area.

The basic cell 19 is a unit element for obtaining a desired logic function, storage function, etc., and the I10 cell 18 is a logic level conversion circuit between inside and outside the integrated circuit, and a buffer for increasing driving capacity. This is a group of elements for configuring the . and,
The bonding pad 17 is a pad for connecting the internal circuit and the envelope terminal.

As a conventional example of a specific layout of the basic cell 19, there is one described, for example, in Japanese Patent Laid-Open No. 62-256468.

The planar shape of the specific layout of the basic cell in this conventional example is shown in FIG. 3 and will be explained.

In FIG. 3, 1 is a p-channel transistor region;
2 indicates an n-channel transistor region, and these two regions are formed as a pair.

In this p-channel transistor region 1, p-channel transistors P+, Pz are formed, and in the n-channel transistor region 2, an n-channel transistor nI+nZ is formed. Furthermore, 5 is a polysilicon gate electrode of a P-channel transistor;
8 indicates the polysilicon gate electrode of the n-channel transistor.

In the conventional mask slicing method, the basic cells shown in FIG. 3 are arranged in the basic cell row 50 shown in FIG. is forming.

[Problems to be Solved by the Invention] A plan view of an SRAM (static random access memory) constructed using the basic cell shown in FIG. 3 above will be described with reference to FIG. 4.

The RAM cells are 19-1 arranged adjacent to the basic cell row 50.
It is composed of three basic cells: 1.19-2.19-3. Of these, R
One bit of AM cell is formed.

By the way, for one bit of a RAM cell, a plurality of pass transistors, which are gates serving as switch parts, are required. Therefore, it is necessary to construct a pass transistor using an n-channel transistor in the basic cell. Therefore,
Two elementary cells 19-1, 19-3, on both sides of elementary cell 19-2, n-channel transistors 70.
71 will be used to configure a pass transistor,
In this case, a total of six p, n-channel transistors present in basic cell 19-1, 19-3 are wasted.

The memory circuit area on the chip occupies a large area. When creating an SRAM using basic cells as described above, if a plurality of p, n-channel transistors are wasted as shown in FIG. The area becomes relatively large, and the area occupied by the logic circuit area becomes correspondingly small. Therefore, there are problems in that it is not possible to obtain a high integration density and it is not possible to obtain a high-performance semiconductor integrated circuit.

Therefore, in order to solve such unresolved problems, the present invention aims to provide a high-performance semiconductor integrated circuit that can achieve high integration density by improving the usage efficiency of basic cells. shall be.

[Means to solve the problem]

In order to solve the above object, the present invention provides a basic cell row in which a plurality of basic cells in which a p-channel transistor region and an n-channel transistor region are formed as a pair are arranged in a matrix; A semiconductor integrated circuit comprising an input/output cell and a plurality of bonding pads, characterized in that an n-channel transistor region is further added to the basic cell.

[Effect]

When a semiconductor integrated circuit is fabricated by the mask slicing method using the basic cell of the present invention, the SRAM pass transistor can be fabricated using an n-channel transistor added integrally with the basic cell.

Therefore, it is possible to create an SRAM using one basic cell. As a result, R as shown in FIG.
This eliminates wasted area of the AM cell, improves the usage efficiency of the basic cell, and also reduces the area occupied by the memory area on the chip, resulting in a correspondingly higher integration density. , it becomes possible to obtain a high-performance semiconductor integrated circuit.

〔Example〕

Next, an embodiment of the semiconductor integrated circuit according to the present invention will be described.

FIG. 1 shows a plan view of a basic cell used in this embodiment. Note that the explanation of the same parts in FIG. 1 as those explained in FIG. 3 will be omitted.

In FIG. 1, a newly added n-channel transistor n is located at the side end of the n-channel transistor region 2.
Another n'-channel transistor region 3 having 3+14 is formed. Note that reference numeral 2 indicates a polysilicon gate electrode of an n-channel transistor, 14 a diffusion layer for an n-substrate contact, and 15 a diffusion layer for a p-substrate contact.

Using the basic cell shown in FIG. 1, predetermined AI wiring was applied to create an SRAM. FIG. 5 shows a plan view of a basic cell provided with this AI wiring. In FIG. 5, the hatched portion 24 indicates the −th layer AI wiring, and the 25
shows the 2N-port AI wiring. Further, 21 is a peer hole, and 22 is a contact hole. In addition, 20
23 indicates a p-substrate contact, and 23 indicates an n-substrate contact.

Also, V,,,V. , indicates a power supply connected to the diffusion layer portion of the basic cell.

FIG. 6 is an equivalent circuit of FIG. 5. This figure 6 shows the SR
This shows the configuration of an AM unit element, and a latch circuit 62 is formed by connecting two inverters 60 and 61 in a ring shape.

In the SRAM element shown in Fig. 6, when the WORD line is set to high level, the switch T consisting of an nMOS transistor
NI and TN2 are turned on, the latch circuit made up of two central inverters and the bit line are electrically coupled, and the values of BITI and BIT2 are stored in the latch circuit.

The p-channel transistor regions 1 and n shown in FIG.
- The latch circuit 62 shown in FIG. 6 is configured by the channel transistor region 2, and the two n-channel transistors n 3 + n 4 of the n-channel transistor region 3 existing at the end of the n-channel transistor region 2
As a result, the switches TNI and TN2 shown in FIG. 6 are formed.

Therefore, by using the basic cell shown in FIG. 1, it is possible to create an SRAM unit with one basic cell.

As shown in FIG. 3 above, the switch TNI.

n-channel transistor n3+n4 corresponding to TN2
As shown in Fig. 4, using a conventional basic cell without SRA
Multiple pn-channel transistors are wasted when attempting to configure M. On the other hand, if an SRAM is configured using the basic cells shown in Fig. 1, there are no wasted transistors, so a semiconductor integrated circuit using the mask slicing method can be created with improved basic cell usage efficiency. It becomes possible.

In this embodiment, n-channel transistors are used as transistors constituting the switch portion of the SRAM, because n-channel transistors operate faster than p-channel transistors.

In particular, SRAM requires high operating speed, and it is necessary to access and read and write data as quickly as possible. To cope with this, n-channel transistors are used.

The installation position of the n-channel transistor in the switch section for inputting and outputting data in the SRAM is not limited to the embodiment shown in FIG. 1, and other positions may be selected as necessary.

In addition, although the above embodiment describes the case where an SRAM is created using basic cells, a two-man NAND circuit,
There is no problem in using the basic cell according to the present invention to create other logic circuits such as a two-man NOR circuit.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to create an SRAM using one basic cell, which improves the usage efficiency of the basic cell and reduces the area occupied by the storage area on the chip. As a result, the integration density can be increased accordingly, making it possible to obtain a high-performance semiconductor integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a basic cell used in an embodiment of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a plan view of a chip showing a general LSI pattern created by applying the mask slicing method. , FIG. 3 is a plan view showing the specific layout of the basic cell in the conventional example, FIG. 4 is a plan view of an SRAM configured using the basic cell shown in FIG. 3, and FIG. FIG. 6 is a plan view of a basic cell of the present invention in which an SRAM is constructed by applying A1 wiring, and is an equivalent circuit diagram of FIG. 5. In the figure, 1 is a p-channel transistor region, 2°3 is an n
- Channel transistor region, 17 is a bonding pad, 18 is a cell for I10, 9 is a basic cell, and 50 is a basic cell column.

Claims (1)

[Claims] (1) A basic cell row in which a plurality of basic cells in which a p-channel transistor region and an n-channel transistor region are formed as a pair are arranged in a matrix, a plurality of input/output cells, and a plurality of basic cells. A semiconductor integrated circuit comprising a bonding pad, wherein the basic cell further includes an n-channel transistor region.